diff options
| author | Jeremy Soller <jeremy@system76.com> | 2019-07-01 08:14:39 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2019-07-05 12:56:44 +0000 |
| commit | 65f03b7c42152188fbd5ac13cea05aaeb953df31 (patch) | |
| tree | c461a84dafeb5d373f12c01f8465ea0596d19cb0 | |
| parent | c32ccb779c56f7a0256fbad0bba3311b5eba2289 (diff) | |
soc/intel/cannonlake: Fix PMC and GPIO block values for PCH-H
Some of the values used for GPIO_CFG and MISCCFG were not correct,
causing GPEs to not work correctly. This adjusts them according to the
values found in the original ACPI tables for the System76 Gazelle.
Unfortunately, the Intel documentation[1] mentioned below is
also incorrect. I have mentioned this to Intel already. The source
for the Intel CoffeeLake FSP also confirms these new numbers.
This was tested on a System76 Gazelle (gaze14). The EC uses GPP_K3 for
its GPE and GPP_K6 is used for the lid switch GPE. Both function
correctly after applying this change.
[1] Intel Document #572235:
Intel ® 300 Series Chipset Families
Platform Controller Hub
External Design Specification (EDS) - Volume 2 of 2
Change-Id: I4ecc9552468037598ef5d4e10122d660dcbfe71d
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h | 24 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/pmc.h | 19 |
2 files changed, 24 insertions, 19 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h index 5176ac734a..23953142d7 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h @@ -22,18 +22,18 @@ * communities. */ -#define GPP_A 0 -#define GPP_B 1 -#define GPP_C 2 -#define GPP_D 3 -#define GPP_G 4 -#define GPP_K 5 -#define GPP_H 6 -#define GPP_E 7 -#define GPP_F 8 -#define GPP_I 9 -#define GPP_J 0xA -#define GPD 0xC +#define GPP_A 0x0 +#define GPP_B 0x1 +#define GPP_C 0x2 +#define GPP_D 0x3 +#define GPP_G 0x4 +#define GPD 0x5 +#define GPP_E 0x6 +#define GPP_F 0x7 +#define GPP_H 0x8 +#define GPP_K 0x9 +#define GPP_I 0xA +#define GPP_J 0xB #define GPIO_NUM_GROUPS 12 #define GPIO_MAX_NUM_PER_GROUP 24 diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 67854d4cbd..e0d2614e8e 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -117,18 +117,23 @@ #define GPE0_DW_SHIFT(x) (4*(x)) #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) +/* + * The values for GPIO_CFG in Intel Document #572235 are incorrect. + * These values now match what is used by the Intel CoffeeLake FSP, + * please do not modify them. + */ #define PMC_GPP_A 0x0 #define PMC_GPP_B 0x1 #define PMC_GPP_C 0x2 #define PMC_GPP_D 0x3 -#define PMC_GPP_E 0x7 -#define PMC_GPP_F 0x8 +#define PMC_GPP_E 0xA +#define PMC_GPP_F 0xB #define PMC_GPP_G 0x4 -#define PMC_GPP_H 0x6 -#define PMC_GPP_I 0x9 -#define PMC_GPP_J 0xA -#define PMC_GPP_K 0x5 -#define PMC_GPD 0xC +#define PMC_GPP_H 0x9 +#define PMC_GPP_I 0xC +#define PMC_GPP_J 0xD +#define PMC_GPP_K 0x8 +#define PMC_GPD 0x7 #else #define PMC_GPP_A 0x0 #define PMC_GPP_B 0x1 |