rk3288: add iomux operation

BUG=chrome-os-partner:29778
TEST=Build coreboot

Change-Id: Ia19f8084a945992d9f252eb080c6c5c9990ac7de
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 30d02610e8e1e018025c2c1c970fb5b33d67d51b
Original-Change-Id: I8f273f8850e4792ca976bb7c2ed39cbe501401f2
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209461
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8861
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

2 files changed, 178 insertions, 24 deletions

diff --git a/src/soc/rockchip/rk3288/grf.h b/src/soc/rockchip/rk3288/grf.h
index 4b99f4b6bf..547a4c7ee9 100755
--- a/src/soc/rockchip/rk3288/grf.h
+++ b/src/soc/rockchip/rk3288/grf.h
@@ -19,30 +19,41 @@
 
 #ifndef __SOC_ROCKCHIP_RK3288_GRF_H__
 #define __SOC_ROCKCHIP_RK3288_GRF_H__
+
+#include <types.h>
 #include "addressmap.h"
+#include "cpu.h"
 
 struct rk3288_grf_gpio_lh {
 	u32 gpiol;
 	u32 gpioh;
 };
 
-struct rk3288_grf_gpio_pe {
-	u32 gpioa;
-	u32 gpiob;
-	u32 gpioc;
-	u32 gpiod;
-};
-
 struct rk3288_grf_regs {
 	u32 reserved[3];
-	u32 gpio1d_iomux;
+	union {
+		u32 gpio1d_iomux;
+		u32 iomux_lcdc;
+	};
 	u32 gpio2a_iomux;
 	u32 gpio2b_iomux;
-	u32 gpio2c_iomux;
+	union {
+		u32 gpio2c_iomux;
+		u32 iomux_i2c3;
+	};
 	u32 reserved2;
-	u32 gpio3a_iomux;
-	u32 gpio3b_iomux;
-	u32 gpio3c_iomux;
+	union {
+		u32 gpio3a_iomux;
+		u32 iomux_emmcdata;
+	};
+	union {
+		u32 gpio3b_iomux;
+		u32 iomux_emmcpwren;
+	};
+	union {
+		u32 gpio3c_iomux;
+		u32 iomux_emmccmd;
+	};
 	u32 gpio3dl_iomux;
 	u32 gpio3dh_iomux;
 	u32 gpio4al_iomux;
@@ -52,26 +63,71 @@ struct rk3288_grf_regs {
 	u32 gpio4c_iomux;
 	u32 gpio4d_iomux;
 	u32 reserved4;
-	u32 gpio5b_iomux;
+	union {
+		u32 gpio5b_iomux;
+		u32 iomux_spi0;
+	};
 	u32 gpio5c_iomux;
-	u32 gpio6a_iomux;
 	u32 reserved5;
-	u32 gpio6b_iomux;
-	u32 gpio6c_iomux;
+	union {
+		u32 gpio6a_iomux;
+		u32 iomux_i2s;
+	};
+	union {
+		u32 gpio6b_iomux;
+		u32 iomux_i2c2;
+		u32 iomux_i2sclk;
+	};
+	union {
+		u32 gpio6c_iomux;
+		u32 iomux_sdmmc0;
+	};
 	u32 reserved6;
-	u32 gpio7a_iomux;
+	union {
+		u32 gpio7a_iomux;
+		u32 iomux_pwm0;
+	};
 	u32 gpio7b_iomux;
-	u32 gpio7cl_iomux;
-	u32 gpio7ch_iomux;
+	union {
+		u32 gpio7cl_iomux;
+		u32 iomux_i2c5sda;
+		u32 iomux_i2c4;
+	};
+	union {
+		u32 gpio7ch_iomux;
+		u32 iomux_uart2;
+		u32 iomux_i2c5scl;
+	};
 	u32 reserved7;
-	u32 gpio8a_iomux;
-	u32 gpio8b_iomux;
+	union {
+		u32 gpio8a_iomux;
+		u32 iomux_spi2csclk;
+		u32 iomux_i2c1;
+	};
+	union {
+		u32 gpio8b_iomux;
+		u32 iomux_spi2txrx;
+	};
 	u32 reserved8[30];
 	struct rk3288_grf_gpio_lh gpio_sr[8];
-	struct rk3288_grf_gpio_pe gpio_p[8];
-	struct rk3288_grf_gpio_pe gpio_e[8];
+	u32 gpio1_p[8][4];
+	u32 gpio1_e[8][4];
 	u32 gpio_smt;
-	u32 soc_con[15];
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 soc_con2;
+	u32 soc_con3;
+	u32 soc_con4;
+	u32 soc_con5;
+	u32 soc_con6;
+	u32 soc_con7;
+	u32 soc_con8;
+	u32 soc_con9;
+	u32 soc_con10;
+	u32 soc_con11;
+	u32 soc_con12;
+	u32 soc_con13;
+	u32 soc_con14;
 	u32 soc_status[22];
 	u32 reserved9[2];
 	u32 peridmac_con[4];
@@ -100,4 +156,27 @@ struct rk3288_grf_regs {
 check_member(rk3288_grf_regs, soc_con16, 0x3a8);
 
 static struct rk3288_grf_regs * const rk3288_grf = (void *)GRF_BASE;
+static struct rk3288_sgrf_regs * const rk3288_sgrf = (void *)GRF_SECURE_BASE;
+
+#define IOMUX_I2C1	RK_CLRSETBITS(3 << 10 | 3 << 8, 1 << 10 | 1 << 8)
+#define IOMUX_I2C2	RK_SETBITS(1 << 4 | 1 << 2)
+#define IOMUX_I2C3	RK_SETBITS(1 << 2 | 1 << 0)
+#define IOMUX_I2C4	RK_SETBITS(1 << 8 | 1 << 4)
+#define IOMUX_I2C5SDA	RK_CLRSETBITS(3 << 12, 1 << 12)
+#define IOMUX_I2C5SCL	RK_CLRSETBITS(3 << 0, 1 << 0)
+#define IOMUX_SPI0	RK_CLRSETBITS(0xff << 8, 1 << 14 | 1 << 12 | \
+					      1 << 10 | 1 << 8)
+#define IOMUX_SPI2_CSCLK RK_CLRSETBITS(3 << 14 | 3 << 12, 1 << 14 | 1 << 12)
+#define IOMUX_SPI2_TXRX  RK_CLRSETBITS(3 << 2 | 3 << 0, 1 << 2 | 1 << 0)
+#define IOMUX_I2S	RK_SETBITS(1 << 8 | 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0)
+#define IOMUX_I2SCLK	RK_SETBITS(1 << 0)
+#define IOMUX_UART2	RK_CLRSETBITS(7 << 12 | 3 << 8, 1 << 12 | 1 << 8)
+#define IOMUX_LCDC  RK_SETBITS(1 << 6 | 1 << 4 | 1 << 2 | 1 << 0)
+#define IOMUX_SDMMC0 RK_CLRSETBITS(0x17ff, 1 << 12 | 1 << 10 | 1 << 8 |\
+					   1 << 6 | 1 << 4 | 1 << 2 | 1 << 0)
+#define IOMUX_EMMCDATA   RK_CLRSETBITS(0xffff, 2 << 14 | 2 << 12 | 2 << 10 |\
+					       2 << 8 | 2 << 6 | 2 << 4 |\
+					       2 << 2 | 2 << 0)
+#define IOMUX_EMMCPWREN  RK_CLRSETBITS(0x3 << 2, 0x2 << 2)
+#define IOMUX_EMMCCMD	 RK_CLRSETBITS(0x3f, 2 << 4 | 2 << 2 | 2 << 0)
 #endif
diff --git a/src/soc/rockchip/rk3288/pmu.h b/src/soc/rockchip/rk3288/pmu.h
new file mode 100644
index 0000000000..44e5989a4e
--- /dev/null
+++ b/src/soc/rockchip/rk3288/pmu.h
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3288_PMU_H__
+#define __SOC_ROCKCHIP_RK3288_PMU_H__
+#include "addressmap.h"
+
+struct rk3288_pmu_regs {
+	u32 wakeup_cfg[2];
+	u32 pwrdn_con;
+	u32 pwrdn_st;
+	u32 idle_req;
+	u32 idle_st;
+	u32 pwrmode_con;
+	u32 pwr_state;
+	u32 osc_cnt;
+	u32 pll_cnt;
+	u32 stabl_cnt;
+	u32 ddr0io_pwron_cnt;
+	u32 ddr1io_pwron_cnt;
+	u32 core_pwrdn_cnt;
+	u32 core_pwrup_cnt;
+	u32 gpu_pwrdn_cnt;
+	u32 gpu_pwrup_cnt;
+	u32 wakeup_rst_clr_cnt;
+	u32 sft_con;
+	u32 ddr_sref_st;
+	u32 int_con;
+	u32 int_st;
+	u32 boot_addr_sel;
+	u32 grf_con;
+	u32 gpio_sr;
+	u32 gpio0pull[3];
+	u32 gpio0drv[3];
+	u32 gpio_op;
+	u32 gpio0_sel18;
+	u32 gpio0a_iomux;
+	union {
+		u32 gpio0b_iomux;
+		u32 iomux_i2c0sda;
+	};
+	union {
+		u32 gpio0c_iomux;
+		u32 iomux_i2c0scl;
+	};
+	union {
+		u32 gpio0d_iomux;
+		u32 iomux_lcdc0;
+	};
+	u32 sys_reg[4];
+};
+check_member(rk3288_pmu_regs, sys_reg[3], 0x00a0);
+
+static struct rk3288_pmu_regs * const rk3288_pmu = (void *)PMU_BASE;
+
+#define IOMUX_I2C0SDA	1 << 14
+#define IOMUX_I2C0SCL	1 << 0
+
+#endif