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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-04-17 14:00:34 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-27 09:07:43 +0000 |
| commit | 5135f1184df2809e4faeb4ecdcad4bc1cb5af70b (patch) | |
| tree | e6deecf5593037529f32eb5cd418c9aaed7f1b93 | |
| parent | 062c729c9b7a405c42b020480a1a76f24c5cb868 (diff) | |
RISC-V boards: Remove PAGETABLES section from memlayout.ld
RISC-V doesn't set up page tables anymore, since commit b26759d703
("arch/riscv: Don't set up virtual memory").
Change-Id: Id1e759b63fb0bc88ab256994d3849d16814affa0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
| -rw-r--r-- | src/arch/riscv/include/arch/memlayout.h | 1 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-riscv/memlayout.ld | 1 | ||||
| -rw-r--r-- | src/mainboard/emulation/spike-riscv/memlayout.ld | 2 | ||||
| -rw-r--r-- | src/mainboard/lowrisc/nexys4ddr/memlayout.ld | 2 |
4 files changed, 2 insertions, 4 deletions
diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h index 5d011418c4..9097cf5721 100644 --- a/src/arch/riscv/include/arch/memlayout.h +++ b/src/arch/riscv/include/arch/memlayout.h @@ -19,7 +19,6 @@ #define __ARCH_MEMLAYOUT_H #define STACK(addr, size) REGION(stack, addr, size, 4096) -#define PAGETABLES(addr, size) REGION(pagetables, addr, size, 4096) /* TODO: Need to add DMA_COHERENT region like on ARM? */ diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index 8cc6d4126b..615d1f2b72 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -24,6 +24,5 @@ SECTIONS ROMSTAGE(0x20000, 128K) STACK(0x40000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x80000, 8K) - PAGETABLES(0x80000+8K, 60K) RAMSTAGE(0x100000, 16M) } diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index 8596723796..bae414ffd5 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -24,7 +24,7 @@ SECTIONS DRAM_START(START) BOOTBLOCK(START, 64K) STACK(START + 8M, 4K) - PAGETABLES(START + 8M + 4K, 60K) + /* hole at (START + 8M + 4K, 60K) */ ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) RAMSTAGE(START + 8M + 200K, 256K) diff --git a/src/mainboard/lowrisc/nexys4ddr/memlayout.ld b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld index 0348c47366..86f3667556 100644 --- a/src/mainboard/lowrisc/nexys4ddr/memlayout.ld +++ b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld @@ -26,6 +26,6 @@ SECTIONS STACK(START + 8M, 64K) ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) - PAGETABLES(START + 8M + 200K, 56K) + /* hole at (START + 8M + 200K, 56K) */ RAMSTAGE(START + 8M + 256K, 256K) } |