diff options
| author | Daniel Kurtz <djkurtz@chromium.org> | 2019-01-14 14:48:34 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-01-16 18:20:46 +0000 |
| commit | 314094fea6e91a99f1d971c406d871a8b925fbce (patch) | |
| tree | a9998476e243b1d28a6a252e4aa02d4a549f4381 | |
| parent | b82afce18aff24b6e5e3b73a67a6533cc4865a26 (diff) | |
mainboard/google/kahlee: Also configure GPIO_9 in RAM stage
The general rule is to configure GPIOs used by coreboot in bootblock
(using the reset table), and GPIOs used by OS in RAM stage.
However, GPIO_9 will be used as both, and we need to reconfigure it to
properly set up debounce, however, it is no longer possible to change
bootblock, so we also configure it in RAM stage to make the new
debounce configuration take affect.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
BUG=b:113880780
BRANCH=none
TEST=Reboot stress test grunt (>100 times); no messages in dmesg like:
tpm tpm0: Timeout waiting for TPM ready
Change-Id: I0f1bca176ed3f9cebf6b9e9e1008905e492a2f03
Reviewed-on: https://review.coreboot.org/c/30922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
| -rw-r--r-- | src/mainboard/google/kahlee/variants/baseboard/gpio.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index e9ae28c25b..399c78c162 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -117,6 +117,9 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { /* GPIO_8 - DDR_ALERT_3V3_L (currently not used) */ PAD_GPI(GPIO_8, PULL_UP), + /* GPIO_9 - H1_PCH_INT_ODL, SCI */ + PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW), + /* GPIO_10 - SLP_S0_L (currently not used) */ PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP), |