diff options
| author | Martin Roth <martin.roth@se-eng.com> | 2014-06-20 21:10:09 -0600 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-06-23 05:48:34 +0200 |
| commit | 2c28ee83cb00af16fe48d72133e668291b1d2a04 (patch) | |
| tree | 993cba2cd3957c8c1c0397de73fd5b17b5702496 | |
| parent | a173a6255b5c3b7febea5cdf581fc3a57299954a (diff) | |
bayleybay_fsp: Add comments for the MMC/SD devices in devicetree
This just adds some additional comments for the EMMC / SD / SDIO PCI
devices in devicetree.
The documentation states that the EMMC 4.1 device shouldn't be used,
but it's available to enable in the FSP. Because it can be enabled,
I've included it in the devicetree even though its use is discouraged.
Change-Id: I64633fe1908368f69a8d4031aa900b0bceb2189e
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6089
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
| -rw-r--r-- | src/mainboard/intel/bayleybay_fsp/devicetree.cb | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/intel/bayleybay_fsp/devicetree.cb b/src/mainboard/intel/bayleybay_fsp/devicetree.cb index cfc71ab570..1bde834c20 100644 --- a/src/mainboard/intel/bayleybay_fsp/devicetree.cb +++ b/src/mainboard/intel/bayleybay_fsp/devicetree.cb @@ -46,14 +46,14 @@ chip soc/intel/fsp_baytrail device pci 02.0 on end # 8086 0F31 - GFX device pci 03.0 off end # 8086 0F38 - MIPI - camera interface - device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port - device pci 11.0 on end # 8086 0F15 - SDIO Port - device pci 12.0 on end # 8086 0F16 - SD Port + device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time + device pci 11.0 on end # 8086 0F15 - SDIO Port (SD2 pins) + device pci 12.0 on end # 8086 0F16 - SD Port (SD3 pins) device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23) device pci 14.0 off end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time device pci 15.0 off end # 8086 0F28 - LP Engine Audio device pci 16.0 off end # 8086 0F37 - OTG controller - device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port + device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time device pci 18.0 on end # 8086 0F40 - SIO - DMA device pci 18.1 on end # 8086 0F41 - I2C Port 1 device pci 18.2 on end # 8086 0F42 - I2C Port 2 |