AGESA f15 boards: Remove - using LATE_CBMEM_INIT

Boards that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. Removed boards: amd/dinar tyan/s2886 supermicro/h8scm supermicro/h8qgi Change-Id: I16be3b43fc0c48d58ed8b6667880c9571c6f5510 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
author: Kyösti Mälkki <kyosti.malkki@gmail.com> 2017-09-26 13:13:23 +0300
committer: Kyösti Mälkki <kyosti.malkki@gmail.com> 2018-01-17 13:23:33 +0000
commit: 2bd6939dc5d2542e28734fa92aad6382535b8604 (patch)
tree: add236d8ffb48792ba18e57ed2057e96919f577e
parent: 9e3ba212f34c6d9f2eb7dac8e4651f8ce12ab0c0 (diff)
106 files changed, 0 insertions, 21936 deletions
diff --git a/src/cpu/amd/agesa/family15/fixme.c b/src/cpu/amd/agesa/family15/fixme.c
index f88cdb7242..bf791b521f 100644
--- a/src/cpu/amd/agesa/family15/fixme.c
+++ b/src/cpu/amd/agesa/family15/fixme.c
@@ -47,7 +47,6 @@ MsrWrite (
 	__writemsr (MsrAddress, Value);
 }
 
-#if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
 void amd_initcpuio(void)
 {
 	UINT32			PciData;
@@ -137,126 +136,6 @@ void amd_initcpuio(void)
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	}
 }
-#else
-
-#define MMIO_NP_BIT		BIT7
-
-void amd_initcpuio(void)
-{
-	UINT64 MsrReg;
-	UINT32 PciData;
-	PCI_ADDR PciAddress;
-	AMD_CONFIG_PARAMS StdHeader;
-	UINT32 TopMem;
-	UINT32 nodes;
-	UINT32 node;
-	UINT32 SbLink;
-	UINT32 i;
-
-	/* get the number of coherent nodes in the system */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x60);
-	LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	nodes = ((PciData >> 4) & 7) + 1;	//nodes[6:4]
-	/* Find out the Link ID of Node0 that connects to the
-	 * Southbridge (system IO hub). e.g. family10 MCM Processor,
-	 * SbLink is Processor0 Link2, internal Node0 Link3
-	 */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x64);
-	LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	SbLink = (PciData >> 8) & 3;	//assume ganged
-	/* Enable MMIO on AMD CPU Address Map Controller for all nodes */
-	for (node = 0; node < nodes; node++) {
-		/* clear all MMIO Mapped Base/Limit Registers */
-		for (i = 0; i < 8; i++) {
-			PciData = 0x00000000;
-			PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i * 8);
-			LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-			PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i * 8);
-			LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		}
-		/* clear all IO Space Base/Limit Registers */
-		for (i = 0; i < 4; i++) {
-			PciData = 0x00000000;
-			PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i * 8);
-			LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-			PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i * 8);
-			LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		}
-
-		/* Enable MMIO on AMD CPU Address Map Controller */
-
-		/* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80);
-		PciData = (0xA0000 >> 8) | 3;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84);
-		PciData = 0xB0000 >> 8;
-		PciData &= (~0xFF);
-		PciData |= SbLink << 4;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-		/* Set UMA MMIO. */
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88);
-		LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
-		TopMem = (UINT32) MsrReg;
-		MsrReg = (MsrReg >> 8) | 3;
-		PciData = (UINT32) MsrReg;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8c);
-		if (TopMem <= CONFIG_MMCONF_BASE_ADDRESS) {
-			PciData = (CONFIG_MMCONF_BASE_ADDRESS - 1) >> 8;
-		} else {
-			PciData = (0x100000000ull - 1) >> 8;
-		}
-		PciData &= (~0xFF);
-		PciData |= SbLink << 4;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-		/* Set PCIE MMIO. */
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x90);
-		PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 3;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x94);
-		PciData = ((CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 * 256 - 1) >> 8) & (~0xFF);
-		PciData &= (~0xFF);
-		PciData |= MMIO_NP_BIT;
-		PciData |= SbLink << 4;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-		/* Set XAPIC MMIO. 24K */
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x98);
-		PciData = (0xFEC00000 >> 8) | 3;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x9c);
-		PciData = ((0xFEC00000 + 6 * 4096 - 1) >> 8);
-		PciData &= (~0xFF);
-		PciData |= MMIO_NP_BIT;
-		PciData |= SbLink << 4;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-		/* Set Local APIC MMIO. 4K*4= 16K, Llano CPU are 4 cores */
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xA0);
-		PciData = (0xFEE00000 >> 8) | 3;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xA8);
-		PciData = (0xFEE00000 + 4 * 4096 - 1) >> 8;
-		PciData &= (~0xFF);
-		PciData |= MMIO_NP_BIT;
-		PciData |= SbLink << 4;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-		/* Set PCIO: 0x0 - 0xFFF000  and enabled VGA IO */
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0);
-		PciData = 0x13;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4);
-		PciData = 0x00FFF000;
-		PciData &= (~0x7F);
-		PciData |= SbLink << 4;
-		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	}
-}
-#endif
 
 void amd_initmmio(void)
 {
@@ -270,28 +149,6 @@ void amd_initmmio(void)
 	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
 	LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
 
-#if IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
-	UINT32 PciData;
-	PCI_ADDR PciAddress;
-
-	/* Set PCIE MMIO. */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x94);
-	/* FIXME: LSB bits are not cleared for PciData. */
-	PciData = ((CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 * 256 - 1) >> 8) | MMIO_NP_BIT;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x90);
-	PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 3;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* Enable memory access */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
-	LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
-	PciData |= BIT1;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
-	LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
-#endif
-
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000 - CACHE_ROM_SIZE) | 5;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c
deleted file mode 100644
index d7cffd153f..0000000000
--- a/src/mainboard/amd/dinar/BiosCallOuts.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include "SB700.h"
-#include "OEM.h"		/* SMBUS0_BASE_ADDRESS */
-#include <stdlib.h>
-
-#include <southbridge/amd/cimx/sb700/smbus_spd.h>
-
-#ifdef __PRE_RAM__
-/* This define is used when selecting the appropriate socket for the SPD read
- * because this is a multi-socket design.
- */
-#define LTC4305_SMBUS_ADDR    (0x94)
-
-static void select_socket(UINT8 socket_id)
-{
-	AMD_CONFIG_PARAMS StdHeader;
-	UINT32            PciData32;
-	UINT8             PciData8;
-	PCI_ADDR          PciAddress;
-
-	/* Set SMBus MMIO. */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90);
-	PciData32 = (SMBUS0_BASE_ADDRESS & 0xFFFFFFF0) | BIT0;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader);
-
-	/* Enable SMBus MMIO. */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2);
-	LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader);
-	PciData8 |= BIT0;
-	LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader);
-
-	switch (socket_id) {
-	case 0:
-		/* Switch onto the First CPU Socket SMBus */
-		writeSmbusByte(SMBUS0_BASE_ADDRESS, LTC4305_SMBUS_ADDR, 0x80, 0x03);
-		break;
-	case 1:
-		/* Switch onto the Second CPU Socket SMBus */
-		writeSmbusByte(SMBUS0_BASE_ADDRESS, LTC4305_SMBUS_ADDR, 0x40, 0x03);
-		break;
-	default:
-		/* Switch off two CPU Sockets SMBus */
-		writeSmbusByte(SMBUS0_BASE_ADDRESS, LTC4305_SMBUS_ADDR, 0x00, 0x03);
-		break;
-	}
-}
-
-static void restore_socket(void)
-{
-	/* Switch off two CPU Sockets SMBus */
-	writeSmbusByte(SMBUS0_BASE_ADDRESS, LTC4305_SMBUS_ADDR, 0x00, 0x03);
-}
-#endif
-
-static AGESA_STATUS board_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			board_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_GNB_PCIE_SLOT_RESET,		agesa_NoopSuccess },
-	{AGESA_GET_IDS_INIT_DATA,		agesa_EmptyIdsInitData },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,	agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-
-static AGESA_STATUS board_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS Status;
-#ifdef __PRE_RAM__
-	if (ConfigPtr == NULL)
-		return AGESA_ERROR;
-
-	select_socket(((AGESA_READ_SPD_PARAMS *)ConfigPtr)->SocketId);
-
-	Status = agesa_ReadSpd (Func, Data, ConfigPtr);
-
-	restore_socket();
-#else
-	Status = AGESA_UNSUPPORTED;
-#endif
-
-	return Status;
-}
diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig
deleted file mode 100644
index 02a6987b25..0000000000
--- a/src/mainboard/amd/dinar/Kconfig
+++ /dev/null
@@ -1,136 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-if BOARD_AMD_DINAR
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select AGESA_LEGACY
-	select CPU_AMD_AGESA_FAMILY15
-	select CPU_AMD_SOCKET_G34
-	select NORTHBRIDGE_AMD_AGESA_FAMILY15
-	select NORTHBRIDGE_AMD_CIMX_RD890
-	select SOUTHBRIDGE_AMD_CIMX_SB700
-	select SUPERIO_SMSC_SIO1036
-	select SUPERIO_SMSC_SCH4037
-	select BOARD_ROMSIZE_KB_2048
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select HAVE_ACPI_TABLES
-	select ENABLE_APIC_EXT_ID
-	select GFXUMA
-
-config MAINBOARD_DIR
-	string
-	default amd/dinar
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Dinar"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 64
-
-config HW_MEM_HOLE_SIZE_AUTO_INC
-	bool
-	default n
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config VGA_BIOS
-	bool
-	default n
-
-config VGA_BIOS_ID
-	depends on VGA_BIOS
-	default "1002,515e"
-
-config AHCI_BIOS
-	bool
-	default y
-
-config AHCI_BIOS_FILE
-	string "AHCI ROM path and filename"
-	depends on AHCI_BIOS
-	default "site-local/ahci/sb700.bin"
-
-config AHCI_BIOS_ID
-	string "AHCI device PCI IDs"
-	depends on AHCI_BIOS
-	default "1002,4391"
-
-config XHC_BIOS
-	bool
-	default n
-
-config XHC_BIOS_FILE
-	string "XHC BIOS path and filename"
-	depends on XHC_BIOS
-	default "site-local/xhc/Xhc.rom"
-
-config XHC_BIOS_ID
-	string "XHC device PCI IDs"
-	depends on XHC_BIOS
-	default "1022,7812"
-
-config SATA_CONTROLLER_MODE
-	hex
-	default 0x0
-
-config ONBOARD_LAN
-	bool
-	default y
-
-config ONBOARD_1394
-	bool
-	default y
-
-config ONBOARD_USB30
-	bool
-	default n
-
-config ONBOARD_BLUETOOTH
-	bool
-	default y
-
-config ONBOARD_WEBCAM
-	bool
-	default y
-
-config ONBOARD_TRAVIS
-	bool
-	default y
-
-config ONBOARD_LIGHTSENSOR
-	bool
-	default n
-
-config REDIRECT_CIMX_TRACE_TO_SERIAL
-	bool "Redirect CIMX Trace to serial console"
-	default y
-
-endif # BOARD_AMD_DINAR
diff --git a/src/mainboard/amd/dinar/Kconfig.name b/src/mainboard/amd/dinar/Kconfig.name
deleted file mode 100644
index b3434c1bc6..0000000000
--- a/src/mainboard/amd/dinar/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_AMD_DINAR
-	bool "Dinar"
diff --git a/src/mainboard/amd/dinar/Makefile.inc b/src/mainboard/amd/dinar/Makefile.inc
deleted file mode 100644
index d7a5da6a59..0000000000
--- a/src/mainboard/amd/dinar/Makefile.inc
+++ /dev/null
@@ -1,30 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += sb700_cfg.c
-romstage-y += rd890_cfg.c
-romstage-y += OemCustomize.c
-
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += sb700_cfg.c
-ramstage-y += rd890_cfg.c
-ramstage-y += OemCustomize.c
-
-AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa
-AGESA_ROOT ?= $(AGESA_PREFIX)/$(if $(CONFIG_CPU_AMD_AGESA_FAMILY15),f15,\
-		echo `wrong configuration`)
diff --git a/src/mainboard/amd/dinar/OemCustomize.c b/src/mainboard/amd/dinar/OemCustomize.c
deleted file mode 100644
index 1a36324dba..0000000000
--- a/src/mainboard/amd/dinar/OemCustomize.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <PlatformMemoryConfiguration.h>
-
-/*----------------------------------------------------------------------------------------
- *                        CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *  use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
-	//      Dinar has the following routing:
-	//           CS0   M[B,A]_CLK_H/L[0]
-	//           CS1   M[B,A]_CLK_H/L[2]
-	//           CS2   M[B,A]_CLK_H/L[1]
-	//           CS3   M[B,A]_CLK_H/L[3]
-	MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x01, 0x04, 0x02, 0x08, 0x00, 0x00),
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
-	PSO_END
-};
-
-
-static AGESA_STATUS OemInitPost(AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.UmaMode = UMA_AUTO;
-	InitPost->MemConfig.BottomIo = 0xE0;
-	InitPost->MemConfig.UmaSize = 0xE0-0xC0;
-	return AGESA_SUCCESS;
-}
-
-const struct OEM_HOOK OemCustomize = {
-	.InitPost = OemInitPost,
-};
diff --git a/src/mainboard/amd/dinar/OptionsIds.h b/src/mainboard/amd/dinar/OptionsIds.h
deleted file mode 100644
index d1d184d941..0000000000
--- a/src/mainboard/amd/dinar/OptionsIds.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDS_DEBUG_PORT
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-//#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-
-//#define IDSOPT_DEBUG_ENABLED  FALSE
-//#undef IDSOPT_HOST_SIMNOW
-//#define IDSOPT_HOST_SIMNOW    FALSE
-//#undef IDSOPT_HOST_HDT
-//#define IDSOPT_HOST_HDT       FALSE
-//#define IDS_DEBUG_PORT    0x80
-
-#endif
diff --git a/src/mainboard/amd/dinar/acpi/ide.asl b/src/mainboard/amd/dinar/acpi/ide.asl
deleted file mode 100644
index f50d9a37bb..0000000000
--- a/src/mainboard/amd/dinar/acpi/ide.asl
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(IDEC) {
-			Name(_ADR, 0x00140001)
-			#include "ide.asl"
-		}
-	}
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
-	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
-	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
-	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
-	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
-	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
-	Field(ICRG, AnyAcc, NoLock, Preserve)
-{
-	PPTS, 8,	/* Primary PIO Slave Timing */
-	PPTM, 8,	/* Primary PIO Master Timing */
-	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
-	PMTM, 8,	/* Primary MWDMA Master Timing */
-	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
-	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
-	PPSM, 4,	/* Primary PIO slave Mode */
-	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
-	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
-	PDSM, 4,	/* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
-	Store(And(Arg0, 0x0F), Local0)	/* Recovery Width */
-	Increment(Local0)
-	Store(ShiftRight(Arg0, 4), Local1)	/* Command Width */
-	Increment(Local1)
-	Return(Multiply(30, Add(Local0, Local1)))
-}
-
-Device(PRID)
-{
-	Name (_ADR, Zero)
-	Method(_GTM, 0)
-	{
-		NAME(OTBF, Buffer(20) { /* out buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
-		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
-		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
-		/* Just return if the channel is disabled */
-		If(And(PPCR, 0x01)) { /* primary PIO control */
-			Return(OTBF)
-		}
-
-		/* Always tell them independent timing available and IOChannelReady used on both drives */
-		Or(BFFG, 0x1A, BFFG)
-
-		Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming  to PIO spd0 */
-		Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing  to PIO spd1 */
-
-		If(And(PDCR, 0x01)) {	/* It's under UDMA mode */
-			Or(BFFG, 0x01, BFFG)
-			Store(DerefOf(Index(UDTT, PDMM)), DSD0)
-		}
-		Else {
-			Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing,  DmaSpd0 */
-		}
-
-		If(And(PDCR, 0x02)) {	/* It's under UDMA mode */
-			Or(BFFG, 0x04, BFFG)
-			Store(DerefOf(Index(UDTT, PDSM)), DSD1)
-		}
-		Else {
-			Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing,  DmaSpd0 */
-		}
-
-		Return(OTBF) /* out buffer */
-	}				/* End Method(_GTM) */
-
-	Method(_STM, 3, NotSerialized)
-	{
-		NAME(INBF, Buffer(20) { /* in buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
-		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
-		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
-		Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
-		Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
-		Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
-		Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
-
-		Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
-		Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
-
-		If(And(BFFG, 0x01)) {	/* Drive 0 is under UDMA mode */
-			Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
-			Divide(Local0, 7, PDMM,)
-			Or(PDCR, 0x01, PDCR)
-		}
-		Else {
-			If(LNotEqual(DSD0, 0xFFFFFFFF)) {
-				Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
-				Store(DerefOf(Index(MDRT, Local0)), PMTM)
-			}
-		}
-
-		If(And(BFFG, 0x04)) {	/* Drive 1 is under UDMA mode */
-			Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
-			Divide(Local0, 7, PDSM,)
-			Or(PDCR, 0x02, PDCR)
-		}
-		Else {
-			If(LNotEqual(DSD1, 0xFFFFFFFF)) {
-				Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
-				Store(DerefOf(Index(MDRT, Local0)), PMTS)
-			}
-		}
-		/* Return(INBF) */
-	}		/*End Method(_STM) */
-	Device(MST)
-	{
-		Name(_ADR, 0)
-		Method(_GTF) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			Store(0xA0, CMDA)
-			Store(0xA0, CMDB)
-			Store(0xA0, CMDC)
-
-			Or(PPMM, 0x08, POMD)
-
-			If(And(PDCR, 0x01)) {
-				Or(PDMM, 0x40, DMMD)
-			}
-			Else {
-				Store(Match
-				      (MDTT, MLE, GTTM(PMTM),
-				       MTR, 0, 0), Local0)
-				If(LLess(Local0, 3)) {
-					Or(0x20, Local0, DMMD)
-				}
-			}
-			Return(CMBF)
-		}
-	}		/* End Device(MST) */
-
-	Device(SLAV)
-	{
-		Name(_ADR, 1)
-		Method(_GTF) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			Store(0xB0, CMDA)
-			Store(0xB0, CMDB)
-			Store(0xB0, CMDC)
-
-			Or(PPSM, 0x08, POMD)
-
-			If(And(PDCR, 0x02)) {
-				Or(PDSM, 0x40, DMMD)
-			}
-			Else {
-				Store(Match
-				      (MDTT, MLE, GTTM(PMTS),
-				       MTR, 0, 0), Local0)
-				If(LLess(Local0, 3)) {
-					Or(0x20, Local0, DMMD)
-				}
-			}
-			Return(CMBF)
-		}
-	}			/* End Device(SLAV) */
-}
diff --git a/src/mainboard/amd/dinar/acpi/routing.asl b/src/mainboard/amd/dinar/acpi/routing.asl
deleted file mode 100644
index 1839c9191b..0000000000
--- a/src/mainboard/amd/dinar/acpi/routing.asl
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
-		)
-	{
-		#include "routing.asl"
-	}
-*/
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, INTC, 0 },
-		Package(){0x0001FFFF, 1, INTD, 0 },
-		/* Bus 0, Dev 2 - */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - */
-		Package(){0x0003FFFF, 0, INTD, 0 },
-		Package(){0x0003FFFF, 1, INTA, 0 },
-		Package(){0x0003FFFF, 2, INTB, 0 },
-		Package(){0x0003FFFF, 3, INTC, 0 },
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, INTB, 0 },
-		Package(){0x0005FFFF, 1, INTC, 0 },
-		Package(){0x0005FFFF, 2, INTD, 0 },
-		Package(){0x0005FFFF, 3, INTA, 0 },
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		/* SB devices */
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI */
-		Package(){0x0012FFFF, 0, INTC, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-		Package(){0x0010FFFF, 0, INTC, 0 },
-		Package(){0x0010FFFF, 1, INTB, 0 },
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-		/* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, 0, 18 },
-		Package(){0x0001FFFF, 1, 0, 19 },
-		/* Bus 0, Dev 2 */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		Package(){0x0002FFFF, 1, 0, 19 },
-		Package(){0x0002FFFF, 2, 0, 16 },
-		Package(){0x0002FFFF, 3, 0, 17 },
-		/* Bus 0, Dev 3 */
-		Package(){0x0003FFFF, 0, 0, 19 },
-		Package(){0x0003FFFF, 1, 0, 16 },
-		Package(){0x0003FFFF, 2, 0, 17 },
-		Package(){0x0003FFFF, 3, 0, 18 },
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, 0, 17 },
-		Package(){0x0005FFFF, 1, 0, 18 },
-		Package(){0x0005FFFF, 2, 0, 19 },
-		Package(){0x0005FFFF, 3, 0, 16 },
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package(){0x0006FFFF, 0, 0, 18 },
-		Package(){0x0006FFFF, 1, 0, 19 },
-		Package(){0x0006FFFF, 2, 0, 16 },
-		Package(){0x0006FFFF, 3, 0, 17 },
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		Package(){0x0007FFFF, 0, 0, 19 },
-		Package(){0x0007FFFF, 1, 0, 16 },
-		Package(){0x0007FFFF, 2, 0, 17 },
-		Package(){0x0007FFFF, 3, 0, 18 },
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI*/
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-		Package(){0x0010FFFF, 0, 0, 18 },
-		Package(){0x0010FFFF, 1, 0, 17 },
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		Package(){0x0011FFFF, 0, 0, 19 },
-		/* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-	})
-
-	Name(PS2, Package(){
-		/* For Device(PBR2) PIC mode*/
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-
-	Name(APS2, Package(){
-		/* For Device(PBR2) APIC mode*/
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS3, Package(){
-		/* For Device(PBR3) PIC mode*/
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-
-	Name(APS3, Package(){
-		/* For Device(PBR3) APIC mode*/
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PS4, Package(){
-		/* For Device(PBR4) PIC mode*/
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-
-	Name(APS4, Package(){
-		/* For Device(PBR4) APIC mode*/
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* For Device(PBR5) PIC mode*/
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-
-	Name(APS5, Package(){
-		/* For Device(PBR5) APIC mode*/
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* For Device(PBR6) PIC mode*/
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-
-	Name(APS6, Package(){
-		/* For Device(PBR6) APIC mode*/
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* For Device(PBR7) PIC mode*/
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-
-	Name(APS7, Package(){
-		/* For Device(PBR7) APIC mode*/
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PE0, Package(){
-		/* For Device(PE20) PIC mode*/
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-
-	Name(APE0, Package(){
-		/* For Device(PE20) APIC mode*/
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* For Device(PE21) PIC mode*/
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-
-	Name(APE1, Package(){
-		/* For Device(PE21) APIC mode*/
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* For Device(PE22) PIC mode*/
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-
-	Name(APE2, Package(){
-		/* For Device(PE22) APIC mode*/
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* For Device(PE23) PIC mode*/
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-
-	Name(APE3, Package(){
-		/* For Device(PE23) APIC mode*/
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-}
diff --git a/src/mainboard/amd/dinar/acpi/sata.asl b/src/mainboard/amd/dinar/acpi/sata.asl
deleted file mode 100644
index 3eebe12a88..0000000000
--- a/src/mainboard/amd/dinar/acpi/sata.asl
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (LGreater(P0IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (LGreater(P1IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (LGreater(P2IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (LGreater(P3IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (LGreater(\_SB.P0IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P0PR)
-		}
-
-		if (\_SB.P1PR) {
-			if (LGreater(\_SB.P1IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P1PR)
-		}
-
-		if (\_SB.P2PR) {
-			if (LGreater(\_SB.P2IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P2PR)
-		}
-
-		if (\_SB.P3PR) {
-			if (LGreater(\_SB.P3IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P3PR)
-		}
-	}
-}
diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c
deleted file mode 100644
index ec6c41fa3c..0000000000
--- a/src/mainboard/amd/dinar/acpi_tables.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <arch/ioapic.h>
-#include <arch/io.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	device_t dev;
-	u32 dword;
-	u32 gsi_base = 0;
-	u32 apicid_sb700;
-	u32 apicid_rd890;
-
-	/*
-	 * AGESA v5 Apply apic enumeration rules
-	 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
-	 * put the local-APICs at m..z
-	 * For systems with < 16 APICs, put the Local-APICs at 0..n and
-	 * put the IO-APICs at (n + 1)..z
-	 */
-	if (CONFIG_MAX_CPUS >= 16)
-		apicid_sb700 = 0x0;
-	else
-		apicid_sb700 = CONFIG_MAX_CPUS + 1;
-	apicid_rd890 = apicid_sb700 + 1;
-
-	/* create all subtables for processors */
-	current = acpi_create_madt_lapics(current);
-
-	/* Write sb700 IOAPIC, only one */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-			apicid_sb700,
-			IO_APIC_ADDR,
-			0
-			);
-
-	/* IOAPIC on rs5690 */
-	gsi_base += IO_APIC_INTERRUPTS;  /* sb700 has 24 IOAPIC entries. */
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-	if (dev) {
-		pci_write_config32(dev, 0xF8, 0x1);
-		dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
-		current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				apicid_rd890,
-				dword,
-				gsi_base
-				);
-	}
-
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current,
-			0, //BUS
-			0, //SOURCE
-			2, //gsirq
-			0  //flags
-			);
-
-	/* 0: mean bus 0--->ISA */
-	/* 0: PIC 0 */
-	/* 2: APIC 2 */
-	/* 5 mean: 0101 --> Edge-triggered, Active high */
-
-	/* create all subtables for processors */
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
-	/* 1: LINT1 connect to NMI */
-
-	return current;
-}
diff --git a/src/mainboard/amd/dinar/board_info.txt b/src/mainboard/amd/dinar/board_info.txt
deleted file mode 100644
index b351b8e696..0000000000
--- a/src/mainboard/amd/dinar/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: eval
diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c
deleted file mode 100644
index 853a240203..0000000000
--- a/src/mainboard/amd/dinar/buildOpts.c
+++ /dev/null
@@ -1,381 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/**
- * @file
- *
- * AMD User options selection for a Sabine/Lynx platform solution system
- *
- * This file is placed in the user's platform directory and contains the
- * build option selections desired for that platform.
- *
- */
-#include <stdlib.h>
-#include "AGESA.h"
-//#define OPTION_HW_DQS_REC_EN_TRAINING TRUE
-/* AGESA will check the OEM configuration during preprocessing stage,
- * coreboot enable -Wundef option, so we should make sure we have all contanstand defined
- */
-/* MEMORY_BUS_SPEED */
-#define DDR400_FREQUENCY		200	///< DDR 400
-#define DDR533_FREQUENCY		266	///< DDR 533
-#define DDR667_FREQUENCY		333	///< DDR 667
-#define DDR800_FREQUENCY		400	///< DDR 800
-#define DDR1066_FREQUENCY		533	///< DDR 1066
-#define DDR1333_FREQUENCY		667	///< DDR 1333
-#define DDR1600_FREQUENCY		800	///< DDR 1600
-#define DDR1866_FREQUENCY		933	///< DDR 1866
-#define UNSUPPORTED_DDR_FREQUENCY	934	///< Highest limit of DDR frequency
-
-/* QUANDRANK_TYPE */
-#define QUADRANK_REGISTERED		0	///< Quadrank registered DIMM
-#define QUADRANK_UNBUFFERED		1	///< Quadrank unbuffered DIMM
-
-/* USER_MEMORY_TIMING_MODE */
-#define TIMING_MODE_AUTO		0	///< Use best rate possible
-#define TIMING_MODE_LIMITED		1	///< Set user top limit
-#define TIMING_MODE_SPECIFIC		2	///< Set user specified speed
-
-/* POWER_DOWN_MODE */
-#define POWER_DOWN_BY_CHANNEL		0	///< Channel power down mode
-#define POWER_DOWN_BY_CHIP_SELECT	1	///< Chip select power down mode
-
-/*  Select the CPU family.  */
-
-
-/*  Select the CPU socket type.  */
-#define INSTALL_G34_SOCKET_SUPPORT  TRUE
-#define INSTALL_C32_SOCKET_SUPPORT  FALSE
-#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
-#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
-#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
-#define INSTALL_FS1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FP1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FT1_SOCKET_SUPPORT  FALSE
-#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
-
-/*
- * Agesa optional capabilities selection.
- * Uncomment and mark FALSE those features you wish to include in the build.
- * Comment out or mark TRUE those features you want to REMOVE from the build.
- */
-
-/* User makes option selections here
- * Comment out the items wanted to be included in the build.
- * Uncomment those items you with to REMOVE from the build.
- */
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
-//#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
-//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
-//#define BLDOPT_REMOVE_DDR3_SUPPORT             TRUE
-//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT      TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES             TRUE
-//#define BLDOPT_REMOVE_SRAT                     TRUE
-//#define BLDOPT_REMOVE_SLIT                     TRUE
-#define BLDOPT_REMOVE_WHEA                     TRUE
-//#define BLDOPT_REMOVE_DMI                      TRUE
-#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
-//#define BLDOPT_REMOVE_FAMILY_15_SUPPORT          TRUE
-/* Build configuration values here.
-*/
-#define BLDCFG_VRM_CURRENT_LIMIT                 120000
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD           0
-#define BLDCFG_PLAT_NUM_IO_APICS                 2
-#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
-#define BLDCFG_MEM_INIT_PSTATE                   0
-#define BLDCFG_AMD_PSTATE_CAP_VALUE              0
-
-#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_SERVER
-
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1600_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
-#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
-#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_REGISTERED
-#define BLDCFG_MEMORY_RDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE              FALSE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    TRUE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
-#define BLDCFG_MEMORY_POWER_DOWN                  TRUE
-#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT  //FALSE
-#define BLDCFG_ONLINE_SPARE                       TRUE
-#define BLDCFG_MEMORY_PARITY_ENABLE               TRUE
-#define BLDCFG_BANK_SWIZZLE                       TRUE
-#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR800_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
-#define BLDCFG_USE_BURST_MODE                     FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON               TRUE
-#define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
-#define BLDCFG_ECC_REDIRECTION                    TRUE
-#define BLDCFG_SCRUB_IC_RATE                      0
-#define BLDCFG_ECC_SYNC_FLOOD                     TRUE
-#define BLDCFG_ECC_SYMBOL_SIZE                    0
-#define BLDCFG_1GB_ALIGN                          FALSE
-#define BLDCFG_PLATFORM_C1E_MODE                  C1eModeMsgBased
-#define BLDCFG_PLATFORM_C1E_OPDATA                0x2000
-//#define BLDCFG_USE_ATM_MODE                       TRUE
-
-#define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeC6
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0xCB0
-#define BLDCFG_PLATFORM_POWER_POLICY_MODE	  Performance  //BatteryLife
-//#define BLDCFG_PLATFORM_CSTATE_MODE                  CStateModeMsgBasedC1e
-//#define BLDCFG_PLATFORM_CSTATE_OPDATA                0x2000
-
-//#define IDSOPT_IDS_ENABLED                        TRUE
-#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
-#define BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT	TRUE
-#define BLDCFG_PSTATE_HPC_MODE                    FALSE
-
-#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap
-/*  Process the options...
- * This file include MUST occur AFTER the user option selection settings
- */
-
-
-/*****************************************************************************
- *   Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
-// This is the delivery package title, "MarG34PI"
-// This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING  {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
-
-// This is the release version number of the AGESA component
-// This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '9', '.', '0', ' ', ' ', ' ', ' '}
-
-// The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket.
-#define INSTALL_G34_SOCKET_SUPPORT           TRUE
-#define INSTALL_FAMILY_10_SUPPORT            TRUE
-#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT   TRUE
-
-#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
-#if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
-#undef INSTALL_FAMILY_10_SUPPORT
-#define INSTALL_FAMILY_10_SUPPORT     FALSE
-#endif
-#endif
-
-#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
-#if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
-#undef INSTALL_FAMILY_15_MODEL_0x_SUPPORT
-#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT     FALSE
-#endif
-#endif
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file.  The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE            (0xFF)
-#define DFLT_SCRUB_L2_RATE              (0x10)
-#define DFLT_SCRUB_L3_RATE              (0x10)
-#define DFLT_SCRUB_IC_RATE              (0)
-#define DFLT_SCRUB_DC_RATE              (0x12)
-#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE              (2500)
-
-/*  Process the options...
- * This file include MUST occur
- AFTER the user option selection settings
- */
-CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] =
-{
-	{
-		/* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-
-		{ //BUID Swap List
-			{ //BUID Swaps
-				/* Each Non-coherent chain may have a list of device swaps,
-				 * Each item specify a device will be swap from its current id to a new one
-				 */
-				/* FromID 0x00 is the chain with the southbridge */
-				/* 'Move' device zero to device zero, All others are non applicable */
-				{0x00, 0x00}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-			},
-
-			{ //The ordered final BUIDs
-				/* Specify the final BUID to be zero, All others are non applicable */
-				0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-				0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-				0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-				0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-			}
-		}
-	},
-
-	/* The 2nd element in the array merely terminates the list */
-	{
-		HT_LIST_TERMINAL,
-	}
-};
-
-#define BLDCFG_BUID_SWAP_LIST &MaranelloManualBuidSwapList
-
-// And another platform specific one ...
-//CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[2] =
-//{
-//  HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-//  HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M,
-//  HT_LIST_TERMINAL
-//};
-
-CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] =
-{
-	{
-		/* On the reference platform, these settings apply to all coherent links */
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-
-		/* Set incoming and outgoing links to 16 bit widths, and 3.2GHz frequencies */
-		HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M,
-	},
-
-	{
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK,
-		HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M,
-	},
-
-	/* The 2nd element in the array merely terminates the list */
-	{
-		HT_LIST_TERMINAL,
-	}
-};
-
-#define BLDCFG_HTFABRIC_LIMITS_LIST &MaranelloCpuToCpuLimitList
-
-// A performance-per-watt optimization.
-CONST SKIP_REGANG ROMDATA PerfPerWatt[] = {
-	{ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, POWERED_OFF },
-	{ HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, POWERED_OFF },
-	{ HT_LIST_TERMINAL }
-};
-
-// uncomment the line below to make Perf-per-watt enabled by default.
-#define BLDCFG_LINK_SKIP_REGANG_LIST &PerfPerWatt
-
-
-CONST IO_PCB_LIMITS ROMDATA MaranelloIoLimitList[2] =
-{
-	{
-		/* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-
-		/* Set upstream and downstream links to 16 bit widths, and limit frequencies to 3.2GHz */
-		HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, //Actually IO hub only support 2600M MAX
-	},
-
-	/* The 2nd element in the array merely terminates the list */
-	{
-		HT_LIST_TERMINAL,
-	}
-};
-
-#define BLDCFG_HTCHAIN_LIMITS_LIST &MaranelloIoLimitList
-
-CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] =
-{
-	// Source Socket, Link (4-7 are sublink 1), Target Socket
-	{0, 0, 1},
-	{0, 1, 1},
-	{0, 3, 1},
-	{0, 4, 1},
-	{0, 5, 1},
-	{0, 7, 1},
-};
-
-#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP &DinarPhysicalSocketMap
-
-/*
- *  PCI Bus numbers for Drachma/Peso board
- */
-CONST OVERRIDE_BUS_NUMBERS ROMDATA MaranelloOverrideBusNumbers[5] =
-{
-	// Socket, Link, SecBus, SubBus
-	{ 0, 2, 0x00, 0xBF },		// RD890 of Dinar
-	{ 1, 0, 0xC0, 0xFF },		// HTX
-	{ (HT_LIST_TERMINAL) }
-};
-
-#define BLDCFG_BUS_NUMBERS_LIST &MaranelloOverrideBusNumbers
-
-CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA DinarDeemphasisList[] =
-{
-	{ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_200M, HT_FREQUENCY_1800M, DeemphasisLevelNone, DcvLevelNone},
-	{ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2600M, DeemphasisLevelMinus3, DcvLevelMinus3},
-	{ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2800M, HT_FREQUENCY_MAX, DeemphasisLevelMinus6, DcvLevelMinus6},
-	{ (0xFF) }
-};
-
-#define BLDCFG_PLATFORM_DEEMPHASIS_LIST DinarDeemphasisList
-/*
-   CONST SKIP_REGANG ROMDATA DinarSkipRegangMap[] =
-   {
-// {socketA, linkA, socketB, linkB}
-{0, 0, 1, 1},
-};
-
-#define BLDCFG_LINK_SKIP_REGANG_LIST &DinarSkipRegangMap
-*/
-
-/*
- *  Device Capabilities Override for disabling ID Clumping
- */
-CONST DEVICE_CAP_OVERRIDE ROMDATA MaranelloOverrideDevCap[2] =
-{
-	{ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-	0, 0, HT_LIST_MATCH_ANY, {0, 0, 0, 0, 0, 1, 0}, 0, 0, 0, 0, 0 },
-	{ (HT_LIST_TERMINAL) }
-};
-
-#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap
-
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterfaceStub.h"
-#include <PlatformInstall.h>
diff --git a/src/mainboard/amd/dinar/cmos.layout b/src/mainboard/amd/dinar/cmos.layout
deleted file mode 100644
index 0e4ad462a0..0000000000
--- a/src/mainboard/amd/dinar/cmos.layout
+++ /dev/null
@@ -1,68 +0,0 @@
-#*****************************************************************************
-#
-#  This file is part of the coreboot project.
-#
-#  Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-#  This program is free software; you can redistribute it and/or modify
-#  it under the terms of the GNU General Public License as published by
-#  the Free Software Foundation; version 2 of the License.
-#
-#  This program is distributed in the hope that it will be useful,
-#  but WITHOUT ANY WARRANTY; without even the implied warranty of
-#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-#  GNU General Public License for more details.
-#*****************************************************************************
-
-entries
-
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#392          3       r       0        unused
-395          1       e       1        hw_scrubber
-396          1       e       1        interleave_chip_selects
-397          2       e       8        max_mem_clock
-399          1       e       2        multi_core
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        iommu
-456          1       e       1        ECC_memory
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
-
-
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-8     0     400Mhz
-8     1     333Mhz
-8     2     266Mhz
-8     3     200Mhz
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/amd/dinar/devicetree.cb b/src/mainboard/amd/dinar/devicetree.cb
deleted file mode 100644
index 114ec73534..0000000000
--- a/src/mainboard/amd/dinar/devicetree.cb
+++ /dev/null
@@ -1,104 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-chip northbridge/amd/agesa/family15/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family15
-		device lapic 0x20 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x1022 0x1705 inherit
-		chip northbridge/amd/agesa/family15 # CPU side of HT root complex
-			device pci 18.0 on     # Put IO-HUB at link_num 0, Instead of HT Link topology to satisfy both f10 and f15 CPUs
-				chip northbridge/amd/cimx/rd890 # North Bridge PCI side of HT Root complex
-					device pci 0.0 on  end # HT Root Complex
-					device pci 0.1 off end # CLKCONFIG
-					device pci 2.0 on  end # GPP1 Port0
-					device pci 3.0 off end # GPP1 Port1
-					device pci 4.0 off end # GPP3a Port0
-					device pci 5.0 off end # GPP3a Port1
-					device pci 6.0 off end # GPP3a Port2
-					device pci 7.0 off end # GPP3a Port3
-					device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time
-					device pci 9.0 off end # GPP3a Port4
-					device pci a.0 off end # GPP3a Port5
-					device pci b.0 off end # GPP2 Port0 (Not for sr5650)
-					device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670)
-					device pci d.0 on  end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
-					register "gpp1_configuration" = "0"   # Configuration 16:0 default
-					register "gpp2_configuration" = "1"   # Configuration 8:8
-					register "gpp3a_configuration" = "2"   # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1
-					register "port_enable" = "0x2104"
-				end # northbridge/amd/cimx/rd890
-				chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pri bus
-					device pci 11.0 on end # SATA
-					device pci 12.0 on end # USB1
-					device pci 12.1 on end # USB1
-					device pci 12.2 on end # USB1
-					device pci 13.0 on end # USB2
-					device pci 13.1 on end # USB2
-					device pci 13.2 on end # USB2
-					device pci 14.0 on # SM
-					end # SM
-					device pci 14.1 off end # IDE  0x439c
-					device pci 14.2 off end # HDA  0x4383
-					device pci 14.3 on # LPC
-						chip superio/smsc/sch4037  # SIO SMSC SCH4037
-							device pnp 2e.0 on # Floppy
-							io 0x60 = 0x3f0
-							irq 0x70 = 6
-							irq 0x74 = 2
-						end
-						device pnp 2e.3 on	# Parallel port
-							io 0x60 = 0x378
-							irq 0x70 = 7
-							irq 0x74 = 4
-						end
-						device pnp 2e.4 on	# COM1
-							io 0x60 = 0x3f8
-							irq 0x70 = 4
-						end
-						device pnp 2e.5 on	# COM2 / IR
-							io 0x60 = 0x2f8
-							irq 0x70 = 3
-						end
-						device pnp 2e.7 on	# PS/2 keyboard / mouse
-							io 0x60 = 0x60
-							io 0x62 = 0x64
-							irq 0x70 = 1	# PS/2 keyboard interrupt
-							irq 0x72 = 12	# PS/2 mouse interrupt
-						end
-					end #SIO SMSC SCH4037
-				end #LPC
-				device pci 14.4 on end # PCI bridge, 0x4384
-					device pci 14.5 on end # USB 3
-					register "boot_switch_sata_ide" = "0"   # 0: boot from SATA. 1: IDE
-				end #southbridge/amd/cimx/sb700
-			end # device pci 18.0
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 0 - Channel 0-3
-				{ {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 1 - Channel 0-3
-			}"
-		end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
-	end #domain
-end #northbridge/amd/agesa/family15/root_complex
diff --git a/src/mainboard/amd/dinar/dsdt.asl b/src/mainboard/amd/dinar/dsdt.asl
deleted file mode 100644
index 08bbe806e4..0000000000
--- a/src/mainboard/amd/dinar/dsdt.asl
+++ /dev/null
@@ -1,1148 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* DefinitionBlock Statement */
-DefinitionBlock (
-	"DSDT.AML",           /* Output filename */
-	"DSDT",                 /* Signature */
-	0x02,           /* DSDT Revision, needs to be 2 for 64bit */
-	"AMD   ",               /* OEMID */
-	"COREBOOT",          /* TABLE ID */
-	0x00010001      /* OEM Revision */
-	)
-{       /* Start of ASL file */
-	/* #include "../../../arch/x86/acpi/debug.asl" */       /* Include global debug methods if needed */
-
-	/* Data to be patched by the BIOS during POST */
-	/* FIXME the patching is not done yet! */
-	/* Memory related values */
-	Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
-	Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
-	Name(PBLN, 0x0) /* Length of BIOS area */
-
-	Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)  /* Base address of PCIe config space */
-	Name(HPBA, 0xFED00000)  /* Base address of HPET table */
-
-	/* Some global data */
-	Name(OSV, Ones) /* Assume nothing */
-	Name(GPIC, 0x1) /* Assume PIC */
-
-	/*
-	 * Processor Object
-	 *
-	 */
-	Scope (\_PR) {          /* define processor scope */
-		Processor(
-		C000,           /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */
-		0,              /* Unique number for this processor */
-		0x810,          /* PBLK system I/O address !hardcoded! */
-		0x06            /* PBLKLEN for boot processor */
-		) {
-		}
-		Processor(
-		C001,           /* name space name */
-		1,              /* Unique number for this processor */
-		0x810,          /* PBLK system I/O address !hardcoded! */
-		0x06            /* PBLKLEN for boot processor */
-		) {
-		}
-		Processor(
-		C002,           /* name space name */
-		2,              /* Unique number for this processor */
-		0x810,          /* PBLK system I/O address !hardcoded! */
-		0x06            /* PBLKLEN for boot processor */
-		) {
-		}
-		Processor(
-		C003,           /* name space name */
-		3,              /* Unique number for this processor */
-		0x810,          /* PBLK system I/O address !hardcoded! */
-		0x06            /* PBLKLEN for boot processor */
-		) {
-		}
-		Processor(
-		C004,		/* name space name */
-		4,		/* Unique number for this processor */
-		0x810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-		}
-		Processor(
-		C005,		/* name space name */
-		5,		/* Unique number for this processor */
-		0x810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-		}
-		Processor(
-		C006,		/* name space name */
-		6,		/* Unique number for this processor */
-		0x810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-		}
-		Processor(
-		C007,		/* name space name */
-		7,		/* Unique number for this processor */
-		0x810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-		}
-	} /* End _PR scope */
-
-	/* PIC IRQ mapping registers, C00h-C01h. */
-	OperationRegion(PIRQ, SystemIO, 0x00000C00, 0x00000002)
-	Field(PIRQ, ByteAcc, NoLock, Preserve) {
-		PIDX, 0x00000008,
-		PDAT, 0x00000008,  /* Offset: 1h */
-	}
-	IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) {
-		PIRA, 0x00000008,       /* Index 0 */
-		PIRB, 0x00000008,       /* Index 1 */
-		PIRC, 0x00000008,       /* Index 2 */
-		PIRD, 0x00000008,       /* Index 3 */
-		PIRE, 0x00000008,       /* Index 4 */
-		PIRF, 0x00000008,       /* Index 5 */
-		PIRG, 0x00000008,       /* Index 6 */
-		PIRH, 0x00000008,       /* Index 7 */
-		Offset(0x10),
-		PIRS, 0x00000008,
-		Offset(0x13),
-		HDAD, 0x00000008,
-		, 0x00000008,
-		GEC,  0x00000008,
-		Offset(0x30),
-		USB1, 0x00000008,
-		USB2, 0x00000008,
-		USB3, 0x00000008,
-		USB4, 0x00000008,
-		USB5, 0x00000008,
-		USB6, 0x00000008,
-		USB7, 0x00000008,
-		Offset(0x40),
-		IDE,  0x00000008,
-		SATA, 0x00000008,
-		Offset(0x50),
-		GPP0, 0x00000008,
-		GPP1, 0x00000008,
-		GPP2, 0x00000008,
-		GPP3, 0x00000008
-	}
-
-	/* PCI Error control register */
-	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
-	Field(PERC, ByteAcc, NoLock, Preserve) {
-		SENS, 0x00000001,
-		PENS, 0x00000001,
-		SENE, 0x00000001,
-		PENE, 0x00000001,
-	}
-
-	/* Client Management index/data registers */
-	OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
-	Field(CMT, ByteAcc, NoLock, Preserve) {
-		CMTI,      8,
-		/* Client Management Data register */
-		G64E,   1,
-		G64O,      1,
-		G32O,      2,
-		,       2,
-		GPSL,     2,
-	}
-
-	/* GPM Port register */
-	OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
-	Field(GPT, ByteAcc, NoLock, Preserve) {
-		GPB0,1,
-		GPB1,1,
-		GPB2,1,
-		GPB3,1,
-		GPB4,1,
-		GPB5,1,
-		GPB6,1,
-		GPB7,1,
-	}
-
-	/* Flash ROM program enable register */
-	OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
-	Field(FRE, ByteAcc, NoLock, Preserve) {
-		,     0x00000006,
-		FLRE, 0x00000001,
-	}
-
-	/* PM2 index/data registers */
-	OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
-	Field(PM2R, ByteAcc, NoLock, Preserve) {
-		PM2I, 0x00000008,
-		PM2D, 0x00000008,
-	}
-
-	/* Power Management I/O registers, TODO:PMIO is quite different in SB700. */
-	OperationRegion(PMRG, SystemIO, 0x00000CD6, 0x00000002)
-	Field(PMRG, ByteAcc, NoLock, Preserve) {
-		PMRI, 0x00000008,
-		PMRD, 0x00000008,
-	}
-	IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) {
-		Offset(0x24),
-		MMSO,32,
-		Offset(0x37),   /* GPMLevelConfig0 */
-		, 3,
-		PLC0, 1,
-		PLC1, 1,
-		PLC2, 1,
-		PLC3, 1,
-		PLC8, 1,
-		Offset(0x38),   /* GPMLevelConfig1 */
-		, 1,
-		PLC4, 1,
-		PLC5, 1,
-		, 1,
-		PLC6, 1,
-		PLC7, 1,
-		Offset(0x50),
-		HPAD,32,
-		Offset(0x60),
-		P1EB,16,
-		Offset(0x65),   /* UsbPMControl */
-		, 4,
-		URRE, 1,
-		Offset(0x96),   /* GPM98IN */
-		G8IS, 1,
-		G9IS, 1,
-		Offset(0x9A),   /* EnhanceControl */
-		,7,
-		HPDE, 1,
-		Offset(0xC8),
-		,2,
-		SPRE,1,
-		TPDE,1,
-		Offset(0xF0),
-		,3,
-		RSTU,1
-	}
-
-	/* PM1 Event Block
-	* First word is PM1_Status, Second word is PM1_Enable
-	*/
-	OperationRegion(P1E0, SystemIO, P1EB, 0x04)
-	Field(P1E0, ByteAcc, NoLock, Preserve) {
-		,14,
-		PEWS,1,
-		WSTA,1,
-		,14,
-		PEWD,1
-	}
-
-	OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
-	Field (GRAM, ByteAcc, Lock, Preserve)
-	{
-		Offset (0x10),
-		FLG0,   8
-	}
-
-	Scope(\_SB) {
-		/* PCIe Configuration Space for 16 busses */
-		OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
-		Field(PCFG, ByteAcc, NoLock, Preserve) {
-		/* Byte offsets are computed using the following technique:
-		 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
-		 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
-		*/
-		Offset(0x00088024),     /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
-		STB5, 32,
-		Offset(0x00098042),     /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
-		PT0D, 1,
-		PT1D, 1,
-		PT2D, 1,
-		PT3D, 1,
-		PT4D, 1,
-		PT5D, 1,
-		PT6D, 1,
-		PT7D, 1,
-		PT8D, 1,
-		PT9D, 1,
-		Offset(0x000A0004),     /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
-		SBIE, 1,
-		SBME, 1,
-		Offset(0x000A0008),     /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
-		SBRI, 8,
-		Offset(0x000A0014),     /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
-		SBB1, 32,
-		Offset(0x000A0078),     /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
-		,14,
-		P92E, 1,                /* Port92 decode enable */
-	}
-
-	OperationRegion(SB5, SystemMemory, STB5, 0x1000)
-	Field(SB5, AnyAcc, NoLock, Preserve){
-		/* Port 0 */
-		Offset(0x120),          /* Port 0 Task file status */
-		P0ER, 1,
-		, 2,
-		P0DQ, 1,
-		, 3,
-		P0BY, 1,
-		Offset(0x128),          /* Port 0 Serial ATA status */
-		P0DD, 4,
-		, 4,
-		P0IS, 4,
-		Offset(0x12C),          /* Port 0 Serial ATA control */
-		P0DI, 4,
-		Offset(0x130),          /* Port 0 Serial ATA error */
-		, 16,
-		P0PR, 1,
-
-		/* Port 1 */
-		offset(0x1A0),          /* Port 1 Task file status */
-		P1ER, 1,
-		, 2,
-		P1DQ, 1,
-		, 3,
-		P1BY, 1,
-		Offset(0x1A8),          /* Port 1 Serial ATA status */
-		P1DD, 4,
-		, 4,
-		P1IS, 4,
-		Offset(0x1AC),          /* Port 1 Serial ATA control */
-		P1DI, 4,
-		Offset(0x1B0),          /* Port 1 Serial ATA error */
-		, 16,
-		P1PR, 1,
-
-		/* Port 2 */
-		Offset(0x220),          /* Port 2 Task file status */
-		P2ER, 1,
-		, 2,
-		P2DQ, 1,
-		, 3,
-		P2BY, 1,
-		Offset(0x228),          /* Port 2 Serial ATA status */
-		P2DD, 4,
-		, 4,
-		P2IS, 4,
-		Offset(0x22C),          /* Port 2 Serial ATA control */
-		P2DI, 4,
-		Offset(0x230),          /* Port 2 Serial ATA error */
-		, 16,
-		P2PR, 1,
-
-		/* Port 3 */
-		Offset(0x2A0),          /* Port 3 Task file status */
-		P3ER, 1,
-		, 2,
-		P3DQ, 1,
-		, 3,
-		P3BY, 1,
-		Offset(0x2A8),          /* Port 3 Serial ATA status */
-		P3DD, 4,
-		, 4,
-		P3IS, 4,
-		Offset(0x2AC),          /* Port 3 Serial ATA control */
-		P3DI, 4,
-		Offset(0x2B0),          /* Port 3 Serial ATA error */
-		, 16,
-		P3PR, 1,
-	}
-}
-
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-
-		/* Debug Port registers, 80h. */
-		OperationRegion(DBBG, SystemIO, 0x00000080, 0x00000001)
-		Field(DBBG, ByteAcc, NoLock, Preserve) {
-			DBG8, 0x00000008,
-		}
-
-		Method(_PIC, 1) {
-			Store(Arg0, GPIC)
-			If (GPIC) {
-				Store(0xAA, \_SB.DBG8)
-				\_SB.DSPI()
-			} else {
-				Store(0xAC, \_SB.DBG8)
-			}
-		}
-
-		Method(DSPI, 0) {
-			\_SB.GRUA(0x1F)
-			\_SB.GRUB(0x1F)
-			\_SB.GRUC(0x1F)
-			\_SB.GRUD(0x1F)
-			Store(0x1F, PIRE)
-			Store(0x1F, PIRF)
-			Store(0x1F, PIRG)
-			Store(0x1F, PIRH)
-		}
-
-		Method(GRUA, 1) {
-			Store(Arg0, PIRA)
-			Store(Arg0, HDAD)
-			Store(Arg0, GEC)
-			Store(Arg0, GPP0)
-			Store(Arg0, GPP0)
-		}
-
-		Method(GRUB, 1) {
-			Store(Arg0, PIRB)
-			Store(Arg0, USB2)
-			Store(Arg0, USB4)
-			Store(Arg0, USB6)
-			Store(Arg0, GPP1)
-			Store(Arg0, IDE)
-		}
-
-		Method(GRUC, 1) {
-			Store(Arg0, PIRC)
-			Store(Arg0, USB1)
-			Store(Arg0, USB3)
-			Store(Arg0, USB5)
-			Store(Arg0, USB7)
-			Store(Arg0, GPP2)
-		}
-
-		Method(GRUD, 1) {
-			Store(Arg0, PIRD)
-			Store(Arg0, SATA)
-			Store(Arg0, GPP3)
-		}
-
-		Name(IRQB, ResourceTemplate() {
-			IRQ(Level, ActiveLow, Shared) {
-				15
-		}})
-
-		Name(IRQP, ResourceTemplate() {
-			IRQ(Level, ActiveLow, Shared) {
-				3, 4, 5, 7, 10, 11, 12, 14, 15
-			}
-		})
-
-		Device(INTA) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 1)
-			Method(_STA, 0) {
-				if (PIRA) {
-					Return(0x0B)
-				} else {
-					Return(0x09)
-				}
-			}
-			Method(_DIS ,0) {
-				\_SB.GRUA(0x1F)
-			}
-			Method(_PRS ,0) {
-				Return(IRQP)
-			}
-			Method(_CRS ,0) {
-				CreateWordField(IRQB, 1, IRQN)
-				ShiftLeft(1, PIRA, IRQN)
-				Return(IRQB)
-			}
-			Method(_SRS, 1) {
-				CreateWordField(Arg0, 1, IRQM)
-				FindSetRightBit(IRQM, Local0)
-				Decrement(Local0)
-				\_SB.GRUA(Local0)
-			}
-		}
-
-		Device(INTB) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 2)
-			Method(_STA, 0) {
-				if (PIRB) {
-					Return(0x0B)
-				} else {
-					Return(0x09)
-				}
-			}
-			Method(_DIS ,0) {
-				\_SB.GRUB(0x1F)
-			}
-			Method(_PRS ,0) {
-				Return(IRQP)
-			}
-			Method(_CRS ,0) {
-				CreateWordField(IRQB, 1, IRQN)
-				ShiftLeft(1, PIRB, IRQN)
-				Return(IRQB)
-			}
-			Method(_SRS, 1) {
-				CreateWordField(Arg0, 1, IRQM)
-				FindSetRightBit(IRQM, Local0)
-				Decrement(Local0)
-				\_SB.GRUB(Local0)
-			}
-		}
-
-		Device(INTC) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 3)
-			Method(_STA, 0) {
-				if (PIRC) {
-					Return(0x0B)
-				} else {
-					Return(0x09)
-				}
-			}
-			Method(_DIS ,0) {
-				\_SB.GRUC(0x1F)
-			}
-			Method(_PRS ,0) {
-				Return(IRQP)
-			}
-			Method(_CRS ,0) {
-				CreateWordField(IRQB, 1, IRQN)
-				ShiftLeft(1, PIRC, IRQN)
-				Return(IRQB)
-			}
-			Method(_SRS, 1) {
-				CreateWordField(Arg0, 1, IRQM)
-				FindSetRightBit(IRQM, Local0)
-				Decrement(Local0)
-				\_SB.GRUC(Local0)
-			}
-		}
-
-		Device(INTD) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 4)
-			Method(_STA, 0) {
-				if (PIRD) {
-					Return(0x0B)
-				} else {
-					Return(0x09)
-				}
-			}
-			Method(_DIS ,0) {
-				\_SB.GRUD(0x1F)
-			}
-			Method(_PRS ,0) {
-				Return(IRQP)
-			}
-			Method(_CRS ,0) {
-				CreateWordField(IRQB, 1, IRQN)
-				ShiftLeft(1, PIRD, IRQN)
-				Return(IRQB)
-			}
-			Method(_SRS, 1) {
-				CreateWordField(Arg0, 1, IRQM)
-				FindSetRightBit(IRQM, Local0)
-				Decrement(Local0)
-				\_SB.GRUD(Local0)
-			}
-		}
-
-		Device(INTE) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 5)
-			Method(_STA, 0) {
-				if (PIRE) {
-					Return(0x0B)
-				} else {
-					Return(0x09)
-				}
-			}
-			Method(_DIS ,0) {
-				Store(0x1F, PIRE)
-			}
-			Method(_PRS ,0) {
-				Return(IRQP)
-			}
-			Method(_CRS ,0) {
-				CreateWordField(IRQB, 1, IRQN)
-				ShiftLeft(1, PIRE, IRQN)
-				Return(IRQB)
-			}
-			Method(_SRS, 1) {
-				CreateWordField(Arg0, 1, IRQM)
-				FindSetRightBit(IRQM, Local0)
-				Decrement(Local0)
-				Store(Local0, PIRE)
-			}
-		}
-
-		Device(INTF) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 6)
-			Method(_STA, 0) {
-				if (PIRF) {
-					Return(0x0B)
-				} else {
-					Return(0x09)
-				}
-			}
-			Method(_DIS ,0) {
-				Store(0x1F, PIRF)
-			}
-			Method(_PRS ,0) {
-				Return(IRQP)
-			}
-			Method(_CRS ,0) {
-				CreateWordField(IRQB, 1, IRQN)
-				ShiftLeft(1, PIRF, IRQN)
-				Return(IRQB)
-			}
-			Method(_SRS, 1) {
-				CreateWordField(Arg0, 1, IRQM)
-				FindSetRightBit(IRQM, Local0)
-				Decrement(Local0)
-				Store(Local0, PIRF)
-			}
-		}
-
-		Device(INTG) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 7)
-			Method(_STA, 0) {
-				if (PIRG) {
-					Return(0x0B)
-				} else {
-					Return(0x09)
-				}
-			}
-			Method(_DIS ,0) {
-				Store(0x1F, PIRG)
-			}
-			Method(_PRS ,0) {
-				Return(IRQP)
-			}
-			Method(_CRS ,0) {
-				CreateWordField(IRQB, 1, IRQN)
-				ShiftLeft(1, PIRG, IRQN)
-				Return(IRQB)
-			}
-			Method(_SRS, 1) {
-				CreateWordField(Arg0, 1, IRQM)
-				FindSetRightBit(IRQM, Local0)
-				Decrement(Local0)
-				Store(Local0, PIRG)
-			}
-		}
-
-		Device(INTH) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 8)
-			Method(_STA, 0) {
-				if (PIRH) {
-					Return(0x0B)
-				} else {
-					Return(0x09)
-				}
-			}
-			Method(_DIS ,0) {
-				Store(0x1F, PIRH)
-			}
-			Method(_PRS ,0) {
-				Return(IRQP)
-			}
-			Method(_CRS ,0) {
-				CreateWordField(IRQB, 1, IRQN)
-				ShiftLeft(1, PIRH, IRQN)
-				Return(IRQB)
-			}
-			Method(_SRS, 1) {
-				CreateWordField(Arg0, 1, IRQM)
-				FindSetRightBit(IRQM, Local0)
-				Decrement(Local0)
-				Store(Local0, PIRH)
-			}
-		}
-	}   /* End Scope(_SB)  */
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Wake status package */
-	Name(WKST,Package(){Zero, Zero})
-
-	/*
-	* \_PTS - Prepare to Sleep method
-	*
-	*       Entry:
-	*               Arg0=The value of the sleeping state S1=1, S2=2, etc
-	*
-	* Exit:
-	*               -none-
-	*
-	* The _PTS control method is executed at the beginning of the sleep process
-	* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-	* control method may be executed a relatively long time before entering the
-	* sleep state and the OS may abort the operation without notification to
-	* the ACPI driver.  This method cannot modify the configuration or power
-	* state of any device in the system.
-	*/
-	Method(\_PTS, 1) {
-		/* DBGO("\\_PTS\n") */
-		/* DBGO("From S0 to S") */
-		/* DBGO(Arg0) */
-		/* DBGO("\n") */
-
-		/* Don't allow PCIRST# to reset USB */
-		if (LEqual(Arg0,3)){
-			Store(0,URRE)
-		}
-
-		/* Clear sleep SMI status flag and enable sleep SMI trap. */
-		/*Store(One, CSSM)
-		Store(One, SSEN)*/
-
-		/* On older chips, clear PciExpWakeDisEn */
-		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
-		*       Store(0,\_SB.PWDE)
-		*}
-		*/
-
-		/* Clear wake status structure. */
-		Store(0, Index(WKST,0))
-		Store(0, Index(WKST,1))
-	} /* End Method(\_PTS) */
-
-	/*
-	*  The following method results in a "not a valid reserved NameSeg"
-	*  warning so I have commented it out for the duration.  It isn't
-	*  used, so it could be removed.
-	*
-	*
-	*       \_GTS OEM Going To Sleep method
-	*
-	*       Entry:
-	*               Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*       Exit:
-	*               -none-
-	*
-	*  Method(\_GTS, 1) {
-	*  DBGO("\\_GTS\n")
-	*  DBGO("From S0 to S")
-	*  DBGO(Arg0)
-	*  DBGO("\n")
-	*  }
-	*/
-
-	/*
-	*       \_BFS OEM Back From Sleep method
-	*
-	*       Entry:
-	*               Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*       Exit:
-	*               -none-
-	*/
-	Method(\_BFS, 1) {
-		/* DBGO("\\_BFS\n") */
-		/* DBGO("From S") */
-		/* DBGO(Arg0) */
-		/* DBGO(" to S0\n") */
-	}
-
-	/*
-	*  \_WAK System Wake method
-	*
-	*       Entry:
-	*               Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*       Exit:
-	*               Return package of 2 DWords
-	*               Dword 1 - Status
-	*                       0x00000000      wake succeeded
-	*                       0x00000001      Wake was signaled but failed due to lack of power
-	*                       0x00000002      Wake was signaled but failed due to thermal condition
-	*               Dword 2 - Power Supply state
-	*                       if non-zero the effective S-state the power supply entered
-	*/
-	Method(\_WAK, 1) {
-		/* DBGO("\\_WAK\n") */
-		/* DBGO("From S") */
-		/* DBGO(Arg0) */
-		/* DBGO(" to S0\n") */
-
-		/* Re-enable HPET */
-		Store(1,HPDE)
-
-		/* Restore PCIRST# so it resets USB */
-		if (LEqual(Arg0,3)){
-			Store(1,URRE)
-		}
-
-		/* Arbitrarily clear PciExpWakeStatus */
-		Store(PEWS, Local0)
-		Store(Local0, PEWS)
-
-		/* if(DeRefOf(Index(WKST,0))) {
-		*       Store(0, Index(WKST,1))
-		* } else {
-		*       Store(Arg0, Index(WKST,1))
-		* }
-		*/
-		Return(WKST)
-	} /* End Method(\_WAK) */
-
-	Scope(\_GPE) {  /* Start Scope GPE */
-	}       /* End Scope GPE */
-
-	/* System Bus */
-	Scope(\_SB) { /* Start \_SB scope */
-		#include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
-
-		/*  _SB.PCI0 */
-		/* Note: Only need HID on Primary Bus */
-		Device(PCI0) {
-			External (TOM1)
-			External (TOM2)
-			External (TOM3)
-			External (TOM4)
-			Name(_HID, EISAID("PNP0A03"))
-			Name(_ADR, 0x00180000)  /* Dev# = BSP Dev#, Func# = 0 */
-			Method(_BBN, 0) { /* Bus number = 0 */
-				Return(0)
-			}
-			Method(_STA, 0) {
-				/* DBGO("\\_SB\\PCI0\\_STA\n") */
-				Return(0x0B)     /* Status is visible */
-			}
-			Method(_PRT,0) {
-				If(GPIC){ Return(APR0) }   /* APIC mode */
-				Return (PR0)                  /* PIC Mode */
-			} /* end _PRT */
-
-			/* Describe the Northbridge devices */
-			Device(AMRT) {
-				Name(_ADR, 0x00000000)
-			} /* end AMRT */
-
-			/* The internal GFX bridge */
-			Device(AGPB) {
-				Name(_ADR, 0x00010000)
-				Method(_STA,0) {
-					Return(0x0F)
-				}
-			}  /* end AGPB */
-
-			/* The external GFX bridge */
-			Device(PBR2) {
-				Name(_ADR, 0x00020000)
-				Method(_PRT,0) {
-					If(GPIC){ Return(APS2) }   /* APIC mode */
-					Return (PS2)               /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR2 */
-
-			/* The external GFX bridge */
-			Device(PBR3) {
-				Name(_ADR, 0x00030000)
-				Method(_PRT,0) {
-					If(GPIC){ Return(APS3) }   /* APIC mode */
-					Return (PS3)               /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR3 */
-
-			Device(PBR4) {
-				Name(_ADR, 0x00040000)
-				Method(_PRT,0) {
-					If(GPIC){ Return(APS4) }   /* APIC mode */
-					Return (PS4)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR4 */
-
-			Device(PBR5) {
-				Name(_ADR, 0x00050000)
-				Method(_PRT,0) {
-					If(GPIC){ Return(APS5) }   /* APIC mode */
-					Return (PS5)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR5 */
-
-			Device(PBR6) {
-				Name(_ADR, 0x00060000)
-				Method(_PRT,0) {
-					If(GPIC){ Return(APS6) }   /* APIC mode */
-					Return (PS6)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR6 */
-
-			/* The onboard EtherNet chip */
-			Device(PBR7) {
-				Name(_ADR, 0x00070000)
-				Method(_PRT,0) {
-					If(GPIC){ Return(APS7) }   /* APIC mode */
-					Return (PS7)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR7 */
-				Device(PE20) {
-				Name(_ADR, 0x00150000)
-				Method(_PRT,0) {
-					If(GPIC){ Return(APE0) }   /* APIC mode */
-					Return (PE0)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PE20 */
-			Device(PE21) {
-				Name(_ADR, 0x00150001)
-				Method(_PRT,0) {
-					If(GPIC){ Return(APE1) }   /* APIC mode */
-					Return (PE1)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PE21 */
-			Device(PE22) {
-				Name(_ADR, 0x00150002)
-				Method(_PRT,0) {
-					If(GPIC){ Return(APE2) }   /* APIC mode */
-					Return (APE2)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PE22 */
-			Device(PE23) {
-				Name(_ADR, 0x00150003)
-				Method(_PRT,0) {
-					If(GPIC){ Return(APE3) }   /* APIC mode */
-					Return (PE3)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PE23 */
-
-			/* Describe the Southbridge devices */
-			Device(AZHD) {
-				Name(_ADR, 0x00140002)
-				OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
-				Field(AZPD, AnyAcc, NoLock, Preserve) {
-				offset (0x42),
-				NSDI, 1,
-				NSDO, 1,
-				NSEN, 1,
-			}
-			} /* end AZHD */
-
-			Device(GEC) {
-				Name(_ADR, 0x00140006)
-			} /* end GEC */
-
-			Device(UOH1) {
-				Name(_ADR, 0x00120000)
-			} /* end UOH1 */
-
-			Device(UOH3) {
-				Name(_ADR, 0x00130000)
-			} /* end UOH3 */
-
-			Device(UOH5) {
-				Name(_ADR, 0x00160000)
-			} /* end UOH5 */
-
-			Device(UEH1) {
-				Name(_ADR, 0x00140005)
-			} /* end UEH1 */
-
-			Device(UOH2) {
-				Name(_ADR, 0x00120002)
-			} /* end UOH2 */
-
-			Device(UOH4) {
-				Name(_ADR, 0x00130002)
-			} /* end UOH4 */
-
-			Device(UOH6) {
-				Name(_ADR, 0x00160002)
-			} /* end UOH5 */
-
-			Device(XHC0) {
-				Name(_ADR, 0x00100000)
-			} /* end XHC0 */
-
-			Device(XHC1) {
-				Name(_ADR, 0x00100001)
-			} /* end XHC1 */
-
-			Device(SBUS) {
-				Name(_ADR, 0x00140000)
-			} /* end SBUS */
-
-			Device(LIBR) {
-				Name(_ADR, 0x00140003)
-				/* Real Time Clock Device */
-				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
-					Name(BUF0, ResourceTemplate() {
-					IO(Decode16, 0x0070, 0x0070, 0x01, 0x02)
-				})
-				Name(BUF1, ResourceTemplate() {
-					IRQNoFlags() {8}
-					IO(Decode16, 0x0070, 0x0070, 0x01, 0x02)
-				})
-				Method(_CRS, 0) {
-					If(LAnd(HPAD, 0xFFFFFF00)) {
-						Return(BUF0)
-					}
-					Return(BUF1)
-				}
-			} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
-			Device(TMR) {   /* Timer */
-				Name(_HID,EISAID("PNP0100"))    /* System Timer */
-				Name(BUF0, ResourceTemplate() {
-					IO(Decode16, 0x0040, 0x0040, 0x01, 0x04)
-				})
-				Name(BUF1, ResourceTemplate() {
-					IRQNoFlags() {0}
-					IO(Decode16, 0x0040, 0x0040, 0x01, 0x04)
-				})
-				Method(_CRS, 0) {
-					If(LAnd(HPAD, 0xFFFFFF00)) {
-						Return(BUF0)
-					}
-					Return(BUF1)
-				}
-			} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
-			Device(SPKR) {  /* Speaker */
-				Name(_HID,EISAID("PNP0800"))    /* AT style speaker */
-				Name(_CRS, ResourceTemplate() {
-					IO(Decode16, 0x0061, 0x0061, 0, 1)
-				})
-			} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
-			Device(PIC) {
-				Name(_HID,EISAID("PNP0000"))    /* AT Interrupt Controller */
-				Name(_CRS, ResourceTemplate() {
-					IRQNoFlags(){2}
-					IO(Decode16,0x0020, 0x0020, 0, 2)
-					IO(Decode16,0x00A0, 0x00A0, 0, 2)
-					/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
-					/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
-				})
-			} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
-			Device(MAD) { /* 8257 DMA */
-				Name(_HID,EISAID("PNP0200"))    /* Hardware Device ID */
-				Name(_CRS, ResourceTemplate() {
-					DMA(Compatibility,BusMaster,Transfer8){4}
-					IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
-					IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
-					IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
-					IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
-					IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
-					IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
-				}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
-			} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
-			Device(COPR) {
-				Name(_HID,EISAID("PNP0C04"))    /* Math Coprocessor */
-				Name(_CRS, ResourceTemplate() {
-					IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
-					IRQNoFlags(){13}
-				})
-			} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
-			Device (PS2M) {
-				Name (_HID, EisaId ("PNP0F13"))
-				Name (_CRS, ResourceTemplate () {
-					IRQNoFlags () {12}
-				})
-				Method (_STA, 0)        {
-					And (FLG0, 0x04, Local0)
-					If (LEqual (Local0, 0x04)) {
-						Return (0x0F)
-					} Else {
-						Return (0x00)
-					}
-				}
-			}
-
-			Device (PS2K) {
-				Name (_HID, EisaId ("PNP0303"))
-				Name (_CRS, ResourceTemplate () {
-					IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
-					IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
-					IRQNoFlags () {1}
-				})
-			}
-		} /* end LIBR */
-
-		Device(STCR) {
-			Name(_ADR, 0x00110000)
-			#include "acpi/sata.asl"
-		} /* end STCR */
-
-		/* Primary (and only) IDE channel */
-		Device(IDEC) {
-			Name(_ADR, 0x00140001)
-			#include "acpi/ide.asl"
-		} /* end IDEC */
-
-		Device(HPET) {
-			Name(_HID,EISAID("PNP0103"))
-			Name(CRS, ResourceTemplate() {
-				IRQNoFlags() {0}
-				IRQNoFlags() {8}
-				Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400)
-			})
-			Method(_STA, 0) {
-				If(LAnd(HPAD, 0xFFFFFF00)) {
-					Return(0x0F)
-				}
-				Return(0x0)
-			}
-			Method(_CRS, 0) {
-				CreateDWordField(CRS, 0x0A, HPEB)
-				Store(HPAD, Local0)
-				And(Local0, 0xFFFFFFC0, HPEB)
-				Return(CRS)
-			}
-		} /* End Device(_SB.PCI0.HPET) */
-
-		Name(CRES, ResourceTemplate() {
-			IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
-
-			WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-				0x0000,                 /* address granularity */
-				0x0000,                 /* range minimum */
-				0x0CF7,                 /* range maximum */
-				0x0000,                 /* translation */
-				0x0CF8                  /* length */
-			)
-
-			WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-				0x0000,                 /* address granularity */
-				0x0D00,                 /* range minimum */
-				0xFFFF,                 /* range maximum */
-				0x0000,                 /* translation */
-				0xF300                  /* length */
-			)
-
-			/* memory space for PCI BARs below 4GB */
-			Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
-		}) /* End Name(_SB.PCI0.CRES) */
-
-		Method(_CRS, 0) {
-			/* DBGO("\\_SB\\PCI0\\_CRS\n") */
-			CreateDWordField(CRES, ^MMIO._BAS, MM1B)
-			CreateDWordField(CRES, ^MMIO._LEN, MM1L)
-
-			Store(\_SB.PCI0.TOM1, MM1B)
-			Subtract(PCBA, MM1B, MM1L)
-
-			Return(CRES) /* note to change the Name buffer */
-		} /* end of Method(_SB.PCI0._CRS) */
-			} /* End Device(PCI0)  */
-
-		Device(PWRB) {  /* Start Power button device */
-			Name(_HID, EISAID("PNP0C0C"))
-			Name(_UID, 0xAA)
-			Name(_STA, 0x0B) /* sata is invisible */
-		}
-	} /* End \_SB scope */
-}
-/* End of ASL file */
diff --git a/src/mainboard/amd/dinar/fadt.c b/src/mainboard/amd/dinar/fadt.c
deleted file mode 100644
index 1aad0b50ed..0000000000
--- a/src/mainboard/amd/dinar/fadt.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- */
-
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include "Platform.h" /*sb700 platform header*/
-
-#ifndef ACPI_BLK_BASE
-#define ACPI_BLK_BASE	PM1_EVT_BLK_ADDRESS
-#endif
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
-	acpi_header_t *header = &(fadt->header);
-
-	printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
-	/* Prepare the header */
-	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
-	memcpy(header->signature, "FACP", 4);
-	header->length = 244;
-	header->revision = 1;
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-	header->asl_compiler_revision = 0;
-
-	if ((uintptr_t)facs > 0xffffffff)
-		printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n");
-	else
-		fadt->firmware_ctrl = (uintptr_t)facs;
-
-	if ((uintptr_t)dsdt > 0xffffffff)
-		printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n");
-	else
-		fadt->dsdt = (uintptr_t)dsdt;
-
-	/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
-	fadt->preferred_pm_profile = 0x03;
-	fadt->sci_int = 9;
-	/* disable system management mode by setting to 0: */
-	fadt->smi_cmd = 0;
-	fadt->acpi_enable = 0xf0;
-	fadt->acpi_disable = 0xf1;
-	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = 0xe2;
-
-	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
-	outl(0x1, PM1_CNT_BLK_ADDRESS);           /* set SCI_EN */
-	fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
-	fadt->pm1b_evt_blk = 0x0000;
-	fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
-	fadt->pm1b_cnt_blk = 0x0000;
-	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
-	fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
-	fadt->gpe0_blk = GPE0_BLK_ADDRESS;
-	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
-
-	fadt->pm1_evt_len = 4;
-	fadt->pm1_cnt_len = 2;
-	fadt->pm2_cnt_len = 1;
-	fadt->pm_tmr_len = 4;
-	fadt->gpe0_blk_len = 8;
-	fadt->gpe1_blk_len = 0;
-	fadt->gpe1_base = 0;
-
-	fadt->cst_cnt = 0xe3;
-	fadt->p_lvl2_lat = 101;
-	fadt->p_lvl3_lat = 1001;
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
-	fadt->duty_offset = 1;
-	fadt->duty_width = 3;
-	fadt->day_alrm = 0;	/* 0x7d these have to be */
-	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
-	fadt->century = 0;	/* 0x7f to make rtc alrm work */
-	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
-	fadt->flags = 0x0001c1a5;/* 0x25; */
-
-	fadt->res2 = 0;
-
-	fadt->reset_reg.space_id = 1;
-	fadt->reset_reg.bit_width = 8;
-	fadt->reset_reg.bit_offset = 0;
-	fadt->reset_reg.resv = 0;
-	fadt->reset_reg.addrl = 0xcf9;
-	fadt->reset_reg.addrh = 0x0;
-
-	fadt->reset_value = 6;
-	fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff;
-	fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32;
-	fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff;
-	fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32;
-
-	fadt->x_pm1a_evt_blk.space_id = 1;
-	fadt->x_pm1a_evt_blk.bit_width = 32;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.resv = 0;
-	fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
-	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_evt_blk.space_id = 1;
-	fadt->x_pm1b_evt_blk.bit_width = 4;
-	fadt->x_pm1b_evt_blk.bit_offset = 0;
-	fadt->x_pm1b_evt_blk.resv = 0;
-	fadt->x_pm1b_evt_blk.addrl = 0x0;
-	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-
-	fadt->x_pm1a_cnt_blk.space_id = 1;
-	fadt->x_pm1a_cnt_blk.bit_width = 16;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.resv = 0;
-	fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
-	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_cnt_blk.space_id = 1;
-	fadt->x_pm1b_cnt_blk.bit_width = 2;
-	fadt->x_pm1b_cnt_blk.bit_offset = 0;
-	fadt->x_pm1b_cnt_blk.resv = 0;
-	fadt->x_pm1b_cnt_blk.addrl = 0x0;
-	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-
-	fadt->x_pm2_cnt_blk.space_id = 1;
-	fadt->x_pm2_cnt_blk.bit_width = 0;
-	fadt->x_pm2_cnt_blk.bit_offset = 0;
-	fadt->x_pm2_cnt_blk.resv = 0;
-	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
-	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-
-	fadt->x_pm_tmr_blk.space_id = 1;
-	fadt->x_pm_tmr_blk.bit_width = 32;
-	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.resv = 0;
-	fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
-	fadt->x_pm_tmr_blk.addrh = 0x0;
-
-
-	fadt->x_gpe0_blk.space_id = 1;
-	fadt->x_gpe0_blk.bit_width = 32;
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.resv = 0;
-	fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
-	fadt->x_gpe0_blk.addrh = 0x0;
-
-
-	fadt->x_gpe1_blk.space_id = 1;
-	fadt->x_gpe1_blk.bit_width = 0;
-	fadt->x_gpe1_blk.bit_offset = 0;
-	fadt->x_gpe1_blk.resv = 0;
-	fadt->x_gpe1_blk.addrl = 0;
-	fadt->x_gpe1_blk.addrh = 0x0;
-
-	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-
-}
diff --git a/src/mainboard/amd/dinar/gpio.c b/src/mainboard/amd/dinar/gpio.c
deleted file mode 100644
index d1d2b864f5..0000000000
--- a/src/mainboard/amd/dinar/gpio.c
+++ /dev/null
@@ -1,447 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "Hudson-2.h"
-#include "AmdSbLib.h"
-#include "gpio.h"
-
-
-#ifndef SB_GPIO_REG01
-#define SB_GPIO_REG01   1
-#endif
-
-#ifndef SB_GPIO_REG07
-#define SB_GPIO_REG07   7
-#endif
-
-#ifndef SB_GPIO_REG25
-#define SB_GPIO_REG25   25
-#endif
-
-#ifndef SB_GPIO_REG26
-#define SB_GPIO_REG26   26
-#endif
-
-#ifndef SB_GPIO_REG27
-#define SB_GPIO_REG27   27
-#endif
-
-void gpioEarlyInit (void);
-
-void
-gpioEarlyInit(
-		void
-	     )
-{
-	u8  Flags;
-	u8	Data8 = 0;
-	u8	StripInfo = 0;
-	u8	BoardType = 1;
-	u8	RegIndex8 = 0;
-	u8	boardRevC = 0x2;
-	u16	Data16 = 0;
-	u32	Index = 0;
-	u32	AcpiMmioAddr = 0;
-	u32	GpioMmioAddr = 0;
-	u32	IoMuxMmioAddr = 0;
-	u32	MiscMmioAddr = 0;
-	u32	SmiMmioAddr = 0;
-	u32	andMask32 = 0;
-
-	// Enable HUDSON MMIO Base (AcpiMmioAddr)
-	ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
-	Data8 |= BIT0;
-	WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
-	// Get HUDSON MMIO Base (AcpiMmioAddr)
-	ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8);
-	Data16 = Data8 << 8;
-	ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8);
-	Data16 |= Data8;
-	AcpiMmioAddr = (u32)Data16 << 16;
-	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
-	IoMuxMmioAddr = AcpiMmioAddr + IOMUX_BASE;
-	MiscMmioAddr =  AcpiMmioAddr + MISC_BASE;
-	Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80);
-	if ((Data8 & BIT4) == 0) {
-		BoardType = 0; // external clock board
-	}
-	Data8 = Mmio8_G (GpioMmioAddr, GPIO_30);
-	StripInfo = (Data8 & BIT7) >> 7;
-	Data8 = Mmio8_G (GpioMmioAddr, GPIO_31);
-	StripInfo |= (Data8 & BIT7) >> 6;
-	if (StripInfo < boardRevC) { 		// for old board. Rev B
-		Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3);		// function 3
-		Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0);		// function 0
-	}
-	for (Index = 0; Index < MAX_GPIO_NO; Index++) {
-		if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) {
-			if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) {
-				// Configure multi-function
-				Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio));
-			}
-			// Configure GPIO
-			if(!((gpio_table[Index].NonGpioGevent & NonGpio))) {
-				Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type);
-				Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value);
-			}
-			if (Index == GPIO_65) {
-				if ( BoardType == 0 ) {
-					Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3);		// function 3
-				}
-			}
-		}
-		// Configure GEVENT
-		if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) {
-			SmiMmioAddr = AcpiMmioAddr + SMI_BASE;
-
-			andMask32 = ~(1 << (Index - GEVENT_00));
-
-			//EventEnable: 0-Disable, 1-Enable
-			Mmio32_And_Or     (SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00)));
-
-			//SciTrig: 0-Falling Edge, 1-Rising Edge
-			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00)));
-
-			//SciLevl: 0-Edge trigger, 1-Level Trigger
-			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00)));
-
-			//SmiSciEn: 0-Not send SMI, 1-Send SMI
-			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00)));
-
-			//SciS0En: 0-Disable, 1-Enable
-			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00)));
-
-			//SciMap: 00000b ~ 11111b
-			RegIndex8=(u8)((Index - GEVENT_00) >> 2);
-			Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8);
-			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8));
-
-			//SmiTrig: 0-Active Low, 1-Active High
-			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)));
-
-			//SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13
-			RegIndex8=(u8)((Index - GEVENT_00) >> 4);
-			Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2);
-			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8));
-		}
-	}
-
-	//
-	// config MXM
-	//	GPIO9: Input for MXM_PRESENT2#
-	//	GPIO10: Input for MXM_PRESENT1#
-	//	GPIO28: Input for MXM_PWRGD
-	//	GPIO35: Output for MXM Reset
-	//	GPIO45: Output for MXM Power Enable, active HIGH
-	//	GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable
-	//	GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO
-	//
-	// set INTE#/GPIO32 as GPO for PCIE_SW
-	RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1);      // GPIO
-	RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0);       // GPO
-	RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6);
-
-	// set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN
-	RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2);      // GPIO
-	RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0);       // GPO
-
-	// set AD9/GPIO9 as GPI for MXM_PRESENT2#
-	RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1);      // GPIO
-	RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5);    // GPI
-
-	// set AD10/GPIO10 as GPI for MXM_PRESENT1#
-	RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1);      // GPIO
-	RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5);    // GPI
-
-	// set GNT1#/GPIO44 as GPO for MXM Reset
-	RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1);      // GPIO
-	RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0);       // GPO
-
-	// set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable
-	RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2);      // GPIO
-	RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0);       // GPO
-
-	// set AD28/GPIO28 as GPI for MXM_PWRGD
-	RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1);      // GPIO
-	RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5);    // GPI
-
-	// set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW)
-	RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3);
-	RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3);
-	RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3);
-	RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x23, BIT3);
-	RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3);
-	RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3);
-
-	//
-	// [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default).
-	//
-	//Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20));
-	//Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20)));
-
-	// check if there any GFX card
-	Flags = 0;
-	// Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL);
-	// Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09);
-	ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8);
-	if (!(Data8 & BIT7))
-	{
-		//Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10);
-		ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8);
-		if (!(Data8 & BIT7))
-		{
-			Flags = 1;
-		}
-	}
-	if (  Flags )
-	{
-		// [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467
-		RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0);
-
-		// [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
-		RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6);
-
-		//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
-		SbStall (10000);
-
-		// Write the GPIO55(MXM_PWR_EN) to enable the integrated power module
-		RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6);
-
-		//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
-		// WAIT POWER READY: GPIO28 (MXM_PWRGD)
-		//while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){}
-		ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
-		while (!(Data8 & BIT7))
-		{
-			ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
-		}
-		// [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset
-		//	RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6);
-	}
-	else
-	{
-		// Write the GPIO55(MXM_PWR_EN) to disable the integrated power module
-		RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0);
-
-		//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
-		SbStall (10000);
-
-		// [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down
-		RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0);
-	}
-
-	//
-	// APU GPP0: On board LAN
-	//	GPIO25: PCIE_RST#_LAN, LOW active
-	//	GPIO63: LAN_CLKREQ#
-	//	GPIO197: LOM_POWER, HIGH Active
-	//	Clock: GPP_CLK3
-	//
-	// Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER
-	RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2);         // GPIO
-	//		RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0);          // GPO
-	RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6);       // output HIGH
-	RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
-
-	// Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN:
-	RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1);          // GPIO
-	//		RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0);           // GPO
-	RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6);        // output HIGH
-	RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3);        // pullup DISABLE
-
-
-	// set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ#
-	RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0);          // CLK_REQ3#
-	RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0);       // Enable GPP_CLK3
-
-	//
-	// APU GPP1: WUSB
-	//	GPIO1: MPCIE_RST2#, LOW active
-	//	GPIO13: WU_DISABLE#, LOW active
-	//	GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default)
-	//
-	// Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable
-	RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2);     // GPIO
-	//		RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0);      // GPO
-	RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0);      // output LOW
-	RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3);   // pullup DISABLE
-
-	// Setup AD01/GPIO01 as GPO for MPCIE_RST2#
-	RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1);      // GPIO
-	//		RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0);       // GPO
-	RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6);    // output LOW
-	RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3);    // pullup DISABLE
-
-	// Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB
-	//		RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1);      // GPIO
-	//		RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0);       // GPO
-	//		RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6);    // output HIGH
-	//		RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3);    // pullup DISABLE
-
-	//
-	// APU GPP2: WWAN
-	//	GPIO0: MPCIE_RST1#, LOW active
-	//	GPIO14: WP_DISABLE#, LOW active
-	//	GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default)
-	//
-	// Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable
-	RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1);     // GPIO
-	//		RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0);      // GPO
-	RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0);      // output LOW
-	RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3);   // pullup DISABLE
-
-	// Set AD00/GPIO00 as GPO for MPCIE_RST1#
-	RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1);      // GPIO
-	//		RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0);       // GPO
-	//		RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6);    // output LOW
-	RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3);    // pullup DISABLE
-
-	// Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN
-	//		RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1);      // GPIO
-	//		RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0);       // GPO
-	//		RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6);
-	//		RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3);
-
-	//
-	// APU GPP3: 1394
-	//	GPIO59: Power control, HIGH active
-	//	GPIO27: PCIE_RST#_1394, LOW active
-	//	GPIO41: CLKREQ#
-	//	Clock: GPP_CLK8
-	//
-	// Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON:
-	RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2);         // GPIO
-	//		RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0);          // GPO
-	RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);       // output HIGH
-	RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
-
-	// Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394
-	RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1);         // GPIO
-	//		RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0);          // GPO
-	RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);       // output HIGH
-	RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
-
-	// set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ#
-	RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1);         // CLK_REQ2#
-
-	// set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C
-	RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1);        // GPIO
-	RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0);         // GPO
-	RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6);       // output HIGH
-	RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
-	//  To fix glitch issue
-	RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0);      // set GPIO_GATE_C to LOW
-	//
-	// Enable/Disable OnBoard LAN
-	//
-	if (!CONFIG_ONBOARD_LAN)
-	{ // 1 - DISABLED
-		RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0);      // LOM_POWER off
-		RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0);
-		RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3);    // PULL UP - DISABLED
-		RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0);     // Disable GPP_CLK3
-	}
-	//		else
-	//		{ // 0 - AUTO
-	//			// set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable)
-	//			RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3);
-	//			RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3);
-	//		}
-
-
-	//
-	// Enable/Disable 1394
-	//
-	if (!CONFIG_ONBOARD_1394)
-	{ // 1 - DISABLED
-		//			RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0);      // set GPIO_GATE_C to LOW
-		RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0);       // 1394 power off
-		RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0);
-		RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3);    // pullup DISABLE
-		RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0);       // DISABLE GPP_CLK8
-		//			RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6);   // set GPIO_GATE_C to HIGH
-	}
-	//		else
-	//		{ // 0 - AUTO
-	//			// set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH)
-	//			RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);
-	//			RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);
-	//
-	//			RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);
-	//			RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3);
-	//		}
-
-	//
-	// external USB 3.0 control:
-	//    amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE
-	//                      GPIO26: PCIE_RST#_USB3.0
-	//                      GPIO46: PCIE_USB30_CLKREQ#
-	//                     GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON
-	//                       Clock: GPP_CLK7
-	//                     GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
-	//	if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) {
-	// disable Onboard NEC USB3.0 controller
-	if (!CONFIG_ONBOARD_USB30) {
-		RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0);
-		RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0);
-		RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3);   // PULL_UP DISABLE
-		RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0);    // DISABLE GPP_CLK7
-		RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0);  // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
-	}
-	//	}
-
-	//
-	// BlueTooth control: BT_ON
-	//    amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE
-	//          GPIO07: BT_ON, 0 - OFF, 1 - ON
-	//
-	if (!CONFIG_ONBOARD_BLUETOOTH) {
-		//-	if (SystemConfiguration.amdBlueTooth == 1) {
-		RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0);
-		//-	}
-	}
-
-	//
-	// WebCam control:
-	//    amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE
-	//       GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF
-	//
-	if (!CONFIG_ONBOARD_WEBCAM) {
-		//-	if (SystemConfiguration.amdWebCam == 1) {
-		RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6);
-		//-	}
-	}
-
-	//
-	// Travis enable:
-	//    amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE
-	//           GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE
-	//
-	if (!CONFIG_ONBOARD_TRAVIS) {
-		//-	if (SystemConfiguration.amdTravisCtrl == 0) {
-		RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6);
-		//-	}
-	}
-
-	//
-	// Disable Light Sensor if needed
-	//
-	if (CONFIG_ONBOARD_LIGHTSENSOR) {
-		//-    if (SystemConfiguration.amdLightSensor == 1) {
-		RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1);
-		//-    }
-	}
-
-}
diff --git a/src/mainboard/amd/dinar/gpio.h b/src/mainboard/amd/dinar/gpio.h
deleted file mode 100644
index e5c1fd398e..0000000000
--- a/src/mainboard/amd/dinar/gpio.h
+++ /dev/null
@@ -1,2296 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _GPIO_H_
-#define _GPIO_H_
-
-#include <stdint.h>
-#include "cbtypes.h"
-
-#define Mmio_Address( BaseAddr, Register ) \
-	( (UINTN)BaseAddr + \
-	  (UINTN)(Register) \
-	)
-
-#define Mmio32_Ptr( BaseAddr, Register ) \
-	( (volatile u32 *)Mmio_Address( BaseAddr, Register ) )
-
-#define Mmio32_G( BaseAddr, Register ) \
-	*Mmio32_Ptr( BaseAddr, Register )
-
-#define Mmio32_And_Or( BaseAddr, Register, AndData, OrData ) \
-	Mmio32_G( BaseAddr, Register ) = \
-(u32) ( \
-		( Mmio32_G( BaseAddr, Register ) & \
-		  (u32)(AndData) \
-		) | \
-		(u32)(OrData) \
-      )
-
-#define Mmio8_Ptr( BaseAddr, Register ) \
-	( (volatile u8 *)Mmio_Address( BaseAddr, Register ) )
-
-#define Mmio8_G( BaseAddr, Register ) \
-	*Mmio8_Ptr( BaseAddr, Register )
-
-#define Mmio8_And_Or( BaseAddr, Register, AndData, OrData ) \
-	Mmio8_G( BaseAddr, Register ) = \
-(u8) ( \
-		( Mmio8_G( BaseAddr, Register ) & \
-		  (u8)(AndData) \
-		) | \
-		(u8)(OrData) \
-     )
-
-#define SMIREG_EVENT_ENABLE 0x04
-#define SMIREG_SCITRIG      0x08
-#define SMIREG_SCILEVEL     0x0C
-#define SMIREG_SMISCIEN     0x14
-#define SMIREG_SCIS0EN      0x20
-#define SMIREG_SCIMAP0      0x40
-#define SMIREG_SCIMAP1      0x44
-#define SMIREG_SCIMAP2      0x48
-#define SMIREG_SCIMAP3      0x4C
-#define SMIREG_SCIMAP4      0x50
-#define SMIREG_SCIMAP5      0x54
-#define SMIREG_SCIMAP6      0x58
-#define SMIREG_SCIMAP7      0x5C
-#define SMIREG_SCIMAP8      0x60
-#define SMIREG_SCIMAP9      0x64
-#define SMIREG_SCIMAP10     0x68
-#define SMIREG_SCIMAP11     0x6C
-#define SMIREG_SCIMAP12     0x70
-#define SMIREG_SCIMAP13     0x74
-#define SMIREG_SCIMAP14     0x78
-#define SMIREG_SCIMAP15     0x7C
-#define SMIREG_SMITRIG      0x98
-#define SMIREG_SMICONTROL0  0xA0
-#define SMIREG_SMICONTROL1  0xA4
-
-#define FUNCTION0           0
-#define FUNCTION1           1
-#define FUNCTION2           2
-#define FUNCTION3           3
-#define NonGpio             0x80				// BIT7
-
-// S0-domain General Purpose I/O: GPIO 00~67
-#define GPIO_00_SELECT      FUNCTION1+NonGpio   // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT
-#define GPIO_01_SELECT      FUNCTION1+NonGpio   // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT
-#define GPIO_02_SELECT      FUNCTION1           // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT
-#define GPIO_03_SELECT      FUNCTION1+NonGpio   // NOT USED
-#define GPIO_04_SELECT      FUNCTION1+NonGpio   // x1 gpp reset, for J3701, low active, HIGH DEFAULT
-#define GPIO_05_SELECT      FUNCTION1+NonGpio   // express card reset, for J2500,  low active, HIGH DEFAULT
-#define GPIO_06_SELECT      FUNCTION0+NonGpio   //NOT USED
-#define GPIO_07_SELECT      FUNCTION1           // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF
-#define GPIO_08_SELECT      FUNCTION1           // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level
-#define GPIO_09_SELECT      FUNCTION1+NonGpio   // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED
-#define GPIO_10_SELECT      FUNCTION1+NonGpio   // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED
-#define GPIO_11_SELECT      FUNCTION0+NonGpio   // NOT USED
-#define GPIO_12_SELECT      FUNCTION1           // WL_DISABLE#, DISABLE THE WALN IN J3702
-#define GPIO_13_SELECT      FUNCTION1           // WU_DISABLE#, DISABLE THE WUSB IN J3711
-#define GPIO_14_SELECT      FUNCTION1           // WP_DISABLE, DISABLE THE WWAN IN J3703
-#define GPIO_15_SELECT      FUNCTION1+NonGpio   // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default
-#define GPIO_16_SELECT      FUNCTION0+NonGpio   // NOT USED
-#define GPIO_17_SELECT      FUNCTION0+NonGpio   // NOT USED
-#define GPIO_18_SELECT      FUNCTION0+NonGpio   // NOT USED
-#define GPIO_19_SELECT      FUNCTION1           // For LASSO_DET# detection when Gevent14# is asserted.
-#define GPIO_20_SELECT      FUNCTION1           // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option)
-#define GPIO_21_SELECT      FUNCTION1           // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option)
-#define GPIO_22_SELECT      FUNCTION1           // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE
-//      1:BATTERY IS FINE(DEFAULT)
-//      0:BATTERY IS LOW
-#define GPIO_23_SELECT      FUNCTION1	        // CODEC_ON.1: CODEC ON (default)0: CODEC OFF
-#define GPIO_24_SELECT      FUNCTION1           // Travis reset,Low active High default
-#define GPIO_25_SELECT      FUNCTION1+NonGpio   // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high
-#define GPIO_26_SELECT      FUNCTION1+NonGpio   // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high
-#define GPIO_27_SELECT      FUNCTION1+NonGpio   // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high
-#define GPIO_28_SELECT      FUNCTION1           // MXM PWRGD INDICATOR, INPUT
-#define GPIO_29_SELECT      FUNCTION1           // MEM HOT, LOW ACTIVE, OUTPUT
-#define GPIO_30_SELECT      FUNCTION1           // INPUT, DEFINE THE BOARD REVISION 0
-#define GPIO_31_SELECT      FUNCTION1           // INPUT, DEFINE THE BOARD REVISION 1
-//      00 - REVA
-//      01 - REVB
-//      10 - REVC
-//      11 - REVD
-#define GPIO_32_SELECT      FUNCTION1+NonGpio   // PCIE_SW - HIGH:MXM; LOW:LASSO
-#define GPIO_33_SELECT      FUNCTION1           // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active.
-//      0:USB3.0 I/F in Express CARD
-//      1:PCIE I/F  in Express CARD detection
-#define GPIO_34_SELECT      FUNCTION1           // WEBCAM_ON#. 0: ON (default) 1: OFF
-#define GPIO_35_SELECT      FUNCTION1           // ODD_DA_INTH#
-#define GPIO_36_SELECT      FUNCTION0+NonGpio   // PCICLK FOR KBC
-#define GPIO_37_SELECT      FUNCTION0+NonGpio   // NOT USED
-#define GPIO_38_SELECT      FUNCTION0+NonGpio   // NOT USED
-#define GPIO_39_SELECT      FUNCTION0+NonGpio   // NOT USED
-#define GPIO_40_SELECT      FUNCTION1           // For DOCK# detection when Gevent14# is asserted.
-#define GPIO_41_SELECT      FUNCTION1+NonGpio   // 1394 CLK REQ#
-#define GPIO_42_SELECT      FUNCTION1+NonGpio   // X4 GPP CLK REQ#
-#define GPIO_43_SELECT      FUNCTION0+NonGpio   // SMBUS0, CLOCK
-#define GPIO_44_SELECT      FUNCTION1+NonGpio   // PEGPIO0, RESET THE MXM MODULE
-#define GPIO_45_SELECT      FUNCTION2+NonGpio   // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF
-#define GPIO_46_SELECT      FUNCTION1+NonGpio   // USB3.0_CLKREQ#
-#define GPIO_47_SELECT      FUNCTION0+NonGpio   // SMBUS0, DATA
-#define GPIO_48_SELECT      FUNCTION0+NonGpio   // SERIRQ
-#define GPIO_49_SELECT      FUNCTION0+NonGpio   // LDRQ#1
-#define GPIO_50_SELECT      FUNCTION2           // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V
-#define GPIO_51_SELECT      FUNCTION0+NonGpio   // back-up for SMARTVOLTAGE1
-#define GPIO_52_SELECT      FUNCTION0+NonGpio   // CPU FAN OUT
-#define GPIO_53_SELECT      FUNCTION1           // ODD POWER ENABLE, HIGH ACTIVE
-#define GPIO_54_SELECT      FUNCTION0+NonGpio   // SB_PROCHOT, OUTPUT, LOW ACTIVE
-#define GPIO_55_SELECT      FUNCTION2+NonGpio   // MXM POWER ENABLE(POWER ON MODULE)
-//      1:ENABLE; 0:DISABLE
-// DEFAULT VALUE DEPENDS ON GPIO 9 AND 10
-#define GPIO_56_SELECT      FUNCTION0+NonGpio   //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN
-#define GPIO_57_SELECT      FUNCTION1           // HDD0_POWER
-#define GPIO_58_SELECT      FUNCTION1           // HDD2_POWER
-#define GPIO_59_SELECT      FUNCTION2+NonGpio   // 1394 POWER, OUTPUT, HIGH ACTIVE
-#define GPIO_60_SELECT      FUNCTION0+NonGpio   // EXPCARD_CLKREQ#
-#define GPIO_61_SELECT      FUNCTION0+NonGpio   // PE0_CLKREQ#, FROM J3700
-#define GPIO_62_SELECT      FUNCTION0+NonGpio   // PE2_CLKREQ#, FROM J3711
-#define GPIO_63_SELECT      FUNCTION0+NonGpio   // LAN_CLKREQ#
-#define GPIO_64_SELECT      FUNCTION0+NonGpio   // PE1_CLKREQ#, FROM J3703
-#define GPIO_65_SELECT      FUNCTION0+NonGpio   // MXM CLK REQ#, FROM MXM
-#define GPIO_66_SELECT      FUNCTION1           // USED AS TRAVIS_EN#; 0:ENABLE as default
-#define GPIO_67_SELECT      FUNCTION0+NonGpio   // USED AS SATA_ACT#
-#define GPIO_68_SELECT      FUNCTION0+NonGpio
-#define GPIO_69_SELECT      FUNCTION0+NonGpio
-#define GPIO_70_SELECT      FUNCTION0+NonGpio
-#define GPIO_71_SELECT      FUNCTION0+NonGpio
-#define GPIO_72_SELECT      FUNCTION0+NonGpio
-#define GPIO_73_SELECT      FUNCTION0+NonGpio
-#define GPIO_74_SELECT      FUNCTION0+NonGpio
-#define GPIO_75_SELECT      FUNCTION0+NonGpio
-#define GPIO_76_SELECT      FUNCTION0+NonGpio
-#define GPIO_77_SELECT      FUNCTION0+NonGpio
-#define GPIO_78_SELECT      FUNCTION0+NonGpio
-#define GPIO_79_SELECT      FUNCTION0+NonGpio
-#define GPIO_80_SELECT      FUNCTION0+NonGpio
-#define GPIO_81_SELECT      FUNCTION0+NonGpio
-#define GPIO_82_SELECT      FUNCTION0+NonGpio
-#define GPIO_83_SELECT      FUNCTION0+NonGpio
-#define GPIO_84_SELECT      FUNCTION0+NonGpio
-#define GPIO_85_SELECT      FUNCTION0+NonGpio
-#define GPIO_86_SELECT      FUNCTION0+NonGpio
-#define GPIO_87_SELECT      FUNCTION0+NonGpio
-#define GPIO_88_SELECT      FUNCTION0+NonGpio
-#define GPIO_89_SELECT      FUNCTION0+NonGpio
-#define GPIO_90_SELECT      FUNCTION0+NonGpio
-#define GPIO_91_SELECT      FUNCTION0+NonGpio
-#define GPIO_92_SELECT      FUNCTION0+NonGpio
-#define GPIO_93_SELECT      FUNCTION0+NonGpio
-#define GPIO_94_SELECT      FUNCTION0+NonGpio
-#define GPIO_95_SELECT      FUNCTION0+NonGpio
-// GEVENT 00~23 are mapped to GPIO 96~119
-#define GPIO_96_SELECT      FUNCTION0           // GA20IN/GEVENT0#
-#define GPIO_97_SELECT      FUNCTION0           // KBRST#/GEVENT1#
-#define GPIO_98_SELECT      FUNCTION0           // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP
-#define GPIO_99_SELECT      FUNCTION1           // LPC_PME#/GEVENT3# -> EC_SCI#
-#define GPIO_100_SELECT     FUNCTION2           // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT#
-#define GPIO_101_SELECT     FUNCTION1           // LPC_PD#/GEVENT5# -> hotplug of express card, low active
-#define GPIO_102_SELECT     FUNCTION0+NonGpio   // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED,
-// there is a confliction to IR function when this pin is as a GEVENT.
-#define GPIO_103_SELECT     FUNCTION0+NonGpio   // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD,
-// special pin difination for SB700 VGA OUTPUT, high active,
-// VGA power for Hudson-M2 will be down when it was asserted.
-#define GPIO_104_SELECT     FUNCTION0           // WAKE#/GEVENT8# -> WAKEUP, low active
-#define GPIO_105_SELECT     FUNCTION2           // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio)
-#define GPIO_106_SELECT     FUNCTION0           // GBE_LED2/GEVENT10# -> GBE_LED2
-#define GPIO_107_SELECT     FUNCTION0+NonGpio   // GBE_STAT0/GEVENT11# -> GBE_STAT0
-#define GPIO_108_SELECT     FUNCTION2           // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active
-// [option for SPI_TPM_CS# in Hudson-M2 A12)]
-#define GPIO_109_SELECT     FUNCTION0           // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) &
-//  USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time
-#define GPIO_110_SELECT     FUNCTION2           // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect,
-// plus judge GPIO40 and GPIO19 level,low is assert.
-//      LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default)
-//      DOCK#:0 & GPIO40:0 -----------> DOCK is present(option)
-#define GPIO_111_SELECT     FUNCTION1+NonGpio	// USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active
-#define GPIO_112_SELECT     FUNCTION2           // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention,
-// low active, when it's low, BIOS will enbale ODD_PWR
-#define GPIO_113_SELECT     FUNCTION2			// USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17#
-#define GPIO_114_SELECT     FUNCTION2           // BLINK/USB_OC7#/GEVENT18# -> BLINK
-#define GPIO_115_SELECT     FUNCTION0           // SYS_RESET#/GEVENT19# -> SYS_RST#
-#define GPIO_116_SELECT     FUNCTION0           // R_RX1/GEVENT20# -> IR INPUT
-#define GPIO_117_SELECT     FUNCTION1+NonGpio   // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1
-#define GPIO_118_SELECT     FUNCTION1           // RI#/GEVENT22# -> LID_CLOSED#
-#define GPIO_119_SELECT     FUNCTION0           // LPC_SMI#/GEVENT23# -> EC_SMI
-#define GPIO_120_SELECT     FUNCTION0+NonGpio
-#define GPIO_121_SELECT     FUNCTION0+NonGpio
-#define GPIO_122_SELECT     FUNCTION0+NonGpio
-#define GPIO_123_SELECT     FUNCTION0+NonGpio
-#define GPIO_124_SELECT     FUNCTION0+NonGpio
-#define GPIO_125_SELECT     FUNCTION0+NonGpio
-#define GPIO_126_SELECT     FUNCTION0+NonGpio
-#define GPIO_127_SELECT     FUNCTION0+NonGpio
-#define GPIO_128_SELECT     FUNCTION0+NonGpio
-#define GPIO_129_SELECT     FUNCTION0+NonGpio
-#define GPIO_130_SELECT     FUNCTION0+NonGpio
-#define GPIO_131_SELECT     FUNCTION0+NonGpio
-#define GPIO_132_SELECT     FUNCTION0+NonGpio
-#define GPIO_133_SELECT     FUNCTION0+NonGpio
-#define GPIO_134_SELECT     FUNCTION0+NonGpio
-#define GPIO_135_SELECT     FUNCTION0+NonGpio
-#define GPIO_136_SELECT     FUNCTION0+NonGpio
-#define GPIO_137_SELECT     FUNCTION0+NonGpio
-#define GPIO_138_SELECT     FUNCTION0+NonGpio
-#define GPIO_139_SELECT     FUNCTION0+NonGpio
-#define GPIO_140_SELECT     FUNCTION0+NonGpio
-#define GPIO_141_SELECT     FUNCTION0+NonGpio
-#define GPIO_142_SELECT     FUNCTION0+NonGpio
-#define GPIO_143_SELECT     FUNCTION0+NonGpio
-#define GPIO_144_SELECT     FUNCTION0+NonGpio
-#define GPIO_145_SELECT     FUNCTION0+NonGpio
-#define GPIO_146_SELECT     FUNCTION0+NonGpio
-#define GPIO_147_SELECT     FUNCTION0+NonGpio
-#define GPIO_148_SELECT     FUNCTION0+NonGpio
-#define GPIO_149_SELECT     FUNCTION0+NonGpio
-#define GPIO_150_SELECT     FUNCTION0+NonGpio
-#define GPIO_151_SELECT     FUNCTION0+NonGpio
-#define GPIO_152_SELECT     FUNCTION0+NonGpio
-#define GPIO_153_SELECT     FUNCTION0+NonGpio
-#define GPIO_154_SELECT     FUNCTION0+NonGpio
-#define GPIO_155_SELECT     FUNCTION0+NonGpio
-#define GPIO_156_SELECT     FUNCTION0+NonGpio
-#define GPIO_157_SELECT     FUNCTION0+NonGpio
-#define GPIO_158_SELECT     FUNCTION0+NonGpio
-#define GPIO_159_SELECT     FUNCTION0+NonGpio
-#define GPIO_160_SELECT     FUNCTION0+NonGpio
-
-// S5-domain General Purpose I/O
-#define GPIO_161_SELECT     FUNCTION0+NonGpio   // ROM_RST#
-#define GPIO_162_SELECT     FUNCTION0+NonGpio   // SPI ROM
-#define GPIO_163_SELECT     FUNCTION0+NonGpio   // SPI ROM
-#define GPIO_164_SELECT     FUNCTION0+NonGpio   // SPI ROM
-#define GPIO_165_SELECT     FUNCTION0+NonGpio   // SPI ROM
-#define GPIO_166_SELECT     FUNCTION1+NonGpio   // GBE_STAT2
-#define GPIO_167_SELECT     FUNCTION0+NonGpio   // AZ_SDATA_IN0
-#define GPIO_168_SELECT     FUNCTION0+NonGpio   // AZ_SDATA_IN1
-#define GPIO_169_SELECT     FUNCTION0+NonGpio   // AZ_SDATA_IN2
-#define GPIO_170_SELECT     FUNCTION1+NonGpio   // gating the power control signal for ODD, see BIOS requirements doc for detail.
-#define GPIO_171_SELECT     FUNCTION0+NonGpio   // TEMPIN0,
-#define GPIO_172_SELECT     FUNCTION1           // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE
-#define GPIO_173_SELECT     FUNCTION0+NonGpio   // TEMPIN3
-#define GPIO_174_SELECT     FUNCTION1+NonGpio   // USED AS TALERT#
-#define GPIO_175_SELECT     FUNCTION1           // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE
-#define GPIO_176_SELECT     FUNCTION1+NonGpio   // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE
-#define GPIO_177_SELECT     FUNCTION2+NonGpio   // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE
-#define GPIO_178_SELECT     FUNCTION2           // MEM_1V5
-#define GPIO_179_SELECT     FUNCTION2           // MEM_1V35
-#define GPIO_180_SELECT     FUNCTION0+NonGpio   // Use as VIN VDDIO
-#define GPIO_181_SELECT     FUNCTION0+NonGpio   // Use as VIN VDDR
-#define GPIO_182_SELECT     FUNCTION1+NonGpio   // GBE_LED3
-#define GPIO_183_SELECT     FUNCTION0+NonGpio   // GBE_LED0
-#define GPIO_184_SELECT     FUNCTION1+NonGpio   // USED AS LLB#
-#define GPIO_185_SELECT     FUNCTION0+NonGpio   // USED AS USB
-#define GPIO_186_SELECT     FUNCTION0+NonGpio   // USED AS USB
-#define GPIO_187_SELECT     FUNCTION2           // USED AS AC LED INDICATOR, LOW ACTIVE
-#define GPIO_188_SELECT     FUNCTION2           // default used AS BATT LED INDICATOR, LOW ACTIVE
-// option for HDMI CEC signal OW ACTIVE
-#define GPIO_189_SELECT     FUNCTION1           // USED AS AC_OK RECIEVER, INPUT, low active
-#define GPIO_190_SELECT     FUNCTION1           // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT
-#define GPIO_191_SELECT     FUNCTION0+NonGpio   // TOUCH PAD, DATA
-#define GPIO_192_SELECT     FUNCTION0+NonGpio   // TOUCH PAD, CLK
-#define GPIO_193_SELECT     FUNCTION0+NonGpio   // SMBUS CLK,
-#define GPIO_194_SELECT     FUNCTION0+NonGpio   // SMBUS, DATA
-#define GPIO_195_SELECT     FUNCTION0+NonGpio   // SMBUS CLK,
-#define GPIO_196_SELECT     FUNCTION0+NonGpio   // SMBUS, DATA
-#define GPIO_197_SELECT     FUNCTION2+NonGpio   // Default GPIO for LOM_POWER, high active
-// RESERVED FOR LCD BACKLIGHT PWM
-#define GPIO_198_SELECT     FUNCTION0+NonGpio   // IMC SCROLL LED CONTROL
-#define GPIO_199_SELECT     FUNCTION3           // STRAP TO SELECT BOOT ROM - H:LPC ROM   L: SPI ROM
-#define GPIO_200_SELECT     FUNCTION2           // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF
-#define GPIO_201_SELECT     FUNCTION0+NonGpio   // KSI
-#define GPIO_202_SELECT     FUNCTION0+NonGpio   // KSI
-#define GPIO_203_SELECT     FUNCTION0+NonGpio   // KSI
-#define GPIO_204_SELECT     FUNCTION0+NonGpio   // KSI
-#define GPIO_205_SELECT     FUNCTION0+NonGpio   // KSI
-#define GPIO_206_SELECT     FUNCTION0+NonGpio   // KSI
-#define GPIO_207_SELECT     FUNCTION0+NonGpio   // KSI
-#define GPIO_208_SELECT     FUNCTION0+NonGpio   // KSI
-#define GPIO_209_SELECT     FUNCTION0+NonGpio   // KSO
-#define GPIO_210_SELECT     FUNCTION0+NonGpio   // KSO
-#define GPIO_211_SELECT     FUNCTION0+NonGpio   // KSO
-#define GPIO_212_SELECT     FUNCTION0+NonGpio   // KSO
-#define GPIO_213_SELECT     FUNCTION0+NonGpio   // KSO
-#define GPIO_214_SELECT     FUNCTION0+NonGpio   // KSO
-#define GPIO_215_SELECT     FUNCTION0+NonGpio   // KSO
-#define GPIO_216_SELECT     FUNCTION0+NonGpio   // KSO
-#define GPIO_217_SELECT     FUNCTION0+NonGpio   // KSO
-#define GPIO_218_SELECT     FUNCTION0+NonGpio   // KSO
-#define GPIO_219_SELECT     FUNCTION0+NonGpio   // KSO
-#define GPIO_220_SELECT     FUNCTION0+NonGpio   // KSO
-#define GPIO_221_SELECT     FUNCTION0+NonGpio   // KSO
-#define GPIO_222_SELECT     FUNCTION0+NonGpio   // KSO
-#define GPIO_223_SELECT     FUNCTION0+NonGpio   // KSO
-#define GPIO_224_SELECT     FUNCTION0+NonGpio   // KSO
-#define GPIO_225_SELECT     FUNCTION2+NonGpio   // KSO
-#define GPIO_226_SELECT     FUNCTION2+NonGpio   // KSO
-#define GPIO_227_SELECT     FUNCTION0+NonGpio   // SMBUS CLK,
-#define GPIO_228_SELECT     FUNCTION0+NonGpio   // SMBUS, DATA
-#define GPIO_229_SELECT     FUNCTION0+NonGpio   // DP1_HPD
-
-#define TYPE_GPI  (1 << 5)
-#define TYPE_GPO  (0 << 5)
-
-#define GPIO_00_TYPE        TYPE_GPO
-#define GPIO_01_TYPE        TYPE_GPO
-#define GPIO_02_TYPE        TYPE_GPO
-#define GPIO_03_TYPE        TYPE_GPO
-#define GPIO_04_TYPE        TYPE_GPO
-#define GPIO_05_TYPE        TYPE_GPO
-#define GPIO_06_TYPE        TYPE_GPO
-#define GPIO_07_TYPE        TYPE_GPO
-#define GPIO_08_TYPE        TYPE_GPO
-#define GPIO_09_TYPE        TYPE_GPI
-#define GPIO_10_TYPE        TYPE_GPI
-#define GPIO_11_TYPE        TYPE_GPO
-#define GPIO_12_TYPE        TYPE_GPO
-#define GPIO_13_TYPE        TYPE_GPO
-#define GPIO_14_TYPE        TYPE_GPO
-#define GPIO_15_TYPE        TYPE_GPO
-#define GPIO_16_TYPE        TYPE_GPO
-#define GPIO_17_TYPE        TYPE_GPO
-#define GPIO_18_TYPE        TYPE_GPO
-#define GPIO_19_TYPE        TYPE_GPO
-#define GPIO_20_TYPE        TYPE_GPO
-#define GPIO_21_TYPE        TYPE_GPO
-#define GPIO_22_TYPE        TYPE_GPO
-#define GPIO_23_TYPE        TYPE_GPO
-#define GPIO_24_TYPE        TYPE_GPO
-#define GPIO_25_TYPE        TYPE_GPO
-#define GPIO_26_TYPE        TYPE_GPO
-#define GPIO_27_TYPE        TYPE_GPO
-#define GPIO_28_TYPE        TYPE_GPI
-#define GPIO_29_TYPE        TYPE_GPO
-#define GPIO_30_TYPE        TYPE_GPI
-#define GPIO_31_TYPE        TYPE_GPI
-#define GPIO_32_TYPE        TYPE_GPO
-#define GPIO_33_TYPE        TYPE_GPI
-#define GPIO_34_TYPE        TYPE_GPO
-#define GPIO_35_TYPE        TYPE_GPO
-#define GPIO_36_TYPE        TYPE_GPO
-#define GPIO_37_TYPE        TYPE_GPO
-#define GPIO_38_TYPE        TYPE_GPO
-#define GPIO_39_TYPE        TYPE_GPO
-#define GPIO_40_TYPE        TYPE_GPO
-#define GPIO_41_TYPE        TYPE_GPI
-#define GPIO_42_TYPE        TYPE_GPI
-#define GPIO_43_TYPE        TYPE_GPO
-#define GPIO_44_TYPE        TYPE_GPO
-#define GPIO_45_TYPE        TYPE_GPO
-#define GPIO_46_TYPE        TYPE_GPI
-#define GPIO_47_TYPE        TYPE_GPO
-#define GPIO_48_TYPE        TYPE_GPO
-#define GPIO_49_TYPE        TYPE_GPO
-#define GPIO_50_TYPE        TYPE_GPO
-#define GPIO_51_TYPE        TYPE_GPO
-#define GPIO_52_TYPE        TYPE_GPO
-#define GPIO_53_TYPE        TYPE_GPO
-#define GPIO_54_TYPE        TYPE_GPO
-#define GPIO_55_TYPE        TYPE_GPO
-#define GPIO_56_TYPE        TYPE_GPI
-#define GPIO_57_TYPE        TYPE_GPO
-#define GPIO_58_TYPE        TYPE_GPO
-#define GPIO_59_TYPE        TYPE_GPO
-#define GPIO_60_TYPE        TYPE_GPI
-#define GPIO_61_TYPE        TYPE_GPI
-#define GPIO_62_TYPE        TYPE_GPI
-#define GPIO_63_TYPE        TYPE_GPI
-#define GPIO_64_TYPE        TYPE_GPI
-#define GPIO_65_TYPE        TYPE_GPI
-#define GPIO_66_TYPE        TYPE_GPO
-#define GPIO_67_TYPE        TYPE_GPO
-#define GPIO_68_TYPE        TYPE_GPO
-#define GPIO_69_TYPE        TYPE_GPO
-#define GPIO_70_TYPE        TYPE_GPO
-#define GPIO_71_TYPE        TYPE_GPO
-#define GPIO_72_TYPE        TYPE_GPO
-#define GPIO_73_TYPE        TYPE_GPO
-#define GPIO_74_TYPE        TYPE_GPO
-#define GPIO_75_TYPE        TYPE_GPO
-#define GPIO_76_TYPE        TYPE_GPO
-#define GPIO_77_TYPE        TYPE_GPO
-#define GPIO_78_TYPE        TYPE_GPO
-#define GPIO_79_TYPE        TYPE_GPO
-#define GPIO_80_TYPE        TYPE_GPO
-#define GPIO_81_TYPE        TYPE_GPO
-#define GPIO_82_TYPE        TYPE_GPO
-#define GPIO_83_TYPE        TYPE_GPO
-#define GPIO_84_TYPE        TYPE_GPO
-#define GPIO_85_TYPE        TYPE_GPO
-#define GPIO_86_TYPE        TYPE_GPO
-#define GPIO_87_TYPE        TYPE_GPO
-#define GPIO_88_TYPE        TYPE_GPO
-#define GPIO_89_TYPE        TYPE_GPO
-#define GPIO_90_TYPE        TYPE_GPO
-#define GPIO_91_TYPE        TYPE_GPO
-#define GPIO_92_TYPE        TYPE_GPO
-#define GPIO_93_TYPE        TYPE_GPO
-#define GPIO_94_TYPE        TYPE_GPO
-#define GPIO_95_TYPE        TYPE_GPO
-
-// GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119
-#define GPIO_96_TYPE        TYPE_GPI
-#define GPIO_97_TYPE        TYPE_GPI
-#define GPIO_98_TYPE        TYPE_GPI
-#define GPIO_99_TYPE        TYPE_GPI
-#define GPIO_100_TYPE       TYPE_GPI
-#define GPIO_101_TYPE       TYPE_GPI
-#define GPIO_102_TYPE       TYPE_GPO
-#define GPIO_103_TYPE       TYPE_GPO
-#define GPIO_104_TYPE       TYPE_GPI
-#define GPIO_105_TYPE       TYPE_GPI
-#define GPIO_106_TYPE       TYPE_GPO
-#define GPIO_107_TYPE       TYPE_GPI
-#define GPIO_108_TYPE       TYPE_GPI
-#define GPIO_109_TYPE       TYPE_GPI
-#define GPIO_110_TYPE       TYPE_GPI
-#define GPIO_111_TYPE       TYPE_GPI
-#define GPIO_112_TYPE       TYPE_GPI
-#define GPIO_113_TYPE       TYPE_GPI
-#define GPIO_114_TYPE       TYPE_GPO
-#define GPIO_115_TYPE       TYPE_GPI
-#define GPIO_116_TYPE       TYPE_GPI
-#define GPIO_117_TYPE       TYPE_GPI
-#define GPIO_118_TYPE       TYPE_GPI
-#define GPIO_119_TYPE       TYPE_GPI
-
-#define GPIO_120_TYPE       TYPE_GPO
-#define GPIO_121_TYPE       TYPE_GPO
-#define GPIO_122_TYPE       TYPE_GPO
-#define GPIO_123_TYPE       TYPE_GPO
-#define GPIO_124_TYPE       TYPE_GPO
-#define GPIO_125_TYPE       TYPE_GPO
-#define GPIO_126_TYPE       TYPE_GPO
-#define GPIO_127_TYPE       TYPE_GPO
-#define GPIO_128_TYPE       TYPE_GPO
-#define GPIO_129_TYPE       TYPE_GPO
-#define GPIO_130_TYPE       TYPE_GPO
-#define GPIO_131_TYPE       TYPE_GPO
-#define GPIO_132_TYPE       TYPE_GPO
-#define GPIO_133_TYPE       TYPE_GPO
-#define GPIO_134_TYPE       TYPE_GPO
-#define GPIO_135_TYPE       TYPE_GPO
-#define GPIO_136_TYPE       TYPE_GPO
-#define GPIO_137_TYPE       TYPE_GPO
-#define GPIO_138_TYPE       TYPE_GPO
-#define GPIO_139_TYPE       TYPE_GPO
-#define GPIO_140_TYPE       TYPE_GPO
-#define GPIO_141_TYPE       TYPE_GPO
-#define GPIO_142_TYPE       TYPE_GPO
-#define GPIO_143_TYPE       TYPE_GPO
-#define GPIO_144_TYPE       TYPE_GPO
-#define GPIO_145_TYPE       TYPE_GPO
-#define GPIO_146_TYPE       TYPE_GPO
-#define GPIO_147_TYPE       TYPE_GPO
-#define GPIO_148_TYPE       TYPE_GPO
-#define GPIO_149_TYPE       TYPE_GPO
-#define GPIO_150_TYPE       TYPE_GPO
-#define GPIO_151_TYPE       TYPE_GPO
-#define GPIO_152_TYPE       TYPE_GPO
-#define GPIO_153_TYPE       TYPE_GPO
-#define GPIO_154_TYPE       TYPE_GPO
-#define GPIO_155_TYPE       TYPE_GPO
-#define GPIO_156_TYPE       TYPE_GPO
-#define GPIO_157_TYPE       TYPE_GPO
-#define GPIO_158_TYPE       TYPE_GPO
-#define GPIO_159_TYPE       TYPE_GPO
-#define GPIO_160_TYPE       TYPE_GPO
-#define GPIO_161_TYPE       TYPE_GPO
-#define GPIO_162_TYPE       TYPE_GPO
-#define GPIO_163_TYPE       TYPE_GPO
-#define GPIO_164_TYPE       TYPE_GPI
-#define GPIO_165_TYPE       TYPE_GPO
-#define GPIO_166_TYPE       TYPE_GPI
-#define GPIO_167_TYPE       TYPE_GPI
-#define GPIO_168_TYPE       TYPE_GPI
-#define GPIO_169_TYPE       TYPE_GPI
-#define GPIO_170_TYPE       TYPE_GPO
-#define GPIO_171_TYPE       TYPE_GPI
-#define GPIO_172_TYPE       TYPE_GPO
-#define GPIO_173_TYPE       TYPE_GPI
-#define GPIO_174_TYPE       TYPE_GPI
-#define GPIO_175_TYPE       TYPE_GPO
-#define GPIO_176_TYPE       TYPE_GPO
-#define GPIO_177_TYPE       TYPE_GPO
-#define GPIO_178_TYPE       TYPE_GPO
-#define GPIO_179_TYPE       TYPE_GPO
-#define GPIO_180_TYPE       TYPE_GPO
-#define GPIO_181_TYPE       TYPE_GPO
-#define GPIO_182_TYPE       TYPE_GPO
-#define GPIO_183_TYPE       TYPE_GPO
-#define GPIO_184_TYPE       TYPE_GPI
-#define GPIO_185_TYPE       TYPE_GPO
-#define GPIO_186_TYPE       TYPE_GPO
-#define GPIO_187_TYPE       TYPE_GPO
-#define GPIO_188_TYPE       TYPE_GPO
-#define GPIO_189_TYPE       TYPE_GPI
-#define GPIO_190_TYPE       TYPE_GPI
-#define GPIO_191_TYPE       TYPE_GPO
-#define GPIO_192_TYPE       TYPE_GPO
-#define GPIO_193_TYPE       TYPE_GPO
-#define GPIO_194_TYPE       TYPE_GPO
-#define GPIO_195_TYPE       TYPE_GPO
-#define GPIO_196_TYPE       TYPE_GPO
-#define GPIO_197_TYPE       TYPE_GPO
-#define GPIO_198_TYPE       TYPE_GPO
-#define GPIO_199_TYPE       TYPE_GPI
-#define GPIO_200_TYPE       TYPE_GPO
-#define GPIO_201_TYPE       TYPE_GPI
-#define GPIO_202_TYPE       TYPE_GPI
-#define GPIO_203_TYPE       TYPE_GPI
-#define GPIO_204_TYPE       TYPE_GPI
-#define GPIO_205_TYPE       TYPE_GPI
-#define GPIO_206_TYPE       TYPE_GPI
-#define GPIO_207_TYPE       TYPE_GPI
-#define GPIO_208_TYPE       TYPE_GPI
-#define GPIO_209_TYPE       TYPE_GPO
-#define GPIO_210_TYPE       TYPE_GPO
-#define GPIO_211_TYPE       TYPE_GPO
-#define GPIO_212_TYPE       TYPE_GPO
-#define GPIO_213_TYPE       TYPE_GPO
-#define GPIO_214_TYPE       TYPE_GPO
-#define GPIO_215_TYPE       TYPE_GPO
-#define GPIO_216_TYPE       TYPE_GPO
-#define GPIO_217_TYPE       TYPE_GPO
-#define GPIO_218_TYPE       TYPE_GPO
-#define GPIO_219_TYPE       TYPE_GPO
-#define GPIO_220_TYPE       TYPE_GPO
-#define GPIO_221_TYPE       TYPE_GPO
-#define GPIO_222_TYPE       TYPE_GPO
-#define GPIO_223_TYPE       TYPE_GPO
-#define GPIO_224_TYPE       TYPE_GPO
-#define GPIO_225_TYPE       TYPE_GPO
-#define GPIO_226_TYPE       TYPE_GPO
-#define GPIO_227_TYPE       TYPE_GPO
-#define GPIO_228_TYPE       TYPE_GPO
-#define GPIO_229_TYPE       TYPE_GPO
-
-#define GPO_LOW   (0 << 6)
-#define GPO_HI    (1 << 6)
-
-#define GPO_00_LEVEL        GPO_HI
-#define GPO_01_LEVEL        GPO_HI
-#define GPO_02_LEVEL        GPO_HI
-#define GPO_03_LEVEL        GPO_HI
-#define GPO_04_LEVEL        GPO_HI
-#define GPO_05_LEVEL        GPO_HI
-#define GPO_06_LEVEL        GPO_HI
-#define GPO_07_LEVEL        GPO_HI
-#define GPO_08_LEVEL        GPO_HI
-#define GPO_09_LEVEL        GPO_LOW
-#define GPO_10_LEVEL        GPO_LOW
-#define GPO_11_LEVEL        GPO_HI
-#define GPO_12_LEVEL        GPO_HI
-#define GPO_13_LEVEL        GPO_HI
-#define GPO_14_LEVEL        GPO_HI
-#define GPO_15_LEVEL        GPO_HI
-#define GPO_16_LEVEL        GPO_HI
-#define GPO_17_LEVEL        GPO_HI
-#define GPO_18_LEVEL        GPO_HI
-#define GPO_19_LEVEL        GPO_LOW
-#define GPO_20_LEVEL        GPO_LOW
-#define GPO_21_LEVEL        GPO_LOW
-#define GPO_22_LEVEL        GPO_HI
-#define GPO_23_LEVEL        GPO_HI
-#define GPO_24_LEVEL        GPO_HI
-#define GPO_25_LEVEL        GPO_HI
-#define GPO_26_LEVEL        GPO_HI
-#define GPO_27_LEVEL        GPO_HI
-#define GPO_28_LEVEL        GPO_LOW
-#define GPO_29_LEVEL        GPO_HI
-#define GPO_30_LEVEL        GPO_LOW
-#define GPO_31_LEVEL        GPO_LOW
-#define GPO_32_LEVEL        GPO_HI
-#define GPO_33_LEVEL        GPO_LOW
-#define GPO_34_LEVEL        GPO_LOW
-#define GPO_35_LEVEL        GPO_LOW
-#define GPO_36_LEVEL        GPO_LOW
-#define GPO_37_LEVEL        GPO_HI
-#define GPO_38_LEVEL        GPO_HI
-#define GPO_39_LEVEL        GPO_HI
-#define GPO_40_LEVEL        GPO_LOW
-#define GPO_41_LEVEL        GPO_LOW
-#define GPO_42_LEVEL        GPO_LOW
-#define GPO_43_LEVEL        GPO_LOW
-#define GPO_44_LEVEL        GPO_HI
-#define GPO_45_LEVEL        GPO_HI
-#define GPO_46_LEVEL        GPO_LOW
-#define GPO_47_LEVEL        GPO_LOW
-#define GPO_48_LEVEL        GPO_LOW
-#define GPO_49_LEVEL        GPO_HI
-#define GPO_50_LEVEL        GPO_HI
-#define GPO_51_LEVEL        GPO_LOW
-#define GPO_52_LEVEL        GPO_HI
-#define GPO_53_LEVEL        GPO_HI
-#define GPO_54_LEVEL        GPO_LOW
-#define GPO_55_LEVEL        GPO_LOW
-#define GPO_56_LEVEL        GPO_LOW
-#define GPO_57_LEVEL        GPO_HI
-#define GPO_58_LEVEL        GPO_HI
-#define GPO_59_LEVEL        GPO_HI
-#define GPO_60_LEVEL        GPO_LOW
-#define GPO_61_LEVEL        GPO_LOW
-#define GPO_62_LEVEL        GPO_LOW
-#define GPO_63_LEVEL        GPO_LOW
-#define GPO_64_LEVEL        GPO_LOW
-#define GPO_65_LEVEL        GPO_LOW
-#define GPO_66_LEVEL        GPO_LOW
-#define GPO_67_LEVEL        GPO_LOW
-#define GPO_68_LEVEL        GPO_LOW
-#define GPO_69_LEVEL        GPO_LOW
-#define GPO_70_LEVEL        GPO_LOW
-#define GPO_71_LEVEL        GPO_LOW
-#define GPO_72_LEVEL        GPO_LOW
-#define GPO_73_LEVEL        GPO_LOW
-#define GPO_74_LEVEL        GPO_LOW
-#define GPO_75_LEVEL        GPO_LOW
-#define GPO_76_LEVEL        GPO_LOW
-#define GPO_77_LEVEL        GPO_LOW
-#define GPO_78_LEVEL        GPO_LOW
-#define GPO_79_LEVEL        GPO_LOW
-#define GPO_80_LEVEL        GPO_LOW
-#define GPO_81_LEVEL        GPO_LOW
-#define GPO_82_LEVEL        GPO_LOW
-#define GPO_83_LEVEL        GPO_LOW
-#define GPO_84_LEVEL        GPO_LOW
-#define GPO_85_LEVEL        GPO_LOW
-#define GPO_86_LEVEL        GPO_LOW
-#define GPO_87_LEVEL        GPO_LOW
-#define GPO_88_LEVEL        GPO_LOW
-#define GPO_89_LEVEL        GPO_LOW
-#define GPO_90_LEVEL        GPO_LOW
-#define GPO_91_LEVEL        GPO_LOW
-#define GPO_92_LEVEL        GPO_LOW
-#define GPO_93_LEVEL        GPO_LOW
-#define GPO_94_LEVEL        GPO_LOW
-#define GPO_95_LEVEL        GPO_LOW
-#define GPO_96_LEVEL        GPO_LOW
-#define GPO_97_LEVEL        GPO_LOW
-#define GPO_98_LEVEL        GPO_LOW
-#define GPO_99_LEVEL        GPO_LOW
-#define GPO_100_LEVEL       GPO_LOW
-#define GPO_101_LEVEL       GPO_LOW
-#define GPO_102_LEVEL       GPO_LOW
-#define GPO_103_LEVEL       GPO_LOW
-#define GPO_104_LEVEL       GPO_LOW
-#define GPO_105_LEVEL       GPO_LOW
-#define GPO_106_LEVEL       GPO_LOW
-#define GPO_107_LEVEL       GPO_LOW
-#define GPO_108_LEVEL       GPO_HI
-#define GPO_109_LEVEL       GPO_LOW
-#define GPO_110_LEVEL       GPO_HI
-#define GPO_111_LEVEL       GPO_HI
-#define GPO_112_LEVEL       GPO_HI
-#define GPO_113_LEVEL       GPO_LOW
-#define GPO_114_LEVEL       GPO_LOW
-#define GPO_115_LEVEL       GPO_LOW
-#define GPO_116_LEVEL       GPO_LOW
-#define GPO_117_LEVEL       GPO_LOW
-#define GPO_118_LEVEL       GPO_LOW
-#define GPO_119_LEVEL       GPO_LOW
-#define GPO_120_LEVEL       GPO_LOW
-#define GPO_121_LEVEL       GPO_LOW
-#define GPO_122_LEVEL       GPO_LOW
-#define GPO_123_LEVEL       GPO_LOW
-#define GPO_124_LEVEL       GPO_LOW
-#define GPO_125_LEVEL       GPO_LOW
-#define GPO_126_LEVEL       GPO_LOW
-#define GPO_127_LEVEL       GPO_LOW
-#define GPO_128_LEVEL       GPO_LOW
-#define GPO_129_LEVEL       GPO_LOW
-#define GPO_130_LEVEL       GPO_LOW
-#define GPO_131_LEVEL       GPO_LOW
-#define GPO_132_LEVEL       GPO_LOW
-#define GPO_133_LEVEL       GPO_LOW
-#define GPO_134_LEVEL       GPO_LOW
-#define GPO_135_LEVEL       GPO_LOW
-#define GPO_136_LEVEL       GPO_LOW
-#define GPO_137_LEVEL       GPO_LOW
-#define GPO_138_LEVEL       GPO_LOW
-#define GPO_139_LEVEL       GPO_LOW
-#define GPO_140_LEVEL       GPO_LOW
-#define GPO_141_LEVEL       GPO_LOW
-#define GPO_142_LEVEL       GPO_LOW
-#define GPO_143_LEVEL       GPO_LOW
-#define GPO_144_LEVEL       GPO_LOW
-#define GPO_145_LEVEL       GPO_LOW
-#define GPO_146_LEVEL       GPO_LOW
-#define GPO_147_LEVEL       GPO_LOW
-#define GPO_148_LEVEL       GPO_LOW
-#define GPO_149_LEVEL       GPO_LOW
-#define GPO_150_LEVEL       GPO_LOW
-#define GPO_151_LEVEL       GPO_LOW
-#define GPO_152_LEVEL       GPO_LOW
-#define GPO_153_LEVEL       GPO_LOW
-#define GPO_154_LEVEL       GPO_LOW
-#define GPO_155_LEVEL       GPO_LOW
-#define GPO_156_LEVEL       GPO_LOW
-#define GPO_157_LEVEL       GPO_LOW
-#define GPO_158_LEVEL       GPO_LOW
-#define GPO_159_LEVEL       GPO_LOW
-#define GPO_160_LEVEL       GPO_LOW
-#define GPO_161_LEVEL       GPO_LOW
-#define GPO_162_LEVEL       GPO_LOW
-#define GPO_163_LEVEL       GPO_LOW
-#define GPO_164_LEVEL       GPO_LOW
-#define GPO_165_LEVEL       GPO_LOW
-#define GPO_166_LEVEL       GPO_LOW
-#define GPO_167_LEVEL       GPO_LOW
-#define GPO_168_LEVEL       GPO_LOW
-#define GPO_169_LEVEL       GPO_LOW
-#define GPO_170_LEVEL       GPO_HI
-#define GPO_171_LEVEL       GPO_LOW
-#define GPO_172_LEVEL       GPO_HI		// FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
-#define GPO_173_LEVEL       GPO_LOW
-#define GPO_174_LEVEL       GPO_LOW
-#define GPO_175_LEVEL       GPO_LOW
-#define GPO_176_LEVEL       GPO_LOW
-#define GPO_177_LEVEL       GPO_LOW
-#define GPO_178_LEVEL       GPO_HI      // AMD.SR BU to set VDDIO level to 1.5V for Barb BU
-#define GPO_179_LEVEL       GPO_HI
-#define GPO_180_LEVEL       GPO_HI
-#define GPO_181_LEVEL       GPO_LOW
-#define GPO_182_LEVEL       GPO_HI
-#define GPO_183_LEVEL       GPO_LOW
-#define GPO_184_LEVEL       GPO_LOW
-#define GPO_185_LEVEL       GPO_LOW
-#define GPO_186_LEVEL       GPO_LOW
-#define GPO_187_LEVEL       GPO_LOW
-#define GPO_188_LEVEL       GPO_LOW
-#define GPO_189_LEVEL       GPO_LOW
-#define GPO_190_LEVEL       GPO_LOW
-#define GPO_191_LEVEL       GPO_LOW
-#define GPO_192_LEVEL       GPO_LOW
-#define GPO_193_LEVEL       GPO_LOW
-#define GPO_194_LEVEL       GPO_LOW
-#define GPO_195_LEVEL       GPO_LOW
-#define GPO_196_LEVEL       GPO_LOW
-#define GPO_197_LEVEL       GPO_LOW
-#define GPO_198_LEVEL       GPO_LOW
-#define GPO_199_LEVEL       GPO_LOW
-#define GPO_200_LEVEL       GPO_HI
-#define GPO_201_LEVEL       GPO_LOW
-#define GPO_202_LEVEL       GPO_LOW
-#define GPO_203_LEVEL       GPO_LOW
-#define GPO_204_LEVEL       GPO_LOW
-#define GPO_205_LEVEL       GPO_LOW
-#define GPO_206_LEVEL       GPO_LOW
-#define GPO_207_LEVEL       GPO_LOW
-#define GPO_208_LEVEL       GPO_LOW
-#define GPO_209_LEVEL       GPO_LOW
-#define GPO_210_LEVEL       GPO_LOW
-#define GPO_211_LEVEL       GPO_LOW
-#define GPO_212_LEVEL       GPO_LOW
-#define GPO_213_LEVEL       GPO_LOW
-#define GPO_214_LEVEL       GPO_LOW
-#define GPO_215_LEVEL       GPO_LOW
-#define GPO_216_LEVEL       GPO_LOW
-#define GPO_217_LEVEL       GPO_LOW
-#define GPO_218_LEVEL       GPO_LOW
-#define GPO_219_LEVEL       GPO_LOW
-#define GPO_220_LEVEL       GPO_LOW
-#define GPO_221_LEVEL       GPO_LOW
-#define GPO_222_LEVEL       GPO_LOW
-#define GPO_223_LEVEL       GPO_LOW
-#define GPO_224_LEVEL       GPO_LOW
-#define GPO_225_LEVEL       GPO_LOW
-#define GPO_226_LEVEL       GPO_LOW
-#define GPO_227_LEVEL       GPO_LOW
-#define GPO_228_LEVEL       GPO_LOW
-#define GPO_229_LEVEL       GPO_LOW
-
-#define GPIO_NONSTICKY   (0 << 2)
-#define GPIO_STICKY      (1 << 2)
-
-#define GPIO_00_STICKY      GPIO_NONSTICKY
-#define GPIO_01_STICKY      GPIO_NONSTICKY
-#define GPIO_02_STICKY      GPIO_NONSTICKY
-#define GPIO_03_STICKY      GPIO_NONSTICKY
-#define GPIO_04_STICKY      GPIO_NONSTICKY
-#define GPIO_05_STICKY      GPIO_NONSTICKY
-#define GPIO_06_STICKY      GPIO_NONSTICKY
-#define GPIO_07_STICKY      GPIO_NONSTICKY
-#define GPIO_08_STICKY      GPIO_NONSTICKY
-#define GPIO_09_STICKY      GPIO_NONSTICKY
-#define GPIO_10_STICKY      GPIO_NONSTICKY
-#define GPIO_11_STICKY      GPIO_NONSTICKY
-#define GPIO_12_STICKY      GPIO_NONSTICKY
-#define GPIO_13_STICKY      GPIO_NONSTICKY
-#define GPIO_14_STICKY      GPIO_NONSTICKY
-#define GPIO_15_STICKY      GPIO_NONSTICKY
-#define GPIO_16_STICKY      GPIO_NONSTICKY
-#define GPIO_17_STICKY      GPIO_STICKY
-#define GPIO_18_STICKY      GPIO_NONSTICKY
-#define GPIO_19_STICKY      GPIO_NONSTICKY
-#define GPIO_20_STICKY      GPIO_NONSTICKY
-#define GPIO_21_STICKY      GPIO_NONSTICKY
-#define GPIO_22_STICKY      GPIO_NONSTICKY
-#define GPIO_23_STICKY      GPIO_NONSTICKY
-#define GPIO_24_STICKY      GPIO_NONSTICKY
-#define GPIO_25_STICKY      GPIO_NONSTICKY
-#define GPIO_26_STICKY      GPIO_NONSTICKY
-#define GPIO_27_STICKY      GPIO_NONSTICKY
-#define GPIO_28_STICKY      GPIO_NONSTICKY
-#define GPIO_29_STICKY      GPIO_NONSTICKY
-#define GPIO_30_STICKY      GPIO_NONSTICKY
-#define GPIO_31_STICKY      GPIO_NONSTICKY
-#define GPIO_32_STICKY      GPIO_NONSTICKY
-#define GPIO_33_STICKY      GPIO_NONSTICKY
-#define GPIO_34_STICKY      GPIO_NONSTICKY
-#define GPIO_35_STICKY      GPIO_NONSTICKY
-#define GPIO_36_STICKY      GPIO_NONSTICKY
-#define GPIO_37_STICKY      GPIO_NONSTICKY
-#define GPIO_38_STICKY      GPIO_NONSTICKY
-#define GPIO_39_STICKY      GPIO_NONSTICKY
-#define GPIO_40_STICKY      GPIO_NONSTICKY
-#define GPIO_41_STICKY      GPIO_NONSTICKY
-#define GPIO_42_STICKY      GPIO_NONSTICKY
-#define GPIO_43_STICKY      GPIO_NONSTICKY
-#define GPIO_44_STICKY      GPIO_NONSTICKY
-#define GPIO_45_STICKY      GPIO_NONSTICKY
-#define GPIO_46_STICKY      GPIO_NONSTICKY
-#define GPIO_47_STICKY      GPIO_NONSTICKY
-#define GPIO_48_STICKY      GPIO_NONSTICKY
-#define GPIO_49_STICKY      GPIO_NONSTICKY
-#define GPIO_50_STICKY      GPIO_NONSTICKY
-#define GPIO_51_STICKY      GPIO_NONSTICKY
-#define GPIO_52_STICKY      GPIO_NONSTICKY
-#define GPIO_53_STICKY      GPIO_NONSTICKY
-#define GPIO_54_STICKY      GPIO_NONSTICKY
-#define GPIO_55_STICKY      GPIO_NONSTICKY
-#define GPIO_56_STICKY      GPIO_NONSTICKY
-#define GPIO_57_STICKY      GPIO_NONSTICKY
-#define GPIO_58_STICKY      GPIO_NONSTICKY
-#define GPIO_59_STICKY      GPIO_NONSTICKY
-#define GPIO_60_STICKY      GPIO_NONSTICKY
-#define GPIO_61_STICKY      GPIO_NONSTICKY
-#define GPIO_62_STICKY      GPIO_NONSTICKY
-#define GPIO_63_STICKY      GPIO_NONSTICKY
-#define GPIO_64_STICKY      GPIO_NONSTICKY
-#define GPIO_65_STICKY      GPIO_NONSTICKY
-#define GPIO_66_STICKY      GPIO_NONSTICKY
-#define GPIO_67_STICKY      GPIO_NONSTICKY
-#define GPIO_68_STICKY      GPIO_NONSTICKY
-#define GPIO_69_STICKY      GPIO_NONSTICKY
-#define GPIO_70_STICKY      GPIO_NONSTICKY
-#define GPIO_71_STICKY      GPIO_NONSTICKY
-#define GPIO_72_STICKY      GPIO_NONSTICKY
-#define GPIO_73_STICKY      GPIO_NONSTICKY
-#define GPIO_74_STICKY      GPIO_NONSTICKY
-#define GPIO_75_STICKY      GPIO_NONSTICKY
-#define GPIO_76_STICKY      GPIO_NONSTICKY
-#define GPIO_77_STICKY      GPIO_NONSTICKY
-#define GPIO_78_STICKY      GPIO_NONSTICKY
-#define GPIO_79_STICKY      GPIO_NONSTICKY
-#define GPIO_80_STICKY      GPIO_NONSTICKY
-#define GPIO_81_STICKY      GPIO_NONSTICKY
-#define GPIO_82_STICKY      GPIO_NONSTICKY
-#define GPIO_83_STICKY      GPIO_NONSTICKY
-#define GPIO_84_STICKY      GPIO_NONSTICKY
-#define GPIO_85_STICKY      GPIO_NONSTICKY
-#define GPIO_86_STICKY      GPIO_NONSTICKY
-#define GPIO_87_STICKY      GPIO_NONSTICKY
-#define GPIO_88_STICKY      GPIO_NONSTICKY
-#define GPIO_89_STICKY      GPIO_NONSTICKY
-#define GPIO_90_STICKY      GPIO_NONSTICKY
-#define GPIO_91_STICKY      GPIO_NONSTICKY
-#define GPIO_92_STICKY      GPIO_NONSTICKY
-#define GPIO_93_STICKY      GPIO_NONSTICKY
-#define GPIO_94_STICKY      GPIO_NONSTICKY
-#define GPIO_95_STICKY      GPIO_NONSTICKY
-#define GPIO_96_STICKY      GPIO_NONSTICKY
-#define GPIO_97_STICKY      GPIO_NONSTICKY
-#define GPIO_98_STICKY      GPIO_NONSTICKY
-#define GPIO_99_STICKY      GPIO_NONSTICKY
-#define GPIO_100_STICKY     GPIO_NONSTICKY
-#define GPIO_101_STICKY     GPIO_NONSTICKY
-#define GPIO_102_STICKY     GPIO_STICKY
-#define GPIO_103_STICKY     GPIO_STICKY
-#define GPIO_104_STICKY     GPIO_NONSTICKY
-#define GPIO_105_STICKY     GPIO_NONSTICKY
-#define GPIO_106_STICKY     GPIO_NONSTICKY
-#define GPIO_107_STICKY     GPIO_NONSTICKY
-#define GPIO_108_STICKY     GPIO_STICKY
-#define GPIO_109_STICKY     GPIO_NONSTICKY
-#define GPIO_110_STICKY     GPIO_NONSTICKY
-#define GPIO_111_STICKY     GPIO_NONSTICKY
-#define GPIO_112_STICKY     GPIO_NONSTICKY
-#define GPIO_113_STICKY     GPIO_NONSTICKY
-#define GPIO_114_STICKY     GPIO_NONSTICKY
-#define GPIO_115_STICKY     GPIO_NONSTICKY
-#define GPIO_116_STICKY     GPIO_NONSTICKY
-#define GPIO_117_STICKY     GPIO_NONSTICKY
-#define GPIO_118_STICKY     GPIO_NONSTICKY
-#define GPIO_119_STICKY     GPIO_NONSTICKY
-#define GPIO_120_STICKY     GPIO_NONSTICKY
-#define GPIO_121_STICKY     GPIO_NONSTICKY
-#define GPIO_122_STICKY     GPIO_NONSTICKY
-#define GPIO_123_STICKY     GPIO_NONSTICKY
-#define GPIO_124_STICKY     GPIO_NONSTICKY
-#define GPIO_125_STICKY     GPIO_NONSTICKY
-#define GPIO_126_STICKY     GPIO_NONSTICKY
-#define GPIO_127_STICKY     GPIO_NONSTICKY
-#define GPIO_128_STICKY     GPIO_NONSTICKY
-#define GPIO_129_STICKY     GPIO_NONSTICKY
-#define GPIO_130_STICKY     GPIO_NONSTICKY
-#define GPIO_131_STICKY     GPIO_NONSTICKY
-#define GPIO_132_STICKY     GPIO_NONSTICKY
-#define GPIO_133_STICKY     GPIO_NONSTICKY
-#define GPIO_134_STICKY     GPIO_NONSTICKY
-#define GPIO_135_STICKY     GPIO_NONSTICKY
-#define GPIO_136_STICKY     GPIO_NONSTICKY
-#define GPIO_137_STICKY     GPIO_NONSTICKY
-#define GPIO_138_STICKY     GPIO_NONSTICKY
-#define GPIO_139_STICKY     GPIO_NONSTICKY
-#define GPIO_140_STICKY     GPIO_NONSTICKY
-#define GPIO_141_STICKY     GPIO_NONSTICKY
-#define GPIO_142_STICKY     GPIO_NONSTICKY
-#define GPIO_143_STICKY     GPIO_NONSTICKY
-#define GPIO_144_STICKY     GPIO_NONSTICKY
-#define GPIO_145_STICKY     GPIO_NONSTICKY
-#define GPIO_146_STICKY     GPIO_NONSTICKY
-#define GPIO_147_STICKY     GPIO_NONSTICKY
-#define GPIO_148_STICKY     GPIO_NONSTICKY
-#define GPIO_149_STICKY     GPIO_NONSTICKY
-#define GPIO_150_STICKY     GPIO_NONSTICKY
-#define GPIO_151_STICKY     GPIO_NONSTICKY
-#define GPIO_152_STICKY     GPIO_NONSTICKY
-#define GPIO_153_STICKY     GPIO_NONSTICKY
-#define GPIO_154_STICKY     GPIO_NONSTICKY
-#define GPIO_155_STICKY     GPIO_NONSTICKY
-#define GPIO_156_STICKY     GPIO_NONSTICKY
-#define GPIO_157_STICKY     GPIO_NONSTICKY
-#define GPIO_158_STICKY     GPIO_NONSTICKY
-#define GPIO_159_STICKY     GPIO_NONSTICKY
-#define GPIO_160_STICKY     GPIO_NONSTICKY
-#define GPIO_161_STICKY     GPIO_NONSTICKY
-#define GPIO_162_STICKY     GPIO_NONSTICKY
-#define GPIO_163_STICKY     GPIO_NONSTICKY
-#define GPIO_164_STICKY     GPIO_NONSTICKY
-#define GPIO_165_STICKY     GPIO_NONSTICKY
-#define GPIO_166_STICKY     GPIO_NONSTICKY
-#define GPIO_167_STICKY     GPIO_NONSTICKY
-#define GPIO_168_STICKY     GPIO_NONSTICKY
-#define GPIO_169_STICKY     GPIO_NONSTICKY
-#define GPIO_170_STICKY     GPIO_STICKY
-#define GPIO_171_STICKY     GPIO_NONSTICKY
-#define GPIO_172_STICKY     GPIO_STICKY
-#define GPIO_173_STICKY     GPIO_NONSTICKY
-#define GPIO_174_STICKY     GPIO_NONSTICKY
-#define GPIO_175_STICKY     GPIO_NONSTICKY
-#define GPIO_176_STICKY     GPIO_NONSTICKY
-#define GPIO_177_STICKY     GPIO_NONSTICKY
-#define GPIO_178_STICKY     GPIO_NONSTICKY
-#define GPIO_179_STICKY     GPIO_NONSTICKY
-#define GPIO_180_STICKY     GPIO_NONSTICKY
-#define GPIO_181_STICKY     GPIO_NONSTICKY
-#define GPIO_182_STICKY     GPIO_NONSTICKY
-#define GPIO_183_STICKY     GPIO_NONSTICKY
-#define GPIO_184_STICKY     GPIO_NONSTICKY
-#define GPIO_185_STICKY     GPIO_NONSTICKY
-#define GPIO_186_STICKY     GPIO_NONSTICKY
-#define GPIO_187_STICKY     GPIO_NONSTICKY
-#define GPIO_188_STICKY     GPIO_NONSTICKY
-#define GPIO_189_STICKY     GPIO_NONSTICKY
-#define GPIO_190_STICKY     GPIO_NONSTICKY
-#define GPIO_191_STICKY     GPIO_NONSTICKY
-#define GPIO_192_STICKY     GPIO_NONSTICKY
-#define GPIO_193_STICKY     GPIO_NONSTICKY
-#define GPIO_194_STICKY     GPIO_NONSTICKY
-#define GPIO_195_STICKY     GPIO_NONSTICKY
-#define GPIO_196_STICKY     GPIO_NONSTICKY
-#define GPIO_197_STICKY     GPIO_NONSTICKY
-#define GPIO_198_STICKY     GPIO_NONSTICKY
-#define GPIO_199_STICKY     GPIO_NONSTICKY
-#define GPIO_200_STICKY     GPIO_NONSTICKY
-#define GPIO_201_STICKY     GPIO_NONSTICKY
-#define GPIO_202_STICKY     GPIO_NONSTICKY
-#define GPIO_203_STICKY     GPIO_NONSTICKY
-#define GPIO_204_STICKY     GPIO_NONSTICKY
-#define GPIO_205_STICKY     GPIO_NONSTICKY
-#define GPIO_206_STICKY     GPIO_NONSTICKY
-#define GPIO_207_STICKY     GPIO_NONSTICKY
-#define GPIO_208_STICKY     GPIO_NONSTICKY
-#define GPIO_209_STICKY     GPIO_NONSTICKY
-#define GPIO_210_STICKY     GPIO_NONSTICKY
-#define GPIO_211_STICKY     GPIO_NONSTICKY
-#define GPIO_212_STICKY     GPIO_NONSTICKY
-#define GPIO_213_STICKY     GPIO_NONSTICKY
-#define GPIO_214_STICKY     GPIO_NONSTICKY
-#define GPIO_215_STICKY     GPIO_NONSTICKY
-#define GPIO_216_STICKY     GPIO_NONSTICKY
-#define GPIO_217_STICKY     GPIO_NONSTICKY
-#define GPIO_218_STICKY     GPIO_NONSTICKY
-#define GPIO_219_STICKY     GPIO_NONSTICKY
-#define GPIO_220_STICKY     GPIO_NONSTICKY
-#define GPIO_221_STICKY     GPIO_NONSTICKY
-#define GPIO_222_STICKY     GPIO_NONSTICKY
-#define GPIO_223_STICKY     GPIO_NONSTICKY
-#define GPIO_224_STICKY     GPIO_NONSTICKY
-#define GPIO_225_STICKY     GPIO_NONSTICKY
-#define GPIO_226_STICKY     GPIO_NONSTICKY
-#define GPIO_227_STICKY     GPIO_NONSTICKY
-#define GPIO_228_STICKY     GPIO_NONSTICKY
-#define GPIO_229_STICKY     GPIO_NONSTICKY
-
-#define PULLUP_ENABLE      (0 << 3)
-#define PULLUP_DISABLE     (1 << 3)
-
-#define GPIO_00_PULLUP      PULLUP_DISABLE
-#define GPIO_01_PULLUP      PULLUP_DISABLE
-#define GPIO_02_PULLUP      PULLUP_DISABLE
-#define GPIO_03_PULLUP      PULLUP_DISABLE
-#define GPIO_04_PULLUP      PULLUP_DISABLE
-#define GPIO_05_PULLUP      PULLUP_DISABLE
-#define GPIO_06_PULLUP      PULLUP_DISABLE
-#define GPIO_07_PULLUP      PULLUP_DISABLE
-#define GPIO_08_PULLUP      PULLUP_DISABLE
-#define GPIO_09_PULLUP      PULLUP_DISABLE
-#define GPIO_10_PULLUP      PULLUP_DISABLE
-#define GPIO_11_PULLUP      PULLUP_DISABLE
-#define GPIO_12_PULLUP      PULLUP_DISABLE
-#define GPIO_13_PULLUP      PULLUP_DISABLE
-#define GPIO_14_PULLUP      PULLUP_DISABLE
-#define GPIO_15_PULLUP      PULLUP_DISABLE
-#define GPIO_16_PULLUP      PULLUP_DISABLE
-#define GPIO_17_PULLUP      PULLUP_DISABLE
-#define GPIO_18_PULLUP      PULLUP_DISABLE
-#define GPIO_19_PULLUP      PULLUP_DISABLE
-#define GPIO_20_PULLUP      PULLUP_DISABLE
-#define GPIO_21_PULLUP      PULLUP_DISABLE
-#define GPIO_22_PULLUP      PULLUP_DISABLE
-#define GPIO_23_PULLUP      PULLUP_DISABLE
-#define GPIO_24_PULLUP      PULLUP_DISABLE
-#define GPIO_25_PULLUP      PULLUP_DISABLE
-#define GPIO_26_PULLUP      PULLUP_DISABLE
-#define GPIO_27_PULLUP      PULLUP_DISABLE
-#define GPIO_28_PULLUP      PULLUP_DISABLE
-#define GPIO_29_PULLUP      PULLUP_DISABLE
-#define GPIO_30_PULLUP      PULLUP_DISABLE
-#define GPIO_31_PULLUP      PULLUP_DISABLE
-#define GPIO_32_PULLUP      PULLUP_DISABLE
-#define GPIO_33_PULLUP      PULLUP_DISABLE
-#define GPIO_34_PULLUP      PULLUP_DISABLE
-#define GPIO_35_PULLUP      PULLUP_DISABLE
-#define GPIO_36_PULLUP      PULLUP_DISABLE
-#define GPIO_37_PULLUP      PULLUP_DISABLE
-#define GPIO_38_PULLUP      PULLUP_DISABLE
-#define GPIO_39_PULLUP      PULLUP_DISABLE
-#define GPIO_40_PULLUP      PULLUP_DISABLE
-#define GPIO_41_PULLUP      PULLUP_DISABLE
-#define GPIO_42_PULLUP      PULLUP_DISABLE
-#define GPIO_43_PULLUP      PULLUP_DISABLE
-#define GPIO_44_PULLUP      PULLUP_DISABLE
-#define GPIO_45_PULLUP      PULLUP_DISABLE
-#define GPIO_46_PULLUP      PULLUP_DISABLE
-#define GPIO_47_PULLUP      PULLUP_DISABLE
-#define GPIO_48_PULLUP      PULLUP_DISABLE
-#define GPIO_49_PULLUP      PULLUP_DISABLE
-#define GPIO_50_PULLUP      PULLUP_DISABLE
-#define GPIO_51_PULLUP      PULLUP_DISABLE
-#define GPIO_52_PULLUP      PULLUP_DISABLE
-#define GPIO_53_PULLUP      PULLUP_DISABLE
-#define GPIO_54_PULLUP      PULLUP_DISABLE
-#define GPIO_55_PULLUP      PULLUP_DISABLE
-#define GPIO_56_PULLUP      PULLUP_DISABLE
-#define GPIO_57_PULLUP      PULLUP_DISABLE
-#define GPIO_58_PULLUP      PULLUP_DISABLE
-#define GPIO_59_PULLUP      PULLUP_DISABLE
-#define GPIO_60_PULLUP      PULLUP_DISABLE
-#define GPIO_61_PULLUP      PULLUP_DISABLE
-#define GPIO_62_PULLUP      PULLUP_DISABLE
-#define GPIO_63_PULLUP      PULLUP_DISABLE
-#define GPIO_64_PULLUP      PULLUP_DISABLE
-#define GPIO_65_PULLUP      PULLUP_DISABLE
-#define GPIO_66_PULLUP      PULLUP_DISABLE
-#define GPIO_67_PULLUP      PULLUP_DISABLE
-#define GPIO_68_PULLUP      PULLUP_DISABLE
-#define GPIO_69_PULLUP      PULLUP_DISABLE
-#define GPIO_70_PULLUP      PULLUP_DISABLE
-#define GPIO_71_PULLUP      PULLUP_DISABLE
-#define GPIO_72_PULLUP      PULLUP_DISABLE
-#define GPIO_73_PULLUP      PULLUP_DISABLE
-#define GPIO_74_PULLUP      PULLUP_DISABLE
-#define GPIO_75_PULLUP      PULLUP_DISABLE
-#define GPIO_76_PULLUP      PULLUP_DISABLE
-#define GPIO_77_PULLUP      PULLUP_DISABLE
-#define GPIO_78_PULLUP      PULLUP_DISABLE
-#define GPIO_79_PULLUP      PULLUP_DISABLE
-#define GPIO_80_PULLUP      PULLUP_DISABLE
-#define GPIO_80_PULLUP      PULLUP_DISABLE
-#define GPIO_81_PULLUP      PULLUP_DISABLE
-#define GPIO_82_PULLUP      PULLUP_DISABLE
-#define GPIO_83_PULLUP      PULLUP_DISABLE
-#define GPIO_84_PULLUP      PULLUP_DISABLE
-#define GPIO_85_PULLUP      PULLUP_DISABLE
-#define GPIO_86_PULLUP      PULLUP_DISABLE
-#define GPIO_87_PULLUP      PULLUP_DISABLE
-#define GPIO_88_PULLUP      PULLUP_DISABLE
-#define GPIO_89_PULLUP      PULLUP_DISABLE
-#define GPIO_90_PULLUP      PULLUP_DISABLE
-#define GPIO_91_PULLUP      PULLUP_DISABLE
-#define GPIO_92_PULLUP      PULLUP_DISABLE
-#define GPIO_93_PULLUP      PULLUP_DISABLE
-#define GPIO_94_PULLUP      PULLUP_DISABLE
-#define GPIO_95_PULLUP      PULLUP_DISABLE
-#define GPIO_96_PULLUP      PULLUP_DISABLE
-#define GPIO_97_PULLUP      PULLUP_DISABLE
-#define GPIO_98_PULLUP      PULLUP_DISABLE
-#define GPIO_99_PULLUP      PULLUP_DISABLE
-#define GPIO_100_PULLUP     PULLUP_DISABLE
-#define GPIO_101_PULLUP     PULLUP_DISABLE
-#define GPIO_102_PULLUP     PULLUP_DISABLE
-#define GPIO_103_PULLUP     PULLUP_DISABLE
-#define GPIO_104_PULLUP     PULLUP_DISABLE
-#define GPIO_105_PULLUP     PULLUP_DISABLE
-#define GPIO_106_PULLUP     PULLUP_DISABLE
-#define GPIO_107_PULLUP     PULLUP_DISABLE
-#define GPIO_108_PULLUP     PULLUP_DISABLE
-#define GPIO_109_PULLUP     PULLUP_DISABLE
-#define GPIO_110_PULLUP     PULLUP_DISABLE
-#define GPIO_111_PULLUP     PULLUP_DISABLE
-#define GPIO_112_PULLUP     PULLUP_DISABLE
-#define GPIO_113_PULLUP     PULLUP_DISABLE
-#define GPIO_114_PULLUP     PULLUP_DISABLE
-#define GPIO_115_PULLUP     PULLUP_DISABLE
-#define GPIO_116_PULLUP     PULLUP_DISABLE
-#define GPIO_117_PULLUP     PULLUP_DISABLE
-#define GPIO_118_PULLUP     PULLUP_ENABLE
-#define GPIO_119_PULLUP     PULLUP_DISABLE
-#define GPIO_120_PULLUP     PULLUP_DISABLE
-#define GPIO_121_PULLUP     PULLUP_DISABLE
-#define GPIO_122_PULLUP     PULLUP_DISABLE
-#define GPIO_123_PULLUP     PULLUP_DISABLE
-#define GPIO_124_PULLUP     PULLUP_DISABLE
-#define GPIO_125_PULLUP     PULLUP_DISABLE
-#define GPIO_126_PULLUP     PULLUP_DISABLE
-#define GPIO_127_PULLUP     PULLUP_DISABLE
-#define GPIO_128_PULLUP     PULLUP_DISABLE
-#define GPIO_129_PULLUP     PULLUP_DISABLE
-#define GPIO_130_PULLUP     PULLUP_DISABLE
-#define GPIO_131_PULLUP     PULLUP_DISABLE
-#define GPIO_132_PULLUP     PULLUP_DISABLE
-#define GPIO_133_PULLUP     PULLUP_DISABLE
-#define GPIO_134_PULLUP     PULLUP_DISABLE
-#define GPIO_135_PULLUP     PULLUP_DISABLE
-#define GPIO_136_PULLUP     PULLUP_DISABLE
-#define GPIO_137_PULLUP     PULLUP_DISABLE
-#define GPIO_138_PULLUP     PULLUP_DISABLE
-#define GPIO_139_PULLUP     PULLUP_DISABLE
-#define GPIO_140_PULLUP     PULLUP_DISABLE
-#define GPIO_141_PULLUP     PULLUP_DISABLE
-#define GPIO_142_PULLUP     PULLUP_DISABLE
-#define GPIO_143_PULLUP     PULLUP_DISABLE
-#define GPIO_144_PULLUP     PULLUP_DISABLE
-#define GPIO_145_PULLUP     PULLUP_DISABLE
-#define GPIO_146_PULLUP     PULLUP_DISABLE
-#define GPIO_147_PULLUP     PULLUP_DISABLE
-#define GPIO_148_PULLUP     PULLUP_DISABLE
-#define GPIO_149_PULLUP     PULLUP_DISABLE
-#define GPIO_150_PULLUP     PULLUP_DISABLE
-#define GPIO_151_PULLUP     PULLUP_DISABLE
-#define GPIO_152_PULLUP     PULLUP_DISABLE
-#define GPIO_153_PULLUP     PULLUP_DISABLE
-#define GPIO_154_PULLUP     PULLUP_DISABLE
-#define GPIO_155_PULLUP     PULLUP_DISABLE
-#define GPIO_156_PULLUP     PULLUP_DISABLE
-#define GPIO_157_PULLUP     PULLUP_DISABLE
-#define GPIO_158_PULLUP     PULLUP_DISABLE
-#define GPIO_159_PULLUP     PULLUP_DISABLE
-#define GPIO_160_PULLUP     PULLUP_DISABLE
-#define GPIO_161_PULLUP     PULLUP_DISABLE
-#define GPIO_162_PULLUP     PULLUP_DISABLE
-#define GPIO_163_PULLUP     PULLUP_DISABLE
-#define GPIO_164_PULLUP     PULLUP_DISABLE
-#define GPIO_165_PULLUP     PULLUP_DISABLE
-#define GPIO_166_PULLUP     PULLUP_DISABLE
-#define GPIO_167_PULLUP     PULLUP_DISABLE
-#define GPIO_168_PULLUP     PULLUP_DISABLE
-#define GPIO_169_PULLUP     PULLUP_DISABLE
-#define GPIO_170_PULLUP     PULLUP_DISABLE
-#define GPIO_171_PULLUP     PULLUP_DISABLE
-#define GPIO_172_PULLUP     PULLUP_DISABLE
-#define GPIO_173_PULLUP     PULLUP_DISABLE
-#define GPIO_174_PULLUP     PULLUP_DISABLE
-#define GPIO_175_PULLUP     PULLUP_DISABLE
-#define GPIO_176_PULLUP     PULLUP_DISABLE
-#define GPIO_177_PULLUP     PULLUP_DISABLE
-#define GPIO_178_PULLUP     PULLUP_DISABLE
-#define GPIO_179_PULLUP     PULLUP_DISABLE
-#define GPIO_180_PULLUP     PULLUP_DISABLE
-#define GPIO_180_PULLUP     PULLUP_DISABLE
-#define GPIO_181_PULLUP     PULLUP_DISABLE
-#define GPIO_182_PULLUP     PULLUP_DISABLE
-#define GPIO_183_PULLUP     PULLUP_DISABLE
-#define GPIO_184_PULLUP     PULLUP_DISABLE
-#define GPIO_185_PULLUP     PULLUP_DISABLE
-#define GPIO_186_PULLUP     PULLUP_DISABLE
-#define GPIO_187_PULLUP     PULLUP_DISABLE
-#define GPIO_188_PULLUP     PULLUP_DISABLE
-#define GPIO_189_PULLUP     PULLUP_DISABLE
-#define GPIO_190_PULLUP     PULLUP_DISABLE
-#define GPIO_191_PULLUP     PULLUP_DISABLE
-#define GPIO_192_PULLUP     PULLUP_DISABLE
-#define GPIO_193_PULLUP     PULLUP_DISABLE
-#define GPIO_194_PULLUP     PULLUP_DISABLE
-#define GPIO_195_PULLUP     PULLUP_DISABLE
-#define GPIO_196_PULLUP     PULLUP_DISABLE
-#define GPIO_197_PULLUP     PULLUP_DISABLE
-#define GPIO_198_PULLUP     PULLUP_DISABLE
-#define GPIO_199_PULLUP     PULLUP_DISABLE
-#define GPIO_200_PULLUP     PULLUP_DISABLE
-#define GPIO_201_PULLUP     PULLUP_DISABLE
-#define GPIO_202_PULLUP     PULLUP_DISABLE
-#define GPIO_203_PULLUP     PULLUP_DISABLE
-#define GPIO_204_PULLUP     PULLUP_DISABLE
-#define GPIO_205_PULLUP     PULLUP_DISABLE
-#define GPIO_206_PULLUP     PULLUP_DISABLE
-#define GPIO_207_PULLUP     PULLUP_DISABLE
-#define GPIO_208_PULLUP     PULLUP_DISABLE
-#define GPIO_209_PULLUP     PULLUP_DISABLE
-#define GPIO_210_PULLUP     PULLUP_DISABLE
-#define GPIO_211_PULLUP     PULLUP_DISABLE
-#define GPIO_212_PULLUP     PULLUP_DISABLE
-#define GPIO_213_PULLUP     PULLUP_DISABLE
-#define GPIO_214_PULLUP     PULLUP_DISABLE
-#define GPIO_215_PULLUP     PULLUP_DISABLE
-#define GPIO_216_PULLUP     PULLUP_DISABLE
-#define GPIO_217_PULLUP     PULLUP_DISABLE
-#define GPIO_218_PULLUP     PULLUP_DISABLE
-#define GPIO_219_PULLUP     PULLUP_DISABLE
-#define GPIO_220_PULLUP     PULLUP_DISABLE
-#define GPIO_221_PULLUP     PULLUP_DISABLE
-#define GPIO_222_PULLUP     PULLUP_DISABLE
-#define GPIO_223_PULLUP     PULLUP_DISABLE
-#define GPIO_224_PULLUP     PULLUP_DISABLE
-#define GPIO_225_PULLUP     PULLUP_DISABLE
-#define GPIO_226_PULLUP     PULLUP_DISABLE
-#define GPIO_227_PULLUP     PULLUP_DISABLE
-#define GPIO_228_PULLUP     PULLUP_DISABLE
-#define GPIO_229_PULLUP     PULLUP_DISABLE
-
-#define PULLDOWN_ENABLE       (1 << 4)
-#define PULLDOWN_DISABLE      (0 << 4)
-
-#define GPIO_00_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_01_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_02_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_03_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_04_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_05_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_06_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_07_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_08_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_09_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_10_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_11_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_12_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_13_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_14_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_15_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_16_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_17_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_18_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_19_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_20_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_21_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_22_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_23_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_24_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_25_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_26_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_27_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_28_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_29_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_30_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_31_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_32_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_33_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_34_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_35_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_36_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_37_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_38_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_39_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_40_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_41_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_42_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_43_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_44_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_45_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_46_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_47_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_48_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_49_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_50_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_51_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_52_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_53_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_54_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_55_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_56_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_57_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_58_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_59_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_60_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_61_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_62_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_63_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_64_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_65_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_66_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_67_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_68_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_69_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_70_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_71_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_72_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_73_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_74_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_75_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_76_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_77_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_78_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_79_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_80_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_80_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_81_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_82_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_83_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_84_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_85_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_86_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_87_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_88_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_89_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_90_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_91_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_92_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_93_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_94_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_95_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_96_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_97_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_98_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_99_PULLDOWN    PULLDOWN_DISABLE
-#define GPIO_100_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_101_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_102_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_103_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_104_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_105_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_106_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_107_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_108_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_109_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_110_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_111_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_112_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_113_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_114_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_115_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_116_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_117_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_118_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_119_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_120_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_121_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_122_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_123_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_124_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_125_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_126_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_127_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_128_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_129_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_130_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_131_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_132_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_133_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_134_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_135_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_136_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_137_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_138_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_139_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_140_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_141_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_142_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_143_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_144_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_145_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_146_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_147_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_148_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_149_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_150_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_151_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_152_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_153_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_154_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_155_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_156_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_157_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_158_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_159_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_160_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_161_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_162_PULLDOWN   PULLDOWN_ENABLE
-#define GPIO_163_PULLDOWN   PULLDOWN_ENABLE
-#define GPIO_164_PULLDOWN   PULLDOWN_ENABLE
-#define GPIO_165_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_166_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_167_PULLDOWN   PULLDOWN_ENABLE
-#define GPIO_168_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_169_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_170_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_171_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_172_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_173_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_174_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_175_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_176_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_177_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_178_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_179_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_180_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_180_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_181_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_182_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_183_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_184_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_185_PULLDOWN   PULLDOWN_ENABLE
-#define GPIO_186_PULLDOWN   PULLDOWN_ENABLE
-#define GPIO_187_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_188_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_189_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_190_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_191_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_192_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_193_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_194_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_195_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_196_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_197_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_198_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_199_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_200_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_201_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_202_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_203_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_204_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_205_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_206_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_207_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_208_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_209_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_210_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_211_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_212_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_213_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_214_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_215_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_216_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_217_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_218_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_219_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_220_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_221_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_222_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_223_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_224_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_225_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_226_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_227_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_228_PULLDOWN   PULLDOWN_DISABLE
-#define GPIO_229_PULLDOWN   PULLDOWN_DISABLE
-
-#define EVENT_DISABLE           0
-#define EVENT_ENABLE            1
-
-#define GEVENT_00_EVENTENABLE   EVENT_DISABLE
-#define GEVENT_01_EVENTENABLE   EVENT_DISABLE
-#define GEVENT_02_EVENTENABLE   EVENT_ENABLE	// APU THERMTRIP#
-#define GEVENT_03_EVENTENABLE   EVENT_ENABLE    // EC_SCI#
-#define GEVENT_04_EVENTENABLE   EVENT_ENABLE    // APU_MEMHOT#
-#define GEVENT_05_EVENTENABLE   EVENT_ENABLE    // PCIE_EXPCARD_PWREN#
-#define GEVENT_06_EVENTENABLE   EVENT_DISABLE
-#define GEVENT_07_EVENTENABLE   EVENT_DISABLE
-#define GEVENT_08_EVENTENABLE   EVENT_DISABLE
-#define GEVENT_09_EVENTENABLE   EVENT_ENABLE    // WF_RADIO
-#define GEVENT_10_EVENTENABLE   EVENT_DISABLE
-#define GEVENT_11_EVENTENABLE   EVENT_DISABLE
-#define GEVENT_12_EVENTENABLE   EVENT_ENABLE    // SMBALERT#
-#define GEVENT_13_EVENTENABLE   EVENT_DISABLE
-#define GEVENT_14_EVENTENABLE   EVENT_ENABLE    // LASSO_DET#/DOCK#
-#define GEVENT_15_EVENTENABLE   EVENT_ENABLE    // ODD_PLUGIN#
-#define GEVENT_16_EVENTENABLE   EVENT_ENABLE    // ODD_DA
-#define GEVENT_17_EVENTENABLE   EVENT_ENABLE    // TWARN
-#define GEVENT_18_EVENTENABLE   EVENT_DISABLE
-#define GEVENT_19_EVENTENABLE   EVENT_DISABLE
-#define GEVENT_20_EVENTENABLE   EVENT_DISABLE
-#define GEVENT_21_EVENTENABLE   EVENT_DISABLE
-#define GEVENT_22_EVENTENABLE   EVENT_ENABLE    // LID_CLOSE#
-#define GEVENT_23_EVENTENABLE   EVENT_DISABLE   // EC_SMI#
-
-#define SCITRIG_LOW             0
-#define SCITRIG_HI              1
-
-#define GEVENT_00_SCITRIG       SCITRIG_LOW
-#define GEVENT_01_SCITRIG       SCITRIG_LOW
-#define GEVENT_02_SCITRIG       SCITRIG_LOW
-#define GEVENT_03_SCITRIG       SCITRIG_LOW
-#define GEVENT_04_SCITRIG       SCITRIG_LOW
-#define GEVENT_05_SCITRIG       SCITRIG_LOW
-#define GEVENT_06_SCITRIG       SCITRIG_LOW
-#define GEVENT_07_SCITRIG       SCITRIG_LOW
-#define GEVENT_08_SCITRIG       SCITRIG_LOW
-#define GEVENT_09_SCITRIG       SCITRIG_LOW
-#define GEVENT_10_SCITRIG       SCITRIG_LOW
-#define GEVENT_11_SCITRIG       SCITRIG_LOW
-#define GEVENT_12_SCITRIG       SCITRIG_LOW
-#define GEVENT_13_SCITRIG       SCITRIG_LOW
-#define GEVENT_14_SCITRIG       SCITRIG_LOW
-#define GEVENT_15_SCITRIG       SCITRIG_LOW
-#define GEVENT_16_SCITRIG       SCITRIG_LOW
-#define GEVENT_17_SCITRIG       SCITRIG_HI
-#define GEVENT_18_SCITRIG       SCITRIG_LOW
-#define GEVENT_19_SCITRIG       SCITRIG_LOW
-#define GEVENT_20_SCITRIG       SCITRIG_LOW
-#define GEVENT_21_SCITRIG       SCITRIG_LOW
-#define GEVENT_22_SCITRIG       SCITRIG_LOW
-#define GEVENT_23_SCITRIG       SCITRIG_LOW
-
-#define SCILEVEL_EDGE           0
-#define SCILEVEL_LEVEL          1
-
-#define GEVENT_00_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_01_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_02_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_03_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_04_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_05_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_06_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_07_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_08_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_09_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_10_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_11_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_12_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_13_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_14_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_15_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_16_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_17_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_18_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_19_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_20_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_21_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_22_SCILEVEL      SCILEVEL_EDGE
-#define GEVENT_23_SCILEVEL      SCILEVEL_EDGE
-
-#define SMISCI_DISABLE          0
-#define SMISCI_ENABLE           1
-
-#define GEVENT_00_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_01_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_02_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_03_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_04_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_05_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_06_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_07_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_08_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_09_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_10_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_11_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_12_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_13_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_14_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_15_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_16_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_17_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_18_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_19_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_20_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_21_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_22_SMISCIEN      SMISCI_DISABLE
-#define GEVENT_23_SMISCIEN      SMISCI_DISABLE
-
-#define SCIS0_DISABLE           0
-#define SCIS0_ENABLE            1
-
-#define GEVENT_00_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_01_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_02_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_03_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_04_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_05_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_06_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_07_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_08_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_09_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_10_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_11_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_12_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_13_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_14_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_15_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_16_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_17_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_18_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_19_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_20_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_21_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_22_SCIS0EN       SCIS0_DISABLE
-#define GEVENT_23_SCIS0EN       SCIS0_DISABLE
-
-#define GEVENT_SCIMASK          0x1F
-#define GEVENT_00_SCIMAP        0
-#define GEVENT_01_SCIMAP        1
-#define GEVENT_02_SCIMAP        2
-#define GEVENT_03_SCIMAP        3
-#define GEVENT_04_SCIMAP        4
-#define GEVENT_05_SCIMAP        5
-#define GEVENT_06_SCIMAP        6
-#define GEVENT_07_SCIMAP        7
-#define GEVENT_08_SCIMAP        8
-#define GEVENT_09_SCIMAP        9
-#define GEVENT_10_SCIMAP        10
-#define GEVENT_11_SCIMAP        11
-#define GEVENT_12_SCIMAP        12
-#define GEVENT_13_SCIMAP        13
-#define GEVENT_14_SCIMAP        14
-#define GEVENT_15_SCIMAP        15
-#define GEVENT_16_SCIMAP        16
-#define GEVENT_17_SCIMAP        17
-#define GEVENT_18_SCIMAP        18
-#define GEVENT_19_SCIMAP        19
-#define GEVENT_20_SCIMAP        20
-#define GEVENT_21_SCIMAP        21
-#define GEVENT_22_SCIMAP        22
-#define GEVENT_23_SCIMAP        23
-
-#define SMITRIG_LOW             0
-#define SMITRIG_HI              1
-
-#define GEVENT_00_SMITRIG       SMITRIG_HI
-#define GEVENT_01_SMITRIG       SMITRIG_HI
-#define GEVENT_02_SMITRIG       SMITRIG_HI
-#define GEVENT_03_SMITRIG       SMITRIG_HI
-#define GEVENT_04_SMITRIG       SMITRIG_HI
-#define GEVENT_05_SMITRIG       SMITRIG_HI
-#define GEVENT_06_SMITRIG       SMITRIG_HI
-#define GEVENT_07_SMITRIG       SMITRIG_HI
-#define GEVENT_08_SMITRIG       SMITRIG_HI
-#define GEVENT_09_SMITRIG       SMITRIG_HI
-#define GEVENT_10_SMITRIG       SMITRIG_HI
-#define GEVENT_11_SMITRIG       SMITRIG_HI
-#define GEVENT_12_SMITRIG       SMITRIG_HI
-#define GEVENT_13_SMITRIG       SMITRIG_HI
-#define GEVENT_14_SMITRIG       SMITRIG_HI
-#define GEVENT_15_SMITRIG       SMITRIG_HI
-#define GEVENT_16_SMITRIG       SMITRIG_HI
-#define GEVENT_17_SMITRIG       SMITRIG_HI
-#define GEVENT_18_SMITRIG       SMITRIG_HI
-#define GEVENT_19_SMITRIG       SMITRIG_HI
-#define GEVENT_20_SMITRIG       SMITRIG_HI
-#define GEVENT_21_SMITRIG       SMITRIG_HI
-#define GEVENT_22_SMITRIG       SMITRIG_HI
-#define GEVENT_23_SMITRIG       SMITRIG_HI
-
-#define SMICONTROL_MASK         3
-#define SMICONTROL_DISABLE      0
-#define SMICONTROL_SMI          1
-#define SMICONTROL_NMI          2
-#define SMICONTROL_IRQ13        3
-
-#define GEVENT_00_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_01_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_02_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_03_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_04_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_05_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_06_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_07_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_08_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_09_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_10_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_11_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_12_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_13_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_14_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_15_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_16_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_17_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_18_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_19_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_20_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_21_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_22_SMICONTROL    SMICONTROL_DISABLE
-#define GEVENT_23_SMICONTROL    SMICONTROL_DISABLE
-
-#define GPIO_RSVD_ZONE0_S   GPIO_81
-#define GPIO_RSVD_ZONE0_E   GPIO_95
-#define GPIO_RSVD_ZONE1_S   GPIO_120
-#define GPIO_RSVD_ZONE1_E   GPIO_127
-
-typedef enum _GPIO_COUNT
-{
-	GPIO_00 = 0,
-	GPIO_01,
-	GPIO_02,
-	GPIO_03,
-	GPIO_04,
-	GPIO_05,
-	GPIO_06,
-	GPIO_07,
-	GPIO_08,
-	GPIO_09,
-	GPIO_10,
-	GPIO_11,
-	GPIO_12,
-	GPIO_13,
-	GPIO_14,
-	GPIO_15,
-	GPIO_16,
-	GPIO_17,
-	GPIO_18,
-	GPIO_19,
-	GPIO_20,
-	GPIO_21,
-	GPIO_22,
-	GPIO_23,
-	GPIO_24,
-	GPIO_25,
-	GPIO_26,
-	GPIO_27,
-	GPIO_28,
-	GPIO_29,
-	GPIO_30,
-	GPIO_31,
-	GPIO_32,
-	GPIO_33,
-	GPIO_34,
-	GPIO_35,
-	GPIO_36,
-	GPIO_37,
-	GPIO_38,
-	GPIO_39,
-	GPIO_40,
-	GPIO_41,
-	GPIO_42,
-	GPIO_43,
-	GPIO_44,
-	GPIO_45,
-	GPIO_46,
-	GPIO_47,
-	GPIO_48,
-	GPIO_49,
-	GPIO_50,
-	GPIO_51,
-	GPIO_52,
-	GPIO_53,
-	GPIO_54,
-	GPIO_55,
-	GPIO_56,
-	GPIO_57,
-	GPIO_58,
-	GPIO_59,
-	GPIO_60,
-	GPIO_61,
-	GPIO_62,
-	GPIO_63,
-	GPIO_64,
-	GPIO_65,
-	GPIO_66,
-	GPIO_67,
-	GPIO_68,
-	GPIO_69,
-	GPIO_70,
-	GPIO_71,
-	GPIO_72,
-	GPIO_73,
-	GPIO_74,
-	GPIO_75,
-	GPIO_76,
-	GPIO_77,
-	GPIO_78,
-	GPIO_79,
-	GPIO_80,
-	GPIO_81,
-	GPIO_82,
-	GPIO_83,
-	GPIO_84,
-	GPIO_85,
-	GPIO_86,
-	GPIO_87,
-	GPIO_88,
-	GPIO_89,
-	GPIO_90,
-	GPIO_91,
-	GPIO_92,
-	GPIO_93,
-	GPIO_94,
-	GPIO_95,
-	GPIO_96,
-	GPIO_97,
-	GPIO_98,
-	GPIO_99,
-	GPIO_100,
-	GPIO_101,
-	GPIO_102,
-	GPIO_103,
-	GPIO_104,
-	GPIO_105,
-	GPIO_106,
-	GPIO_107,
-	GPIO_108,
-	GPIO_109,
-	GPIO_110,
-	GPIO_111,
-	GPIO_112,
-	GPIO_113,
-	GPIO_114,
-	GPIO_115,
-	GPIO_116,
-	GPIO_117,
-	GPIO_118,
-	GPIO_119,
-	GPIO_120,
-	GPIO_121,
-	GPIO_122,
-	GPIO_123,
-	GPIO_124,
-	GPIO_125,
-	GPIO_126,
-	GPIO_127,
-	GPIO_128,
-	GPIO_129,
-	GPIO_130,
-	GPIO_131,
-	GPIO_132,
-	GPIO_133,
-	GPIO_134,
-	GPIO_135,
-	GPIO_136,
-	GPIO_137,
-	GPIO_138,
-	GPIO_139,
-	GPIO_140,
-	GPIO_141,
-	GPIO_142,
-	GPIO_143,
-	GPIO_144,
-	GPIO_145,
-	GPIO_146,
-	GPIO_147,
-	GPIO_148,
-	GPIO_149,
-	GPIO_150,
-	GPIO_151,
-	GPIO_152,
-	GPIO_153,
-	GPIO_154,
-	GPIO_155,
-	GPIO_156,
-	GPIO_157,
-	GPIO_158,
-	GPIO_159,
-	GPIO_160,
-	GPIO_161,
-	GPIO_162,
-	GPIO_163,
-	GPIO_164,
-	GPIO_165,
-	GPIO_166,
-	GPIO_167,
-	GPIO_168,
-	GPIO_169,
-	GPIO_170,
-	GPIO_171,
-	GPIO_172,
-	GPIO_173,
-	GPIO_174,
-	GPIO_175,
-	GPIO_176,
-	GPIO_177,
-	GPIO_178,
-	GPIO_179,
-	GPIO_180,
-	GPIO_181,
-	GPIO_182,
-	GPIO_183,
-	GPIO_184,
-	GPIO_185,
-	GPIO_186,
-	GPIO_187,
-	GPIO_188,
-	GPIO_189,
-	GPIO_190,
-	GPIO_191,
-	GPIO_192,
-	GPIO_193,
-	GPIO_194,
-	GPIO_195,
-	GPIO_196,
-	GPIO_197,
-	GPIO_198,
-	GPIO_199,
-	GPIO_200,
-	GPIO_201,
-	GPIO_202,
-	GPIO_203,
-	GPIO_204,
-	GPIO_205,
-	GPIO_206,
-	GPIO_207,
-	GPIO_208,
-	GPIO_209,
-	GPIO_210,
-	GPIO_211,
-	GPIO_212,
-	GPIO_213,
-	GPIO_214,
-	GPIO_215,
-	GPIO_216,
-	GPIO_217,
-	GPIO_218,
-	GPIO_219,
-	GPIO_220,
-	GPIO_221,
-	GPIO_222,
-	GPIO_223,
-	GPIO_224,
-	GPIO_225,
-	GPIO_226,
-	GPIO_227,
-	GPIO_228,
-	GPIO_229,
-	MAX_GPIO_NO
-} GPIO_COUNT;
-
-typedef struct _GPIO_SETTINGS
-{
-	u8 select;
-	u8 type;
-	u8 value;
-	u8 NonGpioGevent;
-} GPIO_SETTINGS;
-
-GPIO_SETTINGS gpio_table[]=
-{
-	{GPIO_00_SELECT, GPIO_00_TYPE, GPO_00_LEVEL+GPIO_00_STICKY+GPIO_00_PULLUP+GPIO_00_PULLDOWN, GPIO_00_SELECT},
-	{GPIO_01_SELECT, GPIO_01_TYPE, GPO_01_LEVEL+GPIO_01_STICKY+GPIO_01_PULLUP+GPIO_01_PULLDOWN, GPIO_01_SELECT},
-	{GPIO_02_SELECT, GPIO_02_TYPE, GPO_02_LEVEL+GPIO_02_STICKY+GPIO_02_PULLUP+GPIO_02_PULLDOWN, GPIO_02_SELECT},
-	{GPIO_03_SELECT, GPIO_03_TYPE, GPO_03_LEVEL+GPIO_03_STICKY+GPIO_03_PULLUP+GPIO_03_PULLDOWN, GPIO_03_SELECT},
-	{GPIO_04_SELECT, GPIO_04_TYPE, GPO_04_LEVEL+GPIO_04_STICKY+GPIO_04_PULLUP+GPIO_04_PULLDOWN, GPIO_04_SELECT},
-	{GPIO_05_SELECT, GPIO_05_TYPE, GPO_05_LEVEL+GPIO_05_STICKY+GPIO_05_PULLUP+GPIO_05_PULLDOWN, GPIO_05_SELECT},
-	{GPIO_06_SELECT, GPIO_06_TYPE, GPO_06_LEVEL+GPIO_06_STICKY+GPIO_06_PULLUP+GPIO_06_PULLDOWN, GPIO_06_SELECT},
-	{GPIO_07_SELECT, GPIO_07_TYPE, GPO_07_LEVEL+GPIO_07_STICKY+GPIO_07_PULLUP+GPIO_07_PULLDOWN, GPIO_07_SELECT},
-	{GPIO_08_SELECT, GPIO_08_TYPE, GPO_08_LEVEL+GPIO_08_STICKY+GPIO_08_PULLUP+GPIO_08_PULLDOWN, GPIO_08_SELECT},
-	{GPIO_09_SELECT, GPIO_09_TYPE, GPO_09_LEVEL+GPIO_09_STICKY+GPIO_09_PULLUP+GPIO_09_PULLDOWN, GPIO_09_SELECT},
-	{GPIO_10_SELECT, GPIO_10_TYPE, GPO_10_LEVEL+GPIO_10_STICKY+GPIO_10_PULLUP+GPIO_10_PULLDOWN, GPIO_10_SELECT},
-	{GPIO_11_SELECT, GPIO_11_TYPE, GPO_11_LEVEL+GPIO_11_STICKY+GPIO_11_PULLUP+GPIO_11_PULLDOWN, GPIO_11_SELECT},
-	{GPIO_12_SELECT, GPIO_12_TYPE, GPO_12_LEVEL+GPIO_12_STICKY+GPIO_12_PULLUP+GPIO_12_PULLDOWN, GPIO_12_SELECT},
-	{GPIO_13_SELECT, GPIO_13_TYPE, GPO_13_LEVEL+GPIO_13_STICKY+GPIO_13_PULLUP+GPIO_13_PULLDOWN, GPIO_13_SELECT},
-	{GPIO_14_SELECT, GPIO_14_TYPE, GPO_14_LEVEL+GPIO_14_STICKY+GPIO_14_PULLUP+GPIO_14_PULLDOWN, GPIO_14_SELECT},
-	{GPIO_15_SELECT, GPIO_15_TYPE, GPO_15_LEVEL+GPIO_15_STICKY+GPIO_15_PULLUP+GPIO_15_PULLDOWN, GPIO_15_SELECT},
-	{GPIO_16_SELECT, GPIO_16_TYPE, GPO_16_LEVEL+GPIO_16_STICKY+GPIO_16_PULLUP+GPIO_16_PULLDOWN, GPIO_16_SELECT},
-	{GPIO_17_SELECT, GPIO_17_TYPE, GPO_17_LEVEL+GPIO_17_STICKY+GPIO_17_PULLUP+GPIO_17_PULLDOWN, GPIO_17_SELECT},
-	{GPIO_18_SELECT, GPIO_18_TYPE, GPO_18_LEVEL+GPIO_18_STICKY+GPIO_18_PULLUP+GPIO_18_PULLDOWN, GPIO_18_SELECT},
-	{GPIO_19_SELECT, GPIO_19_TYPE, GPO_19_LEVEL+GPIO_19_STICKY+GPIO_19_PULLUP+GPIO_19_PULLDOWN, GPIO_19_SELECT},
-	{GPIO_20_SELECT, GPIO_20_TYPE, GPO_20_LEVEL+GPIO_20_STICKY+GPIO_20_PULLUP+GPIO_20_PULLDOWN, GPIO_20_SELECT},
-	{GPIO_21_SELECT, GPIO_21_TYPE, GPO_21_LEVEL+GPIO_21_STICKY+GPIO_21_PULLUP+GPIO_21_PULLDOWN, GPIO_21_SELECT},
-	{GPIO_22_SELECT, GPIO_22_TYPE, GPO_22_LEVEL+GPIO_22_STICKY+GPIO_22_PULLUP+GPIO_22_PULLDOWN, GPIO_22_SELECT},
-	{GPIO_23_SELECT, GPIO_23_TYPE, GPO_23_LEVEL+GPIO_23_STICKY+GPIO_23_PULLUP+GPIO_23_PULLDOWN, GPIO_23_SELECT},
-	{GPIO_24_SELECT, GPIO_24_TYPE, GPO_24_LEVEL+GPIO_24_STICKY+GPIO_24_PULLUP+GPIO_24_PULLDOWN, GPIO_24_SELECT},
-	{GPIO_25_SELECT, GPIO_25_TYPE, GPO_25_LEVEL+GPIO_25_STICKY+GPIO_25_PULLUP+GPIO_25_PULLDOWN, GPIO_25_SELECT},
-	{GPIO_26_SELECT, GPIO_26_TYPE, GPO_26_LEVEL+GPIO_26_STICKY+GPIO_26_PULLUP+GPIO_26_PULLDOWN, GPIO_26_SELECT},
-	{GPIO_27_SELECT, GPIO_27_TYPE, GPO_27_LEVEL+GPIO_27_STICKY+GPIO_27_PULLUP+GPIO_27_PULLDOWN, GPIO_27_SELECT},
-	{GPIO_28_SELECT, GPIO_28_TYPE, GPO_28_LEVEL+GPIO_28_STICKY+GPIO_28_PULLUP+GPIO_28_PULLDOWN, GPIO_28_SELECT},
-	{GPIO_29_SELECT, GPIO_29_TYPE, GPO_29_LEVEL+GPIO_29_STICKY+GPIO_29_PULLUP+GPIO_29_PULLDOWN, GPIO_29_SELECT},
-	{GPIO_30_SELECT, GPIO_30_TYPE, GPO_30_LEVEL+GPIO_30_STICKY+GPIO_30_PULLUP+GPIO_30_PULLDOWN, GPIO_30_SELECT},
-	{GPIO_31_SELECT, GPIO_31_TYPE, GPO_31_LEVEL+GPIO_31_STICKY+GPIO_31_PULLUP+GPIO_31_PULLDOWN, GPIO_31_SELECT},
-	{GPIO_32_SELECT, GPIO_32_TYPE, GPO_32_LEVEL+GPIO_32_STICKY+GPIO_32_PULLUP+GPIO_32_PULLDOWN, GPIO_32_SELECT},
-	{GPIO_33_SELECT, GPIO_33_TYPE, GPO_33_LEVEL+GPIO_33_STICKY+GPIO_33_PULLUP+GPIO_33_PULLDOWN, GPIO_33_SELECT},
-	{GPIO_34_SELECT, GPIO_34_TYPE, GPO_34_LEVEL+GPIO_34_STICKY+GPIO_34_PULLUP+GPIO_34_PULLDOWN, GPIO_34_SELECT},
-	{GPIO_35_SELECT, GPIO_35_TYPE, GPO_35_LEVEL+GPIO_35_STICKY+GPIO_35_PULLUP+GPIO_35_PULLDOWN, GPIO_35_SELECT},
-	{GPIO_36_SELECT, GPIO_36_TYPE, GPO_36_LEVEL+GPIO_36_STICKY+GPIO_36_PULLUP+GPIO_36_PULLDOWN, GPIO_36_SELECT},
-	{GPIO_37_SELECT, GPIO_37_TYPE, GPO_37_LEVEL+GPIO_37_STICKY+GPIO_37_PULLUP+GPIO_37_PULLDOWN, GPIO_37_SELECT},
-	{GPIO_38_SELECT, GPIO_38_TYPE, GPO_38_LEVEL+GPIO_38_STICKY+GPIO_38_PULLUP+GPIO_38_PULLDOWN, GPIO_38_SELECT},
-	{GPIO_39_SELECT, GPIO_39_TYPE, GPO_39_LEVEL+GPIO_39_STICKY+GPIO_39_PULLUP+GPIO_39_PULLDOWN, GPIO_39_SELECT},
-	{GPIO_40_SELECT, GPIO_40_TYPE, GPO_40_LEVEL+GPIO_40_STICKY+GPIO_40_PULLUP+GPIO_40_PULLDOWN, GPIO_40_SELECT},
-	{GPIO_41_SELECT, GPIO_41_TYPE, GPO_41_LEVEL+GPIO_41_STICKY+GPIO_41_PULLUP+GPIO_41_PULLDOWN, GPIO_41_SELECT},
-	{GPIO_42_SELECT, GPIO_42_TYPE, GPO_42_LEVEL+GPIO_42_STICKY+GPIO_42_PULLUP+GPIO_42_PULLDOWN, GPIO_42_SELECT},
-	{GPIO_43_SELECT, GPIO_43_TYPE, GPO_43_LEVEL+GPIO_43_STICKY+GPIO_43_PULLUP+GPIO_43_PULLDOWN, GPIO_43_SELECT},
-	{GPIO_44_SELECT, GPIO_44_TYPE, GPO_44_LEVEL+GPIO_44_STICKY+GPIO_44_PULLUP+GPIO_44_PULLDOWN, GPIO_44_SELECT},
-	{GPIO_45_SELECT, GPIO_45_TYPE, GPO_45_LEVEL+GPIO_45_STICKY+GPIO_45_PULLUP+GPIO_45_PULLDOWN, GPIO_45_SELECT},
-	{GPIO_46_SELECT, GPIO_46_TYPE, GPO_46_LEVEL+GPIO_46_STICKY+GPIO_46_PULLUP+GPIO_46_PULLDOWN, GPIO_46_SELECT},
-	{GPIO_47_SELECT, GPIO_47_TYPE, GPO_47_LEVEL+GPIO_47_STICKY+GPIO_47_PULLUP+GPIO_47_PULLDOWN, GPIO_47_SELECT},
-	{GPIO_48_SELECT, GPIO_48_TYPE, GPO_48_LEVEL+GPIO_48_STICKY+GPIO_48_PULLUP+GPIO_48_PULLDOWN, GPIO_48_SELECT},
-	{GPIO_49_SELECT, GPIO_49_TYPE, GPO_49_LEVEL+GPIO_49_STICKY+GPIO_49_PULLUP+GPIO_49_PULLDOWN, GPIO_49_SELECT},
-	{GPIO_50_SELECT, GPIO_50_TYPE, GPO_50_LEVEL+GPIO_50_STICKY+GPIO_50_PULLUP+GPIO_50_PULLDOWN, GPIO_50_SELECT},
-	{GPIO_51_SELECT, GPIO_51_TYPE, GPO_51_LEVEL+GPIO_51_STICKY+GPIO_51_PULLUP+GPIO_51_PULLDOWN, GPIO_51_SELECT},
-	{GPIO_52_SELECT, GPIO_52_TYPE, GPO_52_LEVEL+GPIO_52_STICKY+GPIO_52_PULLUP+GPIO_52_PULLDOWN, GPIO_52_SELECT},
-	{GPIO_53_SELECT, GPIO_53_TYPE, GPO_53_LEVEL+GPIO_53_STICKY+GPIO_53_PULLUP+GPIO_53_PULLDOWN, GPIO_53_SELECT},
-	{GPIO_54_SELECT, GPIO_54_TYPE, GPO_54_LEVEL+GPIO_54_STICKY+GPIO_54_PULLUP+GPIO_54_PULLDOWN, GPIO_54_SELECT},
-	{GPIO_55_SELECT, GPIO_55_TYPE, GPO_55_LEVEL+GPIO_55_STICKY+GPIO_55_PULLUP+GPIO_55_PULLDOWN, GPIO_55_SELECT},
-	{GPIO_56_SELECT, GPIO_56_TYPE, GPO_56_LEVEL+GPIO_56_STICKY+GPIO_56_PULLUP+GPIO_56_PULLDOWN, GPIO_56_SELECT},
-	{GPIO_57_SELECT, GPIO_57_TYPE, GPO_57_LEVEL+GPIO_57_STICKY+GPIO_57_PULLUP+GPIO_57_PULLDOWN, GPIO_57_SELECT},
-	{GPIO_58_SELECT, GPIO_58_TYPE, GPO_58_LEVEL+GPIO_58_STICKY+GPIO_58_PULLUP+GPIO_58_PULLDOWN, GPIO_58_SELECT},
-	{GPIO_59_SELECT, GPIO_59_TYPE, GPO_59_LEVEL+GPIO_59_STICKY+GPIO_59_PULLUP+GPIO_59_PULLDOWN, GPIO_59_SELECT},
-	{GPIO_60_SELECT, GPIO_60_TYPE, GPO_60_LEVEL+GPIO_60_STICKY+GPIO_60_PULLUP+GPIO_60_PULLDOWN, GPIO_60_SELECT},
-	{GPIO_61_SELECT, GPIO_61_TYPE, GPO_61_LEVEL+GPIO_61_STICKY+GPIO_61_PULLUP+GPIO_61_PULLDOWN, GPIO_61_SELECT},
-	{GPIO_62_SELECT, GPIO_62_TYPE, GPO_62_LEVEL+GPIO_62_STICKY+GPIO_62_PULLUP+GPIO_62_PULLDOWN, GPIO_62_SELECT},
-	{GPIO_63_SELECT, GPIO_63_TYPE, GPO_63_LEVEL+GPIO_63_STICKY+GPIO_63_PULLUP+GPIO_63_PULLDOWN, GPIO_63_SELECT},
-	{GPIO_64_SELECT, GPIO_64_TYPE, GPO_64_LEVEL+GPIO_64_STICKY+GPIO_64_PULLUP+GPIO_64_PULLDOWN, GPIO_64_SELECT},
-	{GPIO_65_SELECT, GPIO_65_TYPE, GPO_65_LEVEL+GPIO_65_STICKY+GPIO_65_PULLUP+GPIO_65_PULLDOWN, GPIO_65_SELECT},
-	{GPIO_66_SELECT, GPIO_66_TYPE, GPO_66_LEVEL+GPIO_66_STICKY+GPIO_66_PULLUP+GPIO_66_PULLDOWN, GPIO_66_SELECT},
-	{GPIO_67_SELECT, GPIO_67_TYPE, GPO_67_LEVEL+GPIO_67_STICKY+GPIO_67_PULLUP+GPIO_67_PULLDOWN, GPIO_67_SELECT},
-	{GPIO_68_SELECT, GPIO_68_TYPE, GPO_68_LEVEL+GPIO_68_STICKY+GPIO_68_PULLUP+GPIO_68_PULLDOWN, GPIO_68_SELECT},
-	{GPIO_69_SELECT, GPIO_69_TYPE, GPO_69_LEVEL+GPIO_69_STICKY+GPIO_69_PULLUP+GPIO_69_PULLDOWN, GPIO_69_SELECT},
-	{GPIO_70_SELECT, GPIO_70_TYPE, GPO_70_LEVEL+GPIO_70_STICKY+GPIO_70_PULLUP+GPIO_70_PULLDOWN, GPIO_70_SELECT},
-	{GPIO_71_SELECT, GPIO_71_TYPE, GPO_71_LEVEL+GPIO_71_STICKY+GPIO_71_PULLUP+GPIO_71_PULLDOWN, GPIO_71_SELECT},
-	{GPIO_72_SELECT, GPIO_72_TYPE, GPO_72_LEVEL+GPIO_72_STICKY+GPIO_72_PULLUP+GPIO_72_PULLDOWN, GPIO_72_SELECT},
-	{GPIO_73_SELECT, GPIO_73_TYPE, GPO_73_LEVEL+GPIO_73_STICKY+GPIO_73_PULLUP+GPIO_73_PULLDOWN, GPIO_73_SELECT},
-	{GPIO_74_SELECT, GPIO_74_TYPE, GPO_74_LEVEL+GPIO_74_STICKY+GPIO_74_PULLUP+GPIO_74_PULLDOWN, GPIO_74_SELECT},
-	{GPIO_75_SELECT, GPIO_75_TYPE, GPO_75_LEVEL+GPIO_75_STICKY+GPIO_75_PULLUP+GPIO_75_PULLDOWN, GPIO_75_SELECT},
-	{GPIO_76_SELECT, GPIO_76_TYPE, GPO_76_LEVEL+GPIO_76_STICKY+GPIO_76_PULLUP+GPIO_76_PULLDOWN, GPIO_76_SELECT},
-	{GPIO_77_SELECT, GPIO_77_TYPE, GPO_77_LEVEL+GPIO_77_STICKY+GPIO_77_PULLUP+GPIO_77_PULLDOWN, GPIO_77_SELECT},
-	{GPIO_78_SELECT, GPIO_78_TYPE, GPO_78_LEVEL+GPIO_78_STICKY+GPIO_78_PULLUP+GPIO_78_PULLDOWN, GPIO_78_SELECT},
-	{GPIO_79_SELECT, GPIO_79_TYPE, GPO_79_LEVEL+GPIO_79_STICKY+GPIO_79_PULLUP+GPIO_79_PULLDOWN, GPIO_79_SELECT},
-	{GPIO_80_SELECT, GPIO_80_TYPE, GPO_80_LEVEL+GPIO_80_STICKY+GPIO_80_PULLUP+GPIO_80_PULLDOWN, GPIO_80_SELECT},
-	{GPIO_81_SELECT, GPIO_81_TYPE, GPO_81_LEVEL+GPIO_81_STICKY+GPIO_81_PULLUP+GPIO_81_PULLDOWN, GPIO_81_SELECT},
-	{GPIO_82_SELECT, GPIO_82_TYPE, GPO_82_LEVEL+GPIO_82_STICKY+GPIO_82_PULLUP+GPIO_82_PULLDOWN, GPIO_82_SELECT},
-	{GPIO_83_SELECT, GPIO_83_TYPE, GPO_83_LEVEL+GPIO_83_STICKY+GPIO_83_PULLUP+GPIO_83_PULLDOWN, GPIO_83_SELECT},
-	{GPIO_84_SELECT, GPIO_84_TYPE, GPO_84_LEVEL+GPIO_84_STICKY+GPIO_84_PULLUP+GPIO_84_PULLDOWN, GPIO_84_SELECT},
-	{GPIO_85_SELECT, GPIO_85_TYPE, GPO_85_LEVEL+GPIO_85_STICKY+GPIO_85_PULLUP+GPIO_85_PULLDOWN, GPIO_85_SELECT},
-	{GPIO_86_SELECT, GPIO_86_TYPE, GPO_86_LEVEL+GPIO_86_STICKY+GPIO_86_PULLUP+GPIO_86_PULLDOWN, GPIO_86_SELECT},
-	{GPIO_87_SELECT, GPIO_87_TYPE, GPO_87_LEVEL+GPIO_87_STICKY+GPIO_87_PULLUP+GPIO_87_PULLDOWN, GPIO_87_SELECT},
-	{GPIO_88_SELECT, GPIO_88_TYPE, GPO_88_LEVEL+GPIO_88_STICKY+GPIO_88_PULLUP+GPIO_88_PULLDOWN, GPIO_88_SELECT},
-	{GPIO_89_SELECT, GPIO_89_TYPE, GPO_89_LEVEL+GPIO_89_STICKY+GPIO_89_PULLUP+GPIO_89_PULLDOWN, GPIO_89_SELECT},
-	{GPIO_90_SELECT, GPIO_90_TYPE, GPO_90_LEVEL+GPIO_90_STICKY+GPIO_90_PULLUP+GPIO_90_PULLDOWN, GPIO_90_SELECT},
-	{GPIO_91_SELECT, GPIO_91_TYPE, GPO_91_LEVEL+GPIO_91_STICKY+GPIO_91_PULLUP+GPIO_91_PULLDOWN, GPIO_91_SELECT},
-	{GPIO_92_SELECT, GPIO_92_TYPE, GPO_92_LEVEL+GPIO_92_STICKY+GPIO_92_PULLUP+GPIO_92_PULLDOWN, GPIO_92_SELECT},
-	{GPIO_93_SELECT, GPIO_93_TYPE, GPO_93_LEVEL+GPIO_93_STICKY+GPIO_93_PULLUP+GPIO_93_PULLDOWN, GPIO_93_SELECT},
-	{GPIO_94_SELECT, GPIO_94_TYPE, GPO_94_LEVEL+GPIO_94_STICKY+GPIO_94_PULLUP+GPIO_94_PULLDOWN, GPIO_94_SELECT},
-	{GPIO_95_SELECT, GPIO_95_TYPE, GPO_95_LEVEL+GPIO_95_STICKY+GPIO_95_PULLUP+GPIO_95_PULLDOWN, GPIO_95_SELECT},
-	{GPIO_96_SELECT, GPIO_96_TYPE, GPO_96_LEVEL+GPIO_96_STICKY+GPIO_96_PULLUP+GPIO_96_PULLDOWN, GPIO_96_SELECT},
-	{GPIO_97_SELECT, GPIO_97_TYPE, GPO_97_LEVEL+GPIO_97_STICKY+GPIO_97_PULLUP+GPIO_97_PULLDOWN, GPIO_97_SELECT},
-	{GPIO_98_SELECT, GPIO_98_TYPE, GPO_98_LEVEL+GPIO_98_STICKY+GPIO_98_PULLUP+GPIO_98_PULLDOWN, GPIO_98_SELECT},
-	{GPIO_99_SELECT, GPIO_99_TYPE, GPO_99_LEVEL+GPIO_99_STICKY+GPIO_99_PULLUP+GPIO_99_PULLDOWN, GPIO_99_SELECT},
-	{GPIO_100_SELECT, GPIO_100_TYPE, GPO_100_LEVEL+GPIO_100_STICKY+GPIO_100_PULLUP+GPIO_100_PULLDOWN, GPIO_100_SELECT},
-	{GPIO_101_SELECT, GPIO_101_TYPE, GPO_101_LEVEL+GPIO_101_STICKY+GPIO_101_PULLUP+GPIO_101_PULLDOWN, GPIO_101_SELECT},
-	{GPIO_102_SELECT, GPIO_102_TYPE, GPO_102_LEVEL+GPIO_102_STICKY+GPIO_102_PULLUP+GPIO_102_PULLDOWN, GPIO_102_SELECT},
-	{GPIO_103_SELECT, GPIO_103_TYPE, GPO_103_LEVEL+GPIO_103_STICKY+GPIO_103_PULLUP+GPIO_103_PULLDOWN, GPIO_103_SELECT},
-	{GPIO_104_SELECT, GPIO_104_TYPE, GPO_104_LEVEL+GPIO_104_STICKY+GPIO_104_PULLUP+GPIO_104_PULLDOWN, GPIO_104_SELECT},
-	{GPIO_105_SELECT, GPIO_105_TYPE, GPO_105_LEVEL+GPIO_105_STICKY+GPIO_105_PULLUP+GPIO_105_PULLDOWN, GPIO_105_SELECT},
-	{GPIO_106_SELECT, GPIO_106_TYPE, GPO_106_LEVEL+GPIO_106_STICKY+GPIO_106_PULLUP+GPIO_106_PULLDOWN, GPIO_106_SELECT},
-	{GPIO_107_SELECT, GPIO_107_TYPE, GPO_107_LEVEL+GPIO_107_STICKY+GPIO_107_PULLUP+GPIO_107_PULLDOWN, GPIO_107_SELECT},
-	{GPIO_108_SELECT, GPIO_108_TYPE, GPO_108_LEVEL+GPIO_108_STICKY+GPIO_108_PULLUP+GPIO_108_PULLDOWN, GPIO_108_SELECT},
-	{GPIO_109_SELECT, GPIO_109_TYPE, GPO_109_LEVEL+GPIO_109_STICKY+GPIO_109_PULLUP+GPIO_109_PULLDOWN, GPIO_109_SELECT},
-	{GPIO_110_SELECT, GPIO_110_TYPE, GPO_110_LEVEL+GPIO_110_STICKY+GPIO_110_PULLUP+GPIO_110_PULLDOWN, GPIO_110_SELECT},
-	{GPIO_111_SELECT, GPIO_111_TYPE, GPO_111_LEVEL+GPIO_111_STICKY+GPIO_111_PULLUP+GPIO_111_PULLDOWN, GPIO_111_SELECT},
-	{GPIO_112_SELECT, GPIO_112_TYPE, GPO_112_LEVEL+GPIO_112_STICKY+GPIO_112_PULLUP+GPIO_112_PULLDOWN, GPIO_112_SELECT},
-	{GPIO_113_SELECT, GPIO_113_TYPE, GPO_113_LEVEL+GPIO_113_STICKY+GPIO_113_PULLUP+GPIO_113_PULLDOWN, GPIO_113_SELECT},
-	{GPIO_114_SELECT, GPIO_114_TYPE, GPO_114_LEVEL+GPIO_114_STICKY+GPIO_114_PULLUP+GPIO_114_PULLDOWN, GPIO_114_SELECT},
-	{GPIO_115_SELECT, GPIO_115_TYPE, GPO_115_LEVEL+GPIO_115_STICKY+GPIO_115_PULLUP+GPIO_115_PULLDOWN, GPIO_115_SELECT},
-	{GPIO_116_SELECT, GPIO_116_TYPE, GPO_116_LEVEL+GPIO_116_STICKY+GPIO_116_PULLUP+GPIO_116_PULLDOWN, GPIO_116_SELECT},
-	{GPIO_117_SELECT, GPIO_117_TYPE, GPO_117_LEVEL+GPIO_117_STICKY+GPIO_117_PULLUP+GPIO_117_PULLDOWN, GPIO_117_SELECT},
-	{GPIO_118_SELECT, GPIO_118_TYPE, GPO_118_LEVEL+GPIO_118_STICKY+GPIO_118_PULLUP+GPIO_118_PULLDOWN, GPIO_118_SELECT},
-	{GPIO_119_SELECT, GPIO_119_TYPE, GPO_119_LEVEL+GPIO_119_STICKY+GPIO_119_PULLUP+GPIO_119_PULLDOWN, GPIO_119_SELECT},
-	{GPIO_120_SELECT, GPIO_120_TYPE, GPO_120_LEVEL+GPIO_120_STICKY+GPIO_120_PULLUP+GPIO_120_PULLDOWN, GPIO_120_SELECT},
-	{GPIO_121_SELECT, GPIO_121_TYPE, GPO_121_LEVEL+GPIO_121_STICKY+GPIO_121_PULLUP+GPIO_121_PULLDOWN, GPIO_121_SELECT},
-	{GPIO_122_SELECT, GPIO_122_TYPE, GPO_122_LEVEL+GPIO_122_STICKY+GPIO_122_PULLUP+GPIO_122_PULLDOWN, GPIO_122_SELECT},
-	{GPIO_123_SELECT, GPIO_123_TYPE, GPO_123_LEVEL+GPIO_123_STICKY+GPIO_123_PULLUP+GPIO_123_PULLDOWN, GPIO_123_SELECT},
-	{GPIO_124_SELECT, GPIO_124_TYPE, GPO_124_LEVEL+GPIO_124_STICKY+GPIO_124_PULLUP+GPIO_124_PULLDOWN, GPIO_124_SELECT},
-	{GPIO_125_SELECT, GPIO_125_TYPE, GPO_125_LEVEL+GPIO_125_STICKY+GPIO_125_PULLUP+GPIO_125_PULLDOWN, GPIO_125_SELECT},
-	{GPIO_126_SELECT, GPIO_126_TYPE, GPO_126_LEVEL+GPIO_126_STICKY+GPIO_126_PULLUP+GPIO_126_PULLDOWN, GPIO_126_SELECT},
-	{GPIO_127_SELECT, GPIO_127_TYPE, GPO_127_LEVEL+GPIO_127_STICKY+GPIO_127_PULLUP+GPIO_127_PULLDOWN, GPIO_127_SELECT},
-	{GPIO_128_SELECT, GPIO_128_TYPE, GPO_128_LEVEL+GPIO_128_STICKY+GPIO_128_PULLUP+GPIO_128_PULLDOWN, GPIO_128_SELECT},
-	{GPIO_129_SELECT, GPIO_129_TYPE, GPO_129_LEVEL+GPIO_129_STICKY+GPIO_129_PULLUP+GPIO_129_PULLDOWN, GPIO_129_SELECT},
-	{GPIO_130_SELECT, GPIO_130_TYPE, GPO_130_LEVEL+GPIO_130_STICKY+GPIO_130_PULLUP+GPIO_130_PULLDOWN, GPIO_130_SELECT},
-	{GPIO_131_SELECT, GPIO_131_TYPE, GPO_131_LEVEL+GPIO_131_STICKY+GPIO_131_PULLUP+GPIO_131_PULLDOWN, GPIO_131_SELECT},
-	{GPIO_132_SELECT, GPIO_132_TYPE, GPO_132_LEVEL+GPIO_132_STICKY+GPIO_132_PULLUP+GPIO_132_PULLDOWN, GPIO_132_SELECT},
-	{GPIO_133_SELECT, GPIO_133_TYPE, GPO_133_LEVEL+GPIO_133_STICKY+GPIO_133_PULLUP+GPIO_133_PULLDOWN, GPIO_133_SELECT},
-	{GPIO_134_SELECT, GPIO_134_TYPE, GPO_134_LEVEL+GPIO_134_STICKY+GPIO_134_PULLUP+GPIO_134_PULLDOWN, GPIO_134_SELECT},
-	{GPIO_135_SELECT, GPIO_135_TYPE, GPO_135_LEVEL+GPIO_135_STICKY+GPIO_135_PULLUP+GPIO_135_PULLDOWN, GPIO_135_SELECT},
-	{GPIO_136_SELECT, GPIO_136_TYPE, GPO_136_LEVEL+GPIO_136_STICKY+GPIO_136_PULLUP+GPIO_136_PULLDOWN, GPIO_136_SELECT},
-	{GPIO_137_SELECT, GPIO_137_TYPE, GPO_137_LEVEL+GPIO_137_STICKY+GPIO_137_PULLUP+GPIO_137_PULLDOWN, GPIO_137_SELECT},
-	{GPIO_138_SELECT, GPIO_138_TYPE, GPO_138_LEVEL+GPIO_138_STICKY+GPIO_138_PULLUP+GPIO_138_PULLDOWN, GPIO_138_SELECT},
-	{GPIO_139_SELECT, GPIO_139_TYPE, GPO_139_LEVEL+GPIO_139_STICKY+GPIO_139_PULLUP+GPIO_139_PULLDOWN, GPIO_139_SELECT},
-	{GPIO_140_SELECT, GPIO_140_TYPE, GPO_140_LEVEL+GPIO_140_STICKY+GPIO_140_PULLUP+GPIO_140_PULLDOWN, GPIO_140_SELECT},
-	{GPIO_141_SELECT, GPIO_141_TYPE, GPO_141_LEVEL+GPIO_141_STICKY+GPIO_141_PULLUP+GPIO_141_PULLDOWN, GPIO_141_SELECT},
-	{GPIO_142_SELECT, GPIO_142_TYPE, GPO_142_LEVEL+GPIO_142_STICKY+GPIO_142_PULLUP+GPIO_142_PULLDOWN, GPIO_142_SELECT},
-	{GPIO_143_SELECT, GPIO_143_TYPE, GPO_143_LEVEL+GPIO_143_STICKY+GPIO_143_PULLUP+GPIO_143_PULLDOWN, GPIO_143_SELECT},
-	{GPIO_144_SELECT, GPIO_144_TYPE, GPO_144_LEVEL+GPIO_144_STICKY+GPIO_144_PULLUP+GPIO_144_PULLDOWN, GPIO_144_SELECT},
-	{GPIO_145_SELECT, GPIO_145_TYPE, GPO_145_LEVEL+GPIO_145_STICKY+GPIO_145_PULLUP+GPIO_145_PULLDOWN, GPIO_145_SELECT},
-	{GPIO_146_SELECT, GPIO_146_TYPE, GPO_146_LEVEL+GPIO_146_STICKY+GPIO_146_PULLUP+GPIO_146_PULLDOWN, GPIO_146_SELECT},
-	{GPIO_147_SELECT, GPIO_147_TYPE, GPO_147_LEVEL+GPIO_147_STICKY+GPIO_147_PULLUP+GPIO_147_PULLDOWN, GPIO_147_SELECT},
-	{GPIO_148_SELECT, GPIO_148_TYPE, GPO_148_LEVEL+GPIO_148_STICKY+GPIO_148_PULLUP+GPIO_148_PULLDOWN, GPIO_148_SELECT},
-	{GPIO_149_SELECT, GPIO_149_TYPE, GPO_149_LEVEL+GPIO_149_STICKY+GPIO_149_PULLUP+GPIO_149_PULLDOWN, GPIO_149_SELECT},
-	{GPIO_150_SELECT, GPIO_150_TYPE, GPO_150_LEVEL+GPIO_150_STICKY+GPIO_150_PULLUP+GPIO_150_PULLDOWN, GPIO_150_SELECT},
-	{GPIO_151_SELECT, GPIO_151_TYPE, GPO_151_LEVEL+GPIO_151_STICKY+GPIO_151_PULLUP+GPIO_151_PULLDOWN, GPIO_151_SELECT},
-	{GPIO_152_SELECT, GPIO_152_TYPE, GPO_152_LEVEL+GPIO_152_STICKY+GPIO_152_PULLUP+GPIO_152_PULLDOWN, GPIO_152_SELECT},
-	{GPIO_153_SELECT, GPIO_153_TYPE, GPO_153_LEVEL+GPIO_153_STICKY+GPIO_153_PULLUP+GPIO_153_PULLDOWN, GPIO_153_SELECT},
-	{GPIO_154_SELECT, GPIO_154_TYPE, GPO_154_LEVEL+GPIO_154_STICKY+GPIO_154_PULLUP+GPIO_154_PULLDOWN, GPIO_154_SELECT},
-	{GPIO_155_SELECT, GPIO_155_TYPE, GPO_155_LEVEL+GPIO_155_STICKY+GPIO_155_PULLUP+GPIO_155_PULLDOWN, GPIO_155_SELECT},
-	{GPIO_156_SELECT, GPIO_156_TYPE, GPO_156_LEVEL+GPIO_156_STICKY+GPIO_156_PULLUP+GPIO_156_PULLDOWN, GPIO_156_SELECT},
-	{GPIO_157_SELECT, GPIO_157_TYPE, GPO_157_LEVEL+GPIO_157_STICKY+GPIO_157_PULLUP+GPIO_157_PULLDOWN, GPIO_157_SELECT},
-	{GPIO_158_SELECT, GPIO_158_TYPE, GPO_158_LEVEL+GPIO_158_STICKY+GPIO_158_PULLUP+GPIO_158_PULLDOWN, GPIO_158_SELECT},
-	{GPIO_159_SELECT, GPIO_159_TYPE, GPO_159_LEVEL+GPIO_159_STICKY+GPIO_159_PULLUP+GPIO_159_PULLDOWN, GPIO_159_SELECT},
-	{GPIO_160_SELECT, GPIO_160_TYPE, GPO_160_LEVEL+GPIO_160_STICKY+GPIO_160_PULLUP+GPIO_160_PULLDOWN, GPIO_160_SELECT},
-	{GPIO_161_SELECT, GPIO_161_TYPE, GPO_161_LEVEL+GPIO_161_STICKY+GPIO_161_PULLUP+GPIO_161_PULLDOWN, GPIO_161_SELECT},
-	{GPIO_162_SELECT, GPIO_162_TYPE, GPO_162_LEVEL+GPIO_162_STICKY+GPIO_162_PULLUP+GPIO_162_PULLDOWN, GPIO_162_SELECT},
-	{GPIO_163_SELECT, GPIO_163_TYPE, GPO_163_LEVEL+GPIO_163_STICKY+GPIO_163_PULLUP+GPIO_163_PULLDOWN, GPIO_163_SELECT},
-	{GPIO_164_SELECT, GPIO_164_TYPE, GPO_164_LEVEL+GPIO_164_STICKY+GPIO_164_PULLUP+GPIO_164_PULLDOWN, GPIO_164_SELECT},
-	{GPIO_165_SELECT, GPIO_165_TYPE, GPO_165_LEVEL+GPIO_165_STICKY+GPIO_165_PULLUP+GPIO_165_PULLDOWN, GPIO_165_SELECT},
-	{GPIO_166_SELECT, GPIO_166_TYPE, GPO_166_LEVEL+GPIO_166_STICKY+GPIO_166_PULLUP+GPIO_166_PULLDOWN, GPIO_166_SELECT},
-	{GPIO_167_SELECT, GPIO_167_TYPE, GPO_167_LEVEL+GPIO_167_STICKY+GPIO_167_PULLUP+GPIO_167_PULLDOWN, GPIO_167_SELECT},
-	{GPIO_168_SELECT, GPIO_168_TYPE, GPO_168_LEVEL+GPIO_168_STICKY+GPIO_168_PULLUP+GPIO_168_PULLDOWN, GPIO_168_SELECT},
-	{GPIO_169_SELECT, GPIO_169_TYPE, GPO_169_LEVEL+GPIO_169_STICKY+GPIO_169_PULLUP+GPIO_169_PULLDOWN, GPIO_169_SELECT},
-	{GPIO_170_SELECT, GPIO_170_TYPE, GPO_170_LEVEL+GPIO_170_STICKY+GPIO_170_PULLUP+GPIO_170_PULLDOWN, GPIO_170_SELECT},
-	{GPIO_171_SELECT, GPIO_171_TYPE, GPO_171_LEVEL+GPIO_171_STICKY+GPIO_171_PULLUP+GPIO_171_PULLDOWN, GPIO_171_SELECT},
-	{GPIO_172_SELECT, GPIO_172_TYPE, GPO_172_LEVEL+GPIO_172_STICKY+GPIO_172_PULLUP+GPIO_172_PULLDOWN, GPIO_172_SELECT},
-	{GPIO_173_SELECT, GPIO_173_TYPE, GPO_173_LEVEL+GPIO_173_STICKY+GPIO_173_PULLUP+GPIO_173_PULLDOWN, GPIO_173_SELECT},
-	{GPIO_174_SELECT, GPIO_174_TYPE, GPO_174_LEVEL+GPIO_174_STICKY+GPIO_174_PULLUP+GPIO_174_PULLDOWN, GPIO_174_SELECT},
-	{GPIO_175_SELECT, GPIO_175_TYPE, GPO_175_LEVEL+GPIO_175_STICKY+GPIO_175_PULLUP+GPIO_175_PULLDOWN, GPIO_175_SELECT},
-	{GPIO_176_SELECT, GPIO_176_TYPE, GPO_176_LEVEL+GPIO_176_STICKY+GPIO_176_PULLUP+GPIO_176_PULLDOWN, GPIO_176_SELECT},
-	{GPIO_177_SELECT, GPIO_177_TYPE, GPO_177_LEVEL+GPIO_177_STICKY+GPIO_177_PULLUP+GPIO_177_PULLDOWN, GPIO_177_SELECT},
-	{GPIO_178_SELECT, GPIO_178_TYPE, GPO_178_LEVEL+GPIO_178_STICKY+GPIO_178_PULLUP+GPIO_178_PULLDOWN, GPIO_178_SELECT},
-	{GPIO_179_SELECT, GPIO_179_TYPE, GPO_179_LEVEL+GPIO_179_STICKY+GPIO_179_PULLUP+GPIO_179_PULLDOWN, GPIO_179_SELECT},
-	{GPIO_180_SELECT, GPIO_180_TYPE, GPO_180_LEVEL+GPIO_180_STICKY+GPIO_180_PULLUP+GPIO_180_PULLDOWN, GPIO_180_SELECT},
-	{GPIO_181_SELECT, GPIO_181_TYPE, GPO_181_LEVEL+GPIO_181_STICKY+GPIO_181_PULLUP+GPIO_181_PULLDOWN, GPIO_181_SELECT},
-	{GPIO_182_SELECT, GPIO_182_TYPE, GPO_182_LEVEL+GPIO_182_STICKY+GPIO_182_PULLUP+GPIO_182_PULLDOWN, GPIO_182_SELECT},
-	{GPIO_183_SELECT, GPIO_183_TYPE, GPO_183_LEVEL+GPIO_183_STICKY+GPIO_183_PULLUP+GPIO_183_PULLDOWN, GPIO_183_SELECT},
-	{GPIO_184_SELECT, GPIO_184_TYPE, GPO_184_LEVEL+GPIO_184_STICKY+GPIO_184_PULLUP+GPIO_184_PULLDOWN, GPIO_184_SELECT},
-	{GPIO_185_SELECT, GPIO_185_TYPE, GPO_185_LEVEL+GPIO_185_STICKY+GPIO_185_PULLUP+GPIO_185_PULLDOWN, GPIO_185_SELECT},
-	{GPIO_186_SELECT, GPIO_186_TYPE, GPO_186_LEVEL+GPIO_186_STICKY+GPIO_186_PULLUP+GPIO_186_PULLDOWN, GPIO_186_SELECT},
-	{GPIO_187_SELECT, GPIO_187_TYPE, GPO_187_LEVEL+GPIO_187_STICKY+GPIO_187_PULLUP+GPIO_187_PULLDOWN, GPIO_187_SELECT},
-	{GPIO_188_SELECT, GPIO_188_TYPE, GPO_188_LEVEL+GPIO_188_STICKY+GPIO_188_PULLUP+GPIO_188_PULLDOWN, GPIO_188_SELECT},
-	{GPIO_189_SELECT, GPIO_189_TYPE, GPO_189_LEVEL+GPIO_189_STICKY+GPIO_189_PULLUP+GPIO_189_PULLDOWN, GPIO_189_SELECT},
-	{GPIO_190_SELECT, GPIO_190_TYPE, GPO_190_LEVEL+GPIO_190_STICKY+GPIO_190_PULLUP+GPIO_190_PULLDOWN, GPIO_190_SELECT},
-	{GPIO_191_SELECT, GPIO_191_TYPE, GPO_191_LEVEL+GPIO_191_STICKY+GPIO_191_PULLUP+GPIO_191_PULLDOWN, GPIO_191_SELECT},
-	{GPIO_192_SELECT, GPIO_192_TYPE, GPO_192_LEVEL+GPIO_192_STICKY+GPIO_192_PULLUP+GPIO_192_PULLDOWN, GPIO_192_SELECT},
-	{GPIO_193_SELECT, GPIO_193_TYPE, GPO_193_LEVEL+GPIO_193_STICKY+GPIO_193_PULLUP+GPIO_193_PULLDOWN, GPIO_193_SELECT},
-	{GPIO_194_SELECT, GPIO_194_TYPE, GPO_194_LEVEL+GPIO_194_STICKY+GPIO_194_PULLUP+GPIO_194_PULLDOWN, GPIO_194_SELECT},
-	{GPIO_195_SELECT, GPIO_195_TYPE, GPO_195_LEVEL+GPIO_195_STICKY+GPIO_195_PULLUP+GPIO_195_PULLDOWN, GPIO_195_SELECT},
-	{GPIO_196_SELECT, GPIO_196_TYPE, GPO_196_LEVEL+GPIO_196_STICKY+GPIO_196_PULLUP+GPIO_196_PULLDOWN, GPIO_196_SELECT},
-	{GPIO_197_SELECT, GPIO_197_TYPE, GPO_197_LEVEL+GPIO_197_STICKY+GPIO_197_PULLUP+GPIO_197_PULLDOWN, GPIO_197_SELECT},
-	{GPIO_198_SELECT, GPIO_198_TYPE, GPO_198_LEVEL+GPIO_198_STICKY+GPIO_198_PULLUP+GPIO_198_PULLDOWN, GPIO_198_SELECT},
-	{GPIO_199_SELECT, GPIO_199_TYPE, GPO_199_LEVEL+GPIO_199_STICKY+GPIO_199_PULLUP+GPIO_199_PULLDOWN, GPIO_199_SELECT},
-	{GPIO_200_SELECT, GPIO_200_TYPE, GPO_200_LEVEL+GPIO_200_STICKY+GPIO_200_PULLUP+GPIO_200_PULLDOWN, GPIO_200_SELECT},
-	{GPIO_201_SELECT, GPIO_201_TYPE, GPO_201_LEVEL+GPIO_201_STICKY+GPIO_201_PULLUP+GPIO_201_PULLDOWN, GPIO_201_SELECT},
-	{GPIO_202_SELECT, GPIO_202_TYPE, GPO_202_LEVEL+GPIO_202_STICKY+GPIO_202_PULLUP+GPIO_202_PULLDOWN, GPIO_202_SELECT},
-	{GPIO_203_SELECT, GPIO_203_TYPE, GPO_203_LEVEL+GPIO_203_STICKY+GPIO_203_PULLUP+GPIO_203_PULLDOWN, GPIO_203_SELECT},
-	{GPIO_204_SELECT, GPIO_204_TYPE, GPO_204_LEVEL+GPIO_204_STICKY+GPIO_204_PULLUP+GPIO_204_PULLDOWN, GPIO_204_SELECT},
-	{GPIO_205_SELECT, GPIO_205_TYPE, GPO_205_LEVEL+GPIO_205_STICKY+GPIO_205_PULLUP+GPIO_205_PULLDOWN, GPIO_205_SELECT},
-	{GPIO_206_SELECT, GPIO_206_TYPE, GPO_206_LEVEL+GPIO_206_STICKY+GPIO_206_PULLUP+GPIO_206_PULLDOWN, GPIO_206_SELECT},
-	{GPIO_207_SELECT, GPIO_207_TYPE, GPO_207_LEVEL+GPIO_207_STICKY+GPIO_207_PULLUP+GPIO_207_PULLDOWN, GPIO_207_SELECT},
-	{GPIO_208_SELECT, GPIO_208_TYPE, GPO_208_LEVEL+GPIO_208_STICKY+GPIO_208_PULLUP+GPIO_208_PULLDOWN, GPIO_208_SELECT},
-	{GPIO_209_SELECT, GPIO_209_TYPE, GPO_209_LEVEL+GPIO_209_STICKY+GPIO_209_PULLUP+GPIO_209_PULLDOWN, GPIO_209_SELECT},
-	{GPIO_210_SELECT, GPIO_210_TYPE, GPO_210_LEVEL+GPIO_210_STICKY+GPIO_210_PULLUP+GPIO_210_PULLDOWN, GPIO_210_SELECT},
-	{GPIO_211_SELECT, GPIO_211_TYPE, GPO_211_LEVEL+GPIO_211_STICKY+GPIO_211_PULLUP+GPIO_211_PULLDOWN, GPIO_211_SELECT},
-	{GPIO_212_SELECT, GPIO_212_TYPE, GPO_212_LEVEL+GPIO_212_STICKY+GPIO_212_PULLUP+GPIO_212_PULLDOWN, GPIO_212_SELECT},
-	{GPIO_213_SELECT, GPIO_213_TYPE, GPO_213_LEVEL+GPIO_213_STICKY+GPIO_213_PULLUP+GPIO_213_PULLDOWN, GPIO_213_SELECT},
-	{GPIO_214_SELECT, GPIO_214_TYPE, GPO_214_LEVEL+GPIO_214_STICKY+GPIO_214_PULLUP+GPIO_214_PULLDOWN, GPIO_214_SELECT},
-	{GPIO_215_SELECT, GPIO_215_TYPE, GPO_215_LEVEL+GPIO_215_STICKY+GPIO_215_PULLUP+GPIO_215_PULLDOWN, GPIO_215_SELECT},
-	{GPIO_216_SELECT, GPIO_216_TYPE, GPO_216_LEVEL+GPIO_216_STICKY+GPIO_216_PULLUP+GPIO_216_PULLDOWN, GPIO_216_SELECT},
-	{GPIO_217_SELECT, GPIO_217_TYPE, GPO_217_LEVEL+GPIO_217_STICKY+GPIO_217_PULLUP+GPIO_217_PULLDOWN, GPIO_217_SELECT},
-	{GPIO_218_SELECT, GPIO_218_TYPE, GPO_218_LEVEL+GPIO_218_STICKY+GPIO_218_PULLUP+GPIO_218_PULLDOWN, GPIO_218_SELECT},
-	{GPIO_219_SELECT, GPIO_219_TYPE, GPO_219_LEVEL+GPIO_219_STICKY+GPIO_219_PULLUP+GPIO_219_PULLDOWN, GPIO_219_SELECT},
-	{GPIO_220_SELECT, GPIO_220_TYPE, GPO_220_LEVEL+GPIO_220_STICKY+GPIO_220_PULLUP+GPIO_220_PULLDOWN, GPIO_220_SELECT},
-	{GPIO_221_SELECT, GPIO_221_TYPE, GPO_221_LEVEL+GPIO_221_STICKY+GPIO_221_PULLUP+GPIO_221_PULLDOWN, GPIO_221_SELECT},
-	{GPIO_222_SELECT, GPIO_222_TYPE, GPO_222_LEVEL+GPIO_222_STICKY+GPIO_222_PULLUP+GPIO_222_PULLDOWN, GPIO_222_SELECT},
-	{GPIO_223_SELECT, GPIO_223_TYPE, GPO_223_LEVEL+GPIO_223_STICKY+GPIO_223_PULLUP+GPIO_223_PULLDOWN, GPIO_223_SELECT},
-	{GPIO_224_SELECT, GPIO_224_TYPE, GPO_224_LEVEL+GPIO_224_STICKY+GPIO_224_PULLUP+GPIO_224_PULLDOWN, GPIO_224_SELECT},
-	{GPIO_225_SELECT, GPIO_225_TYPE, GPO_225_LEVEL+GPIO_225_STICKY+GPIO_225_PULLUP+GPIO_225_PULLDOWN, GPIO_225_SELECT},
-	{GPIO_226_SELECT, GPIO_226_TYPE, GPO_226_LEVEL+GPIO_226_STICKY+GPIO_226_PULLUP+GPIO_226_PULLDOWN, GPIO_226_SELECT},
-	{GPIO_227_SELECT, GPIO_227_TYPE, GPO_227_LEVEL+GPIO_227_STICKY+GPIO_227_PULLUP+GPIO_227_PULLDOWN, GPIO_227_SELECT},
-	{GPIO_228_SELECT, GPIO_228_TYPE, GPO_228_LEVEL+GPIO_228_STICKY+GPIO_228_PULLUP+GPIO_228_PULLDOWN, GPIO_228_SELECT},
-	{GPIO_229_SELECT, GPIO_229_TYPE, GPO_229_LEVEL+GPIO_229_STICKY+GPIO_229_PULLUP+GPIO_229_PULLDOWN, GPIO_229_SELECT},
-};
-
-typedef enum _GEVENT_COUNT
-{
-	GEVENT_00 = 0x60,
-	GEVENT_01,
-	GEVENT_02,
-	GEVENT_03,
-	GEVENT_04,
-	GEVENT_05,
-	GEVENT_06,
-	GEVENT_07,
-	GEVENT_08,
-	GEVENT_09,
-	GEVENT_10,
-	GEVENT_11,
-	GEVENT_12,
-	GEVENT_13,
-	GEVENT_14,
-	GEVENT_15,
-	GEVENT_16,
-	GEVENT_17,
-	GEVENT_18,
-	GEVENT_19,
-	GEVENT_20,
-	GEVENT_21,
-	GEVENT_22,
-	GEVENT_23
-} GEVENT_COUNT;
-
-typedef struct _GEVENT_SETTINGS
-{
-	u8 EventEnable;      // 0: Disable, 1: Enable
-	u8 SciTrig;          // 0: Falling Edge, 1: Rising Edge
-	u8 SciLevl;          // 0: Edge trigger, 1: Level Trigger
-	u8 SmiSciEn;         // 0: Not send SMI, 1: Send SMI
-	u8 SciS0En;          // 0: Disable, 1: Enable
-	u8 SciMap;           // 0000b->1111b
-	u8 SmiTrig;          // 0: Active Low, 1: Active High
-	u8 SmiControl;       // 0: Disable, 1: SMI 2: NMI 3: IRQ13
-} GEVENT_SETTINGS;
-
-GEVENT_SETTINGS gevent_table[] =
-{
-	{GEVENT_00_EVENTENABLE, GEVENT_00_SCITRIG, GEVENT_00_SCILEVEL, GEVENT_00_SMISCIEN, GEVENT_00_SCIS0EN, GEVENT_00_SCIMAP, GEVENT_00_SMITRIG, GEVENT_00_SMICONTROL},
-	{GEVENT_01_EVENTENABLE, GEVENT_01_SCITRIG, GEVENT_01_SCILEVEL, GEVENT_01_SMISCIEN, GEVENT_01_SCIS0EN, GEVENT_01_SCIMAP, GEVENT_01_SMITRIG, GEVENT_01_SMICONTROL},
-	{GEVENT_02_EVENTENABLE, GEVENT_02_SCITRIG, GEVENT_02_SCILEVEL, GEVENT_02_SMISCIEN, GEVENT_02_SCIS0EN, GEVENT_02_SCIMAP, GEVENT_02_SMITRIG, GEVENT_02_SMICONTROL},
-	{GEVENT_03_EVENTENABLE, GEVENT_03_SCITRIG, GEVENT_03_SCILEVEL, GEVENT_03_SMISCIEN, GEVENT_03_SCIS0EN, GEVENT_03_SCIMAP, GEVENT_03_SMITRIG, GEVENT_03_SMICONTROL},
-	{GEVENT_04_EVENTENABLE, GEVENT_04_SCITRIG, GEVENT_04_SCILEVEL, GEVENT_04_SMISCIEN, GEVENT_04_SCIS0EN, GEVENT_04_SCIMAP, GEVENT_04_SMITRIG, GEVENT_04_SMICONTROL},
-	{GEVENT_05_EVENTENABLE, GEVENT_05_SCITRIG, GEVENT_05_SCILEVEL, GEVENT_05_SMISCIEN, GEVENT_05_SCIS0EN, GEVENT_05_SCIMAP, GEVENT_05_SMITRIG, GEVENT_05_SMICONTROL},
-	{GEVENT_06_EVENTENABLE, GEVENT_06_SCITRIG, GEVENT_06_SCILEVEL, GEVENT_06_SMISCIEN, GEVENT_06_SCIS0EN, GEVENT_06_SCIMAP, GEVENT_06_SMITRIG, GEVENT_06_SMICONTROL},
-	{GEVENT_07_EVENTENABLE, GEVENT_07_SCITRIG, GEVENT_07_SCILEVEL, GEVENT_07_SMISCIEN, GEVENT_07_SCIS0EN, GEVENT_07_SCIMAP, GEVENT_07_SMITRIG, GEVENT_07_SMICONTROL},
-	{GEVENT_08_EVENTENABLE, GEVENT_08_SCITRIG, GEVENT_08_SCILEVEL, GEVENT_08_SMISCIEN, GEVENT_08_SCIS0EN, GEVENT_08_SCIMAP, GEVENT_08_SMITRIG, GEVENT_08_SMICONTROL},
-	{GEVENT_09_EVENTENABLE, GEVENT_09_SCITRIG, GEVENT_09_SCILEVEL, GEVENT_09_SMISCIEN, GEVENT_09_SCIS0EN, GEVENT_09_SCIMAP, GEVENT_09_SMITRIG, GEVENT_09_SMICONTROL},
-	{GEVENT_10_EVENTENABLE, GEVENT_10_SCITRIG, GEVENT_10_SCILEVEL, GEVENT_10_SMISCIEN, GEVENT_10_SCIS0EN, GEVENT_10_SCIMAP, GEVENT_10_SMITRIG, GEVENT_10_SMICONTROL},
-	{GEVENT_11_EVENTENABLE, GEVENT_11_SCITRIG, GEVENT_11_SCILEVEL, GEVENT_11_SMISCIEN, GEVENT_11_SCIS0EN, GEVENT_11_SCIMAP, GEVENT_11_SMITRIG, GEVENT_11_SMICONTROL},
-	{GEVENT_12_EVENTENABLE, GEVENT_12_SCITRIG, GEVENT_12_SCILEVEL, GEVENT_12_SMISCIEN, GEVENT_12_SCIS0EN, GEVENT_12_SCIMAP, GEVENT_12_SMITRIG, GEVENT_12_SMICONTROL},
-	{GEVENT_13_EVENTENABLE, GEVENT_13_SCITRIG, GEVENT_13_SCILEVEL, GEVENT_13_SMISCIEN, GEVENT_13_SCIS0EN, GEVENT_13_SCIMAP, GEVENT_13_SMITRIG, GEVENT_13_SMICONTROL},
-	{GEVENT_14_EVENTENABLE, GEVENT_14_SCITRIG, GEVENT_14_SCILEVEL, GEVENT_14_SMISCIEN, GEVENT_14_SCIS0EN, GEVENT_14_SCIMAP, GEVENT_14_SMITRIG, GEVENT_14_SMICONTROL},
-	{GEVENT_15_EVENTENABLE, GEVENT_15_SCITRIG, GEVENT_15_SCILEVEL, GEVENT_15_SMISCIEN, GEVENT_15_SCIS0EN, GEVENT_15_SCIMAP, GEVENT_15_SMITRIG, GEVENT_15_SMICONTROL},
-	{GEVENT_16_EVENTENABLE, GEVENT_16_SCITRIG, GEVENT_16_SCILEVEL, GEVENT_16_SMISCIEN, GEVENT_16_SCIS0EN, GEVENT_16_SCIMAP, GEVENT_16_SMITRIG, GEVENT_16_SMICONTROL},
-	{GEVENT_17_EVENTENABLE, GEVENT_17_SCITRIG, GEVENT_17_SCILEVEL, GEVENT_17_SMISCIEN, GEVENT_17_SCIS0EN, GEVENT_17_SCIMAP, GEVENT_17_SMITRIG, GEVENT_17_SMICONTROL},
-	{GEVENT_18_EVENTENABLE, GEVENT_18_SCITRIG, GEVENT_18_SCILEVEL, GEVENT_18_SMISCIEN, GEVENT_18_SCIS0EN, GEVENT_18_SCIMAP, GEVENT_18_SMITRIG, GEVENT_18_SMICONTROL},
-	{GEVENT_19_EVENTENABLE, GEVENT_19_SCITRIG, GEVENT_19_SCILEVEL, GEVENT_19_SMISCIEN, GEVENT_19_SCIS0EN, GEVENT_19_SCIMAP, GEVENT_19_SMITRIG, GEVENT_19_SMICONTROL},
-	{GEVENT_20_EVENTENABLE, GEVENT_20_SCITRIG, GEVENT_20_SCILEVEL, GEVENT_20_SMISCIEN, GEVENT_20_SCIS0EN, GEVENT_20_SCIMAP, GEVENT_20_SMITRIG, GEVENT_20_SMICONTROL},
-	{GEVENT_21_EVENTENABLE, GEVENT_21_SCITRIG, GEVENT_21_SCILEVEL, GEVENT_21_SMISCIEN, GEVENT_21_SCIS0EN, GEVENT_21_SCIMAP, GEVENT_21_SMITRIG, GEVENT_21_SMICONTROL},
-	{GEVENT_22_EVENTENABLE, GEVENT_22_SCITRIG, GEVENT_22_SCILEVEL, GEVENT_22_SMISCIEN, GEVENT_22_SCIS0EN, GEVENT_22_SCIMAP, GEVENT_22_SMITRIG, GEVENT_22_SMICONTROL},
-	{GEVENT_23_EVENTENABLE, GEVENT_23_SCITRIG, GEVENT_23_SCILEVEL, GEVENT_23_SMISCIEN, GEVENT_23_SCIS0EN, GEVENT_23_SCIMAP, GEVENT_23_SMITRIG, GEVENT_23_SMICONTROL},
-};
-
-#endif
diff --git a/src/mainboard/amd/dinar/irq_tables.c b/src/mainboard/amd/dinar/irq_tables.c
deleted file mode 100644
index 6ca70dea4c..0000000000
--- a/src/mainboard/amd/dinar/irq_tables.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr += 15;
-	addr &= ~15;
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
-	return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c
deleted file mode 100644
index ecdb0db4b1..0000000000
--- a/src/mainboard/amd/dinar/mainboard.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-
-#include <NbPlatform.h>
-
-//#define SMBUS_IO_BASE 0x6000
-
-void set_pcie_reset(void *nbconfig);
-void set_pcie_dereset(void *nbconfig);
-
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void *nbconfig)
-{
-}
-
-/**
- * Mainboard specific RD890 CIMx callback
- * Release Resets to PCIe Links
- * SR5690 PCIE_RESET_GPIO1,2,3,4 to reset pcie
- */
-void set_pcie_dereset(void *nbconfig)
-{
-	//u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
-	u32 i;
-	u32 val;
-	u32 nb_addr;
-
-	val = 0x00000007UL;
-	AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig;
-	for (i = 0; i < MAX_NB_COUNT; i ++) {
-		nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX;
-		LibNbPciIndexRMW(nb_addr,
-				NB_HTIU_REGA8,
-				AccessS3SaveWidth32,
-				~val,
-				val,
-				&(pConfig->Northbridges[i]));
-	}
-}
-
-
-/*************************************************
- * enable the dedicated function in dinar board.
- *************************************************/
-static void mainboard_enable(device_t dev)
-{
-	printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev);
-}
-
-struct chip_operations mainboard_ops = {
-		.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c
deleted file mode 100644
index b5df41ea49..0000000000
--- a/src/mainboard/amd/dinar/mptable.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-	u32 apicid_sb700;
-	u32 apicid_rd890;
-	device_t dev;
-	u8 *dword;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/*
-	 * AGESA v5 Apply apic enumeration rules
-	 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
-	 * put the local-APICs at m..z
-	 * For systems with < 16 APICs, put the Local-APICs at 0..n and
-	 * put the IO-APICs at (n + 1)..z
-	 */
-	if (CONFIG_MAX_CPUS >= 16)
-		apicid_sb700 = 0x0;
-	else
-		apicid_sb700 = CONFIG_MAX_CPUS + 1;
-	apicid_rd890 = apicid_sb700 + 1;
-
-	dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	if (dev) {
-		/* Set sb700 IOAPIC ID */
-		dword = (u8 *)(uintptr_t)(pci_read_config32(dev, 0x74) & 0xfffffff0);
-		smp_write_ioapic(mc, apicid_sb700, 0x20, dword);
-
-		/*
-		 * 00:12.0: PROG SATA : INT F
-		 * 00:13.0: INTA USB_0
-		 * 00:13.1: INTB USB_1
-		 * 00:13.2: INTC USB_2
-		 * 00:13.3: INTD USB_3
-		 * 00:13.4: INTC USB_4
-		 * 00:13.5: INTD USB2
-		 * 00:14.1: INTA IDE
-		 * 00:14.2: Prog HDA : INT E
-		 * 00:14.5: INTB ACI
-		 * 00:14.6: INTB MCI
-		 */
-
-		/* Set RS5650 IOAPIC ID */
-		dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-		if (dev) {
-			pci_write_config32(dev, 0xF8, 0x1);
-			dword = (u8 *)(uintptr_t)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
-			smp_write_ioapic(mc, apicid_rd890, 0x20, dword);
-		}
-
-	}
-
-	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
-	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
-
-	/* PCI interrupts are level triggered, and are
-	 * associated with a specific bus/device/function tuple.
-	 */
-#define PCI_INT(bus, dev, int_sign, pin) \
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb700, (pin))
-
-	/* SMBUS */
-	//PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0
-
-	/* HD Audio */
-	PCI_INT(0x0, 0x14, 0x2, 0x10);
-
-	/* USB */
-	/* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */
-	/* EHCI hard-wired to 02h, corresponding to using INTB# */
-	/* USB1 */
-	PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */
-	PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */
-	PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */
-
-	/* USB2 */
-	PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */
-	PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */
-	PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */
-
-	/* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */
-	PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */
-
-	/* SATA */
-	PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
-
-	/* PCI slots */
-	dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-	if (dev && dev->enabled) {
-		u8 bus_pci = dev->link_list->secondary;
-
-		/* PCI_SLOT 0. */
-		PCI_INT(bus_pci, 0x5, 0x0, 0x14);
-		PCI_INT(bus_pci, 0x5, 0x1, 0x15);
-		PCI_INT(bus_pci, 0x5, 0x2, 0x16);
-		PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
-		/* PCI_SLOT 1. */
-		PCI_INT(bus_pci, 0x6, 0x0, 0x15);
-		PCI_INT(bus_pci, 0x6, 0x1, 0x16);
-		PCI_INT(bus_pci, 0x6, 0x2, 0x17);
-		PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
-		/* PCI_SLOT 2. */
-		PCI_INT(bus_pci, 0x7, 0x0, 0x16);
-		PCI_INT(bus_pci, 0x7, 0x1, 0x17);
-		PCI_INT(bus_pci, 0x7, 0x2, 0x14);
-		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
-	}
-
-	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
-	IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/dinar/platform_cfg.h b/src/mainboard/amd/dinar/platform_cfg.h
deleted file mode 100644
index f10e4d7ad0..0000000000
--- a/src/mainboard/amd/dinar/platform_cfg.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-
-/* northbridge customize options */
-/**
- * Max number of northbridges in the system
- */
-#define MAX_NB_COUNT		1 //TODO: only 1 NB tested
-
-/**
- *  Enable check for PCIe endpoint to be ready for PCI enumeration.
- *
- */
-//#define EPREADY_WORKAROUND_DISABLED
-
-/**
- *  Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table.
- *
- */
-#define IOMMU_SUPPORT_DISABLE //TODO: enable it
-
-/**
- *  Disable server PCIe hotplug support.
- */
-
-//#define HOTPLUG_SUPPORT_DISABLED
-
-/**
- *  Disable support for device number remapping for PCIe portsserver PCIe hotplug support.
- */
-
-//#define DEVICE_REMAP_DISABLE
-
-#endif //_PLATFORM_CFG_H_
diff --git a/src/mainboard/amd/dinar/rd890_cfg.c b/src/mainboard/amd/dinar/rd890_cfg.c
deleted file mode 100644
index 54592009f5..0000000000
--- a/src/mainboard/amd/dinar/rd890_cfg.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "NbPlatform.h"
-#include "rd890_cfg.h"
-#include "northbridge/amd/cimx/rd890/chip.h"
-#include "nbInitializer.h"
-#include <string.h>
-#include <arch/ioapic.h>
-
-#ifndef __PRE_RAM__
-#include <device/device.h>
-extern void set_pcie_reset(void *config);
-extern void set_pcie_dereset(void *config);
-
-/**
- * Platform dependent configuration at ramstage
- */
-static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr)
-{
-	u16 i;
-	PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig;
-	//AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr);
-	struct northbridge_amd_cimx_rd890_config *rd890_info = NULL;
-	DEFAULT_PLATFORM_CONFIG(platform_config);
-
-	/* update the platform depentent configuration by devicetree */
-	rd890_info  = nb_dev->chip_info;
-	platform_config.PortEnableMap = rd890_info->port_enable;
-	if (rd890_info->gpp1_configuration == 0) {
-		platform_config.Gpp1Config = GFX_CONFIG_AAAA;
-	} else if (rd890_info->gpp1_configuration == 1) {
-		platform_config.Gpp1Config = GFX_CONFIG_AABB;
-	}
-	if (rd890_info->gpp2_configuration == 0) {
-		platform_config.Gpp2Config = GFX_CONFIG_AAAA;
-	} else if (rd890_info->gpp2_configuration == 1) {
-		platform_config.Gpp2Config = GFX_CONFIG_AABB;
-	}
-	platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration;
-
-	if (platform_config.Gpp1Config != 0) {
-		pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config;
-	}
-	if (platform_config.Gpp2Config != 0) {
-		pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config;
-	}
-	if (platform_config.Gpp3aConfig != 0) {
-		pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig;
-	}
-
-	pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20);
-	for (i = 0; i <= MAX_CORE_ID; i++) {
-		NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF;
-		NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF;
-	}
-	for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
-		NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2;
-	}
-
-	for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
-		if ((platform_config.PortEnableMap & (1 << i)) != 0) {
-			pPcieConfig->PortConfiguration[i].PortPresent = ON;
-			if ((platform_config.PortGen1Map & (1 << i)) != 0) {
-				pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1;
-			}
-			if ((platform_config.PortHotplugMap & (1 << i)) != 0) {
-				u16 j;
-				pPcieConfig->PortConfiguration[i].PortHotplug = ON; /* Enable Hotplug */
-				/* Set Hotplug descriptor info */
-				for (j = 0; j < 8; j++) {
-					u32 PortDescriptor;
-					PortDescriptor = platform_config.PortHotplugDescriptors[j];
-					if ((PortDescriptor & 0xF) == j) {
-						pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap  = (PortDescriptor >> 4)  & 3;
-						pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6)  & 1;
-						break;
-					}
-				}
-			}
-		}
-	}
-}
-#endif // __PRE_RAM__
-
-/**
- * @brief Entry point of Northbridge CIMx callout/CallBack
- *
- * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr);
- *
- * @param[in] func     Northbridge CIMx CallBackId
- * @param[in] data     Northbridge Input Data.
- * @param[in] *config  Northbridge configuration structure pointer.
- *
- */
-static u32 rd890_callout_entry(u32 func, uintptr_t data, void *config)
-{
-	u32 ret = 0;
-#ifndef __PRE_RAM__
-	device_t nb_dev = (device_t)data;
-#endif
-	AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config;
-
-	switch (func) {
-		case PHCB_AmdPortTrainingCompleted:
-			break;
-
-		case PHCB_AmdPortResetDeassert:
-#ifndef __PRE_RAM__
-			set_pcie_dereset(config);
-#endif
-			break;
-
-		case PHCB_AmdPortResetAssert:
-#ifndef __PRE_RAM__
-			set_pcie_reset(config);
-#endif
-			break;
-
-		case PHCB_AmdPortResetSupported:
-			break;
-		case PHCB_AmdGeneratePciReset:
-			break;
-		case PHCB_AmdGetExclusionTable:
-			break;
-		case PHCB_AmdAllocateBuffer:
-			break;
-		case PHCB_AmdUpdateApicInterruptMapping:
-			break;
-		case PHCB_AmdFreeBuffer:
-			break;
-		case PHCB_AmdLocateBuffer:
-			break;
-		case PHCB_AmdReportEvent:
-			break;
-		case PHCB_AmdPcieAsmpInfo:
-			break;
-
-		case CB_AmdSetNbPorConfig:
-			break;
-		case CB_AmdSetHtConfig:
-			/*TODO: different HT path and deempasis for each NB */
-			nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES;
-
-			break;
-		case CB_AmdSetPcieEarlyConfig:
-#ifndef __PRE_RAM__
-			nb_platform_config(nb_dev, nbConfigPtr);
-#endif
-			break;
-
-		case CB_AmdSetEarlyPostConfig:
-			break;
-
-		case CB_AmdSetMidPostConfig:
-			nbConfigPtr->pNbConfig->IoApicBaseAddress = RD890_IOAPIC_ADDR;
-#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu
-			/* SBIOS must alloc 16K memory for IOMMU MMIO */
-			UINT32  MmcfgBarAddress; //using default IOmmuBaseAddress
-			LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C,
-					AccessWidth32,
-					&MmcfgBarAddress,
-					nbConfigPtr);
-			MmcfgBarAddress &= ~0xf;
-			if (MmcfgBarAddress != 0) {
-				nbConfigPtr->IommuBaseAddress = MmcfgBarAddress;
-			}
-			nbConfigPtr->IommuBaseAddress = 0; //disable iommu
-#endif
-			break;
-
-		case CB_AmdSetLatePostConfig:
-			break;
-
-		case CB_AmdSetRecoveryConfig:
-			break;
-	}
-
-	return ret;
-}
-
-
-/**
- * @brief North Bridge CIMx configuration
- *
- * should be called before exeucte CIMx function.
- * this function will be called in romstage and ramstage.
- */
-void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig)
-{
-	u16 i = 0;
-	PCI_ADDR PciAddress;
-	u32 val, sbNode, sbLink;
-
-	if (!pConfig) {
-		return;
-	}
-
-	memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK));
-	for (i = 0; i < MAX_NB_COUNT; i++) {
-		pConfig->Northbridges[i].pNbConfig	= &nbConfig[i];
-		pConfig->Northbridges[i].pHtConfig	= &htConfig[i];
-		pConfig->Northbridges[i].pPcieConfig	= &pcieConfig[i];
-		pConfig->Northbridges[i].ConfigPtr	= &pConfig;
-	}
-
-	/* Initialize all NB structures */
-	AmdInitializer(pConfig);
-
-	pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
-	pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
-	pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;
-
-	/*
-	 * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform.
-	 * Always 0:0:0 on single NB platform.
-	 */
-	pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
-
-	/* Set HT path to NB by SbNode and SbLink */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
-	LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
-	sbNode = (val >> 8) & 0x07;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
-	LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
-	sbLink = (val >> 8) & 0x07; //assum ganged
-	pConfig->Northbridges[0].NbHtPath.NodeID = sbNode;
-	pConfig->Northbridges[0].NbHtPath.LinkID = sbLink;
-	//TODO: other NBs
-
-#ifndef __PRE_RAM__
-	/* If temporrary MMIO enable set up CPU MMIO */
-	for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) {
-		UINT32  MmioBase;
-		UINT32  LinkId;
-		UINT32  SubLinkId;
-		MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress;
-		if (MmioBase != 0) {
-			LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf;
-			SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0;
-			/* Set Limit */
-			LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84),
-					AccessWidth32,
-					0x0,
-					((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6),
-					&(pConfig->Northbridges[i]));
-			/* Set Base */
-			LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80),
-					AccessWidth32,
-					0x0,
-					(MmioBase << 12) | 0x3,
-					&(pConfig->Northbridges[i]));
-		}
-	}
-#endif
-}
diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h
deleted file mode 100644
index 794c005680..0000000000
--- a/src/mainboard/amd/dinar/rd890_cfg.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef  _RD890_CFG_H_
-#define _RD890_CFG_H_
-
-#include "NbPlatform.h"
-
-#define RD890_IOAPIC_ADDR 0xC8000000
-/* platform dependent configuration default value */
-
-/**
- * Path from CPU to NB
- * [0..7]   - Node  (0..8)
- * [8..11]  - Link  (0..3)
- * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
- */
-#ifndef DEFAULT_HT_PATH
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
-#define DEFAULT_HT_PATH		{0x0, 0x1}
-#else /* FAMILY10 */
-#define DEFAULT_HT_PATH		{0x0, 0x3}
-#endif
-#endif
-
-/**
- * Bitmap of enabled ports on NB #0/1/2/3
- * Bit[0] - Reserved
- * Bit[1] - Reserved
- * Bit[2] - Enable PCIe port 2
- * Bit[3] - Enable PCIe port 3
- * Bit[4] - Enable PCIe port 4
- * Bit[5] - Enable PCIe port 5
- * Bit[6] - Enable PCIe port 2
- * Bit[7] - Enable PCIe port 7
- * Bit[8] - Reserved
- * Bit[9] - Enable PCIe port 9
- * Bit[10]- Enable PCIe port 10
- * Bit[11]- Enable PCIe port 11
- * Bit[12]- Enable PCIe port 12
- * Bit[13]- Enable PCIe port 13
- * Example:
- *  port_enable = 0x14
- *  Port 2 and 4 enabled for training/initialization
- */
-#ifndef DEFAULT_PORT_ENABLE_MAP
-#define DEFAULT_PORT_ENABLE_MAP		0x0014
-#endif
-
-/**
- * Bitmap of ports that have slot or onboard device connected.
- * Example force PCIe Gen1 supporton port 2 and 4  (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4)
- * define DEFAULT_PORT_FORCE_GEN1        0x604
- */
-#ifndef DEFAULT_PORT_FORCE_GEN1
-#define DEFAULT_PORT_FORCE_GEN1		0x0
-#endif
-
-/**
- * Bitmap of ports that have server hotplug support
- */
-#ifndef DEFAULT_HOTPLUG_SUPPORT
-#define DEFAULT_HOTPLUG_SUPPORT		0x0
-#endif
-
-#ifndef DEFAULT_HOTPLUG_DESCRIPTOR
-#define DEFAULT_HOTPLUG_DESCRIPTOR		{0, 0, 0, 0, 0, 0, 0, 0}
-#endif
-
-#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS
-#define DEFAULT_TEMPMMIO_BASE_ADDRESS		0xD0000000
-#endif
-
-/**
- * Default GPP1 core configuraton on NB #0/1/2/3.
- *  2  x8 slot, GFX_CONFIG_AABB
- *  1 x16 slot, GFX_CONFIG_AAAA
- */
-#ifndef DEFAULT_GPP1_CONFIG
-#define DEFAULT_GPP1_CONFIG		GFX_CONFIG_AABB
-#endif
-
-/**
- * Default GPP2 core configuraton on NB #0/1/2/3.
- *  2  x8 slot, GFX_CONFIG_AABB
- *  1 x16 slot, GFX_CONFIG_AAAA
- */
-#ifndef DEFAULT_GPP2_CONFIG
-#define DEFAULT_GPP2_CONFIG		GFX_CONFIG_AABB
-#endif
-
-/**
- * Default GPP3a core configuraton on NB #0/1/2/3.
- * 4:2:0:0:0:0   - GPP_CONFIG_GPP420000, 0x1
- * 4:1:1:0:0:0   - GPP_CONFIG_GPP411000, 0x2
- * 2:2:2:0:0:0   - GPP_CONFIG_GPP222000, 0x3
- * 2:2:1:1:0:0   - GPP_CONFIG_GPP221100, 0x4
- * 2:1:1:1:1:0   - GPP_CONFIG_GPP211110, 0x5
- * 1:1:1:1:1:1   - GPP_CONFIG_GPP111111, 0x6
- */
-#ifndef DEFAULT_GPP3A_CONFIG
-#define DEFAULT_GPP3A_CONFIG		GPP_CONFIG_GPP111111
-#endif
-
-
-/**
- * Default HT Transmitter de-emphasis setting
- */
-#ifndef DEFAULT_HT_DEEMPASIES
-#define DEFAULT_HT_DEEMPASIES		0x3
-#endif
-
-/**
- * Default APIC nterrupt base for IOAPIC
- */
-#ifndef DEFAULT_APIC_INTERRUPT_BASE
-#define DEFAULT_APIC_INTERRUPT_BASE	24
-#endif
-
-
-#define DEFAULT_PLATFORM_CONFIG(name) \
-	NB_PLATFORM_CONFIG name = { \
-		DEFAULT_PORT_ENABLE_MAP, \
-		DEFAULT_PORT_FORCE_GEN1, \
-		DEFAULT_HOTPLUG_SUPPORT, \
-		DEFAULT_HOTPLUG_DESCRIPTOR, \
-		DEFAULT_TEMPMMIO_BASE_ADDRESS, \
-		DEFAULT_GPP1_CONFIG, \
-		DEFAULT_GPP2_CONFIG, \
-		DEFAULT_GPP3A_CONFIG, \
-		DEFAULT_HT_DEEMPASIES, \
-		/*DEFAULT_HT_PATH,*/ \
-		DEFAULT_APIC_INTERRUPT_BASE, \
-	}
-
-/**
- * Platform configuration
- */
-typedef struct {
-	UINT16  PortEnableMap;            ///< Bitmap of enabled ports
-	UINT16  PortGen1Map;              ///< Bitmap of ports to disable Gen2
-	UINT16  PortHotplugMap;           ///< Bitmap of ports support hotplug
-	UINT8   PortHotplugDescriptors[8];///< Ports Hotplug descriptors
-	UINT32  TemporaryMmio;            ///< Temporary MMIO
-	UINT32  Gpp1Config;               ///< Default PCIe GFX core configuration
-	UINT32  Gpp2Config;               ///< Default PCIe GPP2 core configuration
-	UINT32  Gpp3aConfig;              ///< Default PCIe GPP3a core configuration
-	UINT8   NbTransmitterDeemphasis;  ///< HT transmitter de-emphasis level
-	//	HT_PATH NbHtPath;                 ///< HT path to NB
-	UINT8   GlobalApicInterruptBase;  ///< Global APIC interrupt base that is used in MADT table for IO APIC.
-} NB_PLATFORM_CONFIG;
-
-/**
- * Bridge CIMx configuration
- */
-void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig);
-
-#endif //_RD890_CFG_H_
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
deleted file mode 100644
index f81a57df40..0000000000
--- a/src/mainboard/amd/dinar/romstage.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/cpu.h>
-#include <arch/stages.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <commonlib/loglevel.h>
-#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <cpu/x86/bist.h>
-#include <superio/smsc/sch4037/sch4037.h>
-#include <superio/smsc/sio1036/sio1036.h>
-#include <cpu/x86/lapic.h>
-#include "nb_cimx.h"
-#include <sb_cimx.h>
-
-#define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	u32 val;
-
-	/* Must come first to enable PCI MMCONF. */
-	amd_initmmio();
-
-	if (!cpu_init_detectedx && boot_cpu()) {
-
-		post_code(0x30);
-
-		sch4037_early_init(0x2e);
-
-		sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
-		post_code(0x31);
-		console_init();
-
-		/*
-		 * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
-		 * Disable all Pcie Bridges to work around It.
-		 */
-		sr56x0_rd890_disable_pcie_bridge();
-
-	}
-
-	/* Halt if there was a built in self test failure */
-	post_code(0x33);
-	report_bist_failure(bist);
-
-	// Load MPB
-	val = cpuid_eax(1);
-	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
-	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
-	if(boot_cpu()) {
-		post_code(0x34);
-		sb_Poweron_Init();
-	}
-
-	post_code(0x35);
-	agesawrapper_amdinitreset();
-
-	post_code(0x36);
-	agesawrapper_amdinitearly();
-
-	post_code(0x37);
-	nb_Poweron_Init();
-	post_code(0x38);
-	nb_Ht_Init();
-
-
-	post_code(0x39);
-	agesawrapper_amdinitpost();
-
-	post_code(0x40);
-	agesawrapper_amdinitenv();
-
-
-	post_code(0x43);
-	printk(BIOS_DEBUG, "Disabling cache as RAM ");
-	disable_cache_as_ram();
-	printk(BIOS_DEBUG, "done\n");
-
-	post_code(0x44);
-	copy_and_run();
-
-	post_code(0x45);  // Should never see this post code.
-}
diff --git a/src/mainboard/amd/dinar/sb700_cfg.c b/src/mainboard/amd/dinar/sb700_cfg.c
deleted file mode 100644
index 797bed8a45..0000000000
--- a/src/mainboard/amd/dinar/sb700_cfg.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#include <string.h>
-#include <console/console.h>    /* printk */
-#include "Platform.h"
-#include "sb700_cfg.h"
-
-
-/**
- * @brief South Bridge CIMx configuration
- *
- * should be called before exeucte CIMx function.
- * this function will be called in romstage and ramstage.
- */
-void sb700_cimx_config(AMDSBCFG *sb_config)
-{
-	if (!sb_config) {
-		printk(BIOS_DEBUG, "SB700 - Cfg.c - %s - No sb_config.\n", __func__);
-		return;
-	}
-	printk(BIOS_DEBUG, "SB700 - Cfg.c - %s - Start.\n", __func__);
-	memset(sb_config, 0, sizeof(AMDSBCFG));
-
-	/* SB_POWERON_INIT */
-	sb_config->StdHeader.Func = SB_POWERON_INIT;
-
-	/* header */
-	sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS;
-
-	/* static Build Parameters */
-	sb_config->BuildParameters.BiosSize = BIOS_SIZE;
-	sb_config->BuildParameters.LegacyFree = LEGACY_FREE;
-	sb_config->BuildParameters.EcKbd = 0;
-	sb_config->BuildParameters.EcChannel0 = 0;
-	sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS;
-	sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS;
-	sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS;
-	sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS;
-	sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS;
-
-	sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS;
-	sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS;
-	sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS;
-	sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS;
-	sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS;
-	sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT;
-	sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS;
-
-	sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID;
-	sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID;
-	sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID;
-	sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID;
-	sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID;
-	sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID;
-	sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID;
-	sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID;
-	sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID;
-	sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID;
-	sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID;
-	sb_config->BuildParameters.SmbusSsid = SMBUS_SSID;
-	sb_config->BuildParameters.IdeSsid = IDE_SSID;
-	sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID;
-	sb_config->BuildParameters.LpcSsid = LPC_SSID;
-
-	sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS;
-
-	/* General */
-	sb_config->Spi33Mhz = 1;
-	sb_config->SpreadSpectrum = 0;
-	sb_config->PciClk5 = 0;
-	sb_config->PciClks = 0x1F;
-	sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood
-	sb_config->TimerClockSource = 2;  // Auto
-	sb_config->S3Resume = 0;
-	sb_config->RebootRequired = 0;
-
-	/* HPET */
-	sb_config->HpetTimer = HPET_TIMER;
-
-	/* USB */
-	sb_config->UsbIntClock = 0;     // Use external clock
-	sb_config->Usb1Ohci0 = 1; //0:disable  1:enable Bus 0 Dev 18 Func0
-	sb_config->Usb1Ohci1 = 1; //0:disable  1:enable Bus 0 Dev 18 Func1
-	sb_config->Usb1Ehci  = 1; //0:disable  1:enable Bus 0 Dev 18 Func2
-	sb_config->Usb2Ohci0 = 1; //0:disable  1:enable Bus 0 Dev 19 Func0
-	sb_config->Usb2Ohci1 = 1; //0:disable  1:enable Bus 0 Dev 19 Func1
-	sb_config->Usb2Ehci  = 1; //0:disable  1:enable Bus 0 Dev 19 Func2
-	sb_config->Usb3Ohci  = 1; //0:disable  1:enable Bus 0 Dev 20 Func5
-	sb_config->UsbOhciLegacyEmulation = 1; //0:Enable  1:Disable
-
-	sb_config->AcpiS1Supported = 1;
-
-	/* SATA */
-	sb_config->SataController = 1;
-	sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci
-	sb_config->SataSmbus = 0;
-	sb_config->SataAggrLinkPmCap = 1;
-	sb_config->SataPortMultCap = 1;
-	sb_config->SataClkAutoOff = 1;
-	sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
-	//TODO: set to secondary not take effect.
-	sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled
-	sb_config->SataEspPort = 0;
-	sb_config->SataClkAutoOffAhciMode = 1;
-	sb_config->SataHpcpButNonESP = 0;
-	sb_config->SataHideUnusedPort = 0;
-
-	/* Azalia HDA */
-	sb_config->AzaliaController = AZALIA_CONTROLLER;
-	sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG;
-	sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN_0;
-	sb_config->AzaliaSdin1 = AZALIA_SDIN_PIN_1;
-	sb_config->AzaliaSdin2 = AZALIA_SDIN_PIN_2;
-	sb_config->AzaliaSdin3 = AZALIA_SDIN_PIN_3;
-	sb_config->pAzaliaOemCodecTablePtr = NULL;
-
-#ifndef __PRE_RAM__
-	/* ramstage cimx config here */
-	if (!sb_config->StdHeader.pCallBack) {
-		sb_config->StdHeader.pCallBack = (CIM_HOOK_ENTRY)&sb700_callout_entry;
-	}
-
-	//sb_config->
-#endif //!__PRE_RAM__
-	printk(BIOS_DEBUG, "SB700 - Cfg.c - %s - End.\n", __func__);
-}
diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h
deleted file mode 100644
index 1896d11764..0000000000
--- a/src/mainboard/amd/dinar/sb700_cfg.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#ifndef _SB700_CFG_H_
-#define _SB700_CFG_H_
-
-#include <stdint.h>
-
-
-/**
- * @def BIOS_SIZE_1M
- * @def BIOS_SIZE_2M
- * @def BIOS_SIZE_4M
- * @def BIOS_SIZE_8M
- */
-#define BIOS_SIZE_1M                    0
-#define BIOS_SIZE_2M                    1
-#define BIOS_SIZE_4M                    3
-#define BIOS_SIZE_8M                    7
-
-/* In SB700, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024)
-#define BIOS_SIZE BIOS_SIZE_1M
-#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048)
-#define BIOS_SIZE BIOS_SIZE_2M
-#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096)
-#define BIOS_SIZE BIOS_SIZE_4M
-#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192)
-#define BIOS_SIZE BIOS_SIZE_8M
-#endif
-#endif
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- *  0 - Disable Spread Spectrum function
- *  1 - Enable  Spread Spectrum function
- */
-#define SPREAD_SPECTRUM                 0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- *  0 - Disable hpet
- *  1 - Enable  hpet
- */
-#define HPET_TIMER                      1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- *   0 - Disable
- *   1 - Enable
- *  Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
- *  Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
- *  Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
- *  Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
- *  Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
- *  Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
- *  Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
- */
-#define USB_CINFIG              0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- *   0 - disable
- *   1 - enable
- *  PCI SLOT 0 define at BIT0
- *  PCI SLOT 1 define at BIT1
- *  PCI SLOT 2 define at BIT2
- *  PCI SLOT 3 define at BIT3
- *  PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL                  0x1F
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#ifndef SATA_CONTROLLER
-#define SATA_CONTROLLER               1
-#endif
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#ifndef SATA_MODE
-#define SATA_MODE                     NATIVE_IDE_MODE
-#endif
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE                 0
-#define IDE_NATIVE_MODE                 1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#ifndef SATA_IDE_MODE
-#define SATA_IDE_MODE                 IDE_LEGACY_MODE
-#endif
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- *  PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK          0x00
-#define INTERNAL_CLOCK          0x01
-
-#define SATA_CLOCK_SOURCE       EXTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED     1
-
-
-/**
- * @def   AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def   AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def   AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO                     0
-#define AZALIA_DISABLE                  1
-#define AZALIA_ENABLE                   2
-
-/**
- * @brief INCHIP HDA controller
- */
-#ifndef AZALIA_CONTROLLER
-#define AZALIA_CONTROLLER             AZALIA_AUTO
-#endif
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- *  0 - disable
- *  1 - enable
- */
-#ifndef AZALIA_PIN_CONFIG
-#define AZALIA_PIN_CONFIG             1
-#endif
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- *  SDIN0 is define at BIT0 & BIT1
- *   00 - GPIO PIN
- *   01 - Reserved
- *   10 - As a Azalia SDIN pin
- *  SDIN1 is define at BIT2 & BIT3
- *  SDIN2 is define at BIT4 & BIT5
- *  SDIN3 is define at BIT6 & BIT7
- */
-#ifndef AZALIA_SDIN_PIN
-//#define AZALIA_SDIN_PIN             0xAA
-#define AZALIA_SDIN_PIN
-#define AZALIA_SDIN_PIN_0             0x2
-#define AZALIA_SDIN_PIN_1             0x2
-#define AZALIA_SDIN_PIN_2             0x2
-#define AZALIA_SDIN_PIN_3             0x0
-#endif
-
-/**
- * @def GPP_CONTROLLER
- */
-#ifndef GPP_CONTROLLER
-#define GPP_CONTROLLER                1
-#endif
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- *  GPP_CFGMODE_X4000
- *  GPP_CFGMODE_X2200
- *  GPP_CFGMODE_X2110
- *  GPP_CFGMODE_X1111
- */
-#ifndef GPP_CFGMODE
-#define GPP_CFGMODE                   GPP_CFGMODE_X1111
-#endif
-
-
-/**
- * @brief South Bridge CIMx configuration
- *
- */
-void sb700_cimx_config(AMDSBCFG *sb_cfg);
-
-/**
- * @brief Entry point of Southbridge CIMx callout
- *
- * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
- *
- * @param[in] func    Southbridge CIMx Function ID.
- * @param[in] data    Southbridge Input Data.
- * @param[in] config  Southbridge configuration structure pointer.
- *
- */
-u32 sb700_callout_entry(u32 func, u32 data, void* config);
-
-#endif //_SB700_CFG_H_
diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
deleted file mode 100644
index 3bce79b31e..0000000000
--- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "AGESA.h"
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <arch/io.h>
-
-#ifdef __PRE_RAM__
-/* These defines are used to select the appropriate socket for the SPD read
- * because this is a multi-socket design.
- */
-#define PCI_REG_GPIO_56_to_53_CNTRL      (0x52)
-#define GPIO_OUT_BIT_GPIO53              (BIT0)
-#define GPIO_OUT_BIT_GPIO54              (BIT1)
-#define GPIO_OUT_ENABLE_BIT_GPIO53       (BIT4)
-#define GPIO_OUT_ENABLE_BIT_GPIO54       (BIT5)
-
-#define GPIO_OUT_BIT_GPIO54_to_53_MASK \
-	(GPIO_OUT_BIT_GPIO54 | GPIO_OUT_BIT_GPIO53)
-#define GPIO_OUT_ENABLE_BIT_GPIO54_to_53_MASK \
-	(GPIO_OUT_ENABLE_BIT_GPIO54 | GPIO_OUT_ENABLE_BIT_GPIO53)
-
-static UINT8 select_socket(UINT8 socket_id)
-{
-	pci_devfn_t sm_dev       = PCI_DEV(0, 0x14, 0); //SMBus
-	UINT8    value        = 0;
-	UINT8    gpio56_to_53 = 0;
-
-	/* Configure GPIO54,53 to select the desired socket
-	 * GPIO54,53 control the HC4052 S1,S0
-	 *  S1 S0 true table
-	 *   0  0   channel 1 (Socket1)
-	 *   0  1   channel 2 (Socket2)
-	 *   1  0   channel 3 (Socket3)
-	 *   1  1   channel 4 (Socket4)
-	 */
-	gpio56_to_53 = pci_read_config8(sm_dev, PCI_REG_GPIO_56_to_53_CNTRL);
-	value  = gpio56_to_53 & (~GPIO_OUT_BIT_GPIO54_to_53_MASK);
-	value |= socket_id;
-	value &= (~GPIO_OUT_ENABLE_BIT_GPIO54_to_53_MASK); // 0 = Output Enabled, 1 = Tristate
-	pci_write_config8(sm_dev, PCI_REG_GPIO_56_to_53_CNTRL, value);
-
-	return gpio56_to_53;
-}
-
-static void restore_socket(UINT8 original_value)
-{
-	pci_devfn_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBus
-	pci_write_config8(sm_dev, PCI_REG_GPIO_56_to_53_CNTRL, original_value);
-}
-#endif
-
-static AGESA_STATUS board_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-#include <stdlib.h>
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			board_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_GET_IDS_INIT_DATA,		agesa_EmptyIdsInitData },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-static AGESA_STATUS board_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS Status;
-#ifdef __PRE_RAM__
-	UINT8 original_value = 0;
-
-	if (ConfigPtr == NULL)
-		return AGESA_ERROR;
-
-	original_value = select_socket(((AGESA_READ_SPD_PARAMS *)ConfigPtr)->SocketId);
-
-	Status = agesa_ReadSpd (Func, Data, ConfigPtr);
-
-	restore_socket(original_value);
-#else
-	Status = AGESA_UNSUPPORTED;
-#endif
-
-	return Status;
-}
diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig
deleted file mode 100644
index c47bd5b73c..0000000000
--- a/src/mainboard/supermicro/h8qgi/Kconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-if BOARD_SUPERMICRO_H8QGI
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select AGESA_LEGACY
-	select CPU_AMD_AGESA_FAMILY15
-	select CPU_AMD_SOCKET_G34
-	select NORTHBRIDGE_AMD_AGESA_FAMILY15
-	select NORTHBRIDGE_AMD_CIMX_RD890
-	select SOUTHBRIDGE_AMD_CIMX_SB700
-	select SUPERIO_WINBOND_W83627DHG
-	select SUPERIO_NUVOTON_WPCM450
-	select DRIVERS_I2C_W83795
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_2048
-
-config MAINBOARD_DIR
-	string
-	default supermicro/h8qgi
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "H8QGI"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 64
-
-config HW_MEM_HOLE_SIZE_AUTO_INC
-	bool
-	default n
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config VGA_BIOS
-	bool
-	default n
-
-config VGA_BIOS_ID
-	string
-	depends on VGA_BIOS
-	default "102b,0532"
-
-endif # BOARD_SUPERMICRO_H8QGI
diff --git a/src/mainboard/supermicro/h8qgi/Kconfig.name b/src/mainboard/supermicro/h8qgi/Kconfig.name
deleted file mode 100644
index 4211c5465a..0000000000
--- a/src/mainboard/supermicro/h8qgi/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_SUPERMICRO_H8QGI
-	bool "H8QGI"
diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc
deleted file mode 100644
index 0868bc22d0..0000000000
--- a/src/mainboard/supermicro/h8qgi/Makefile.inc
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-romstage-y += rd890_cfg.c
-romstage-y += sb700_cfg.c
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += rd890_cfg.c
-ramstage-y += sb700_cfg.c
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
-
-AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa
-CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx
-AGESA_ROOT ?= $(AGESA_PREFIX)/f15
-NB_CIMX_ROOT ?= $(CIMX_PREFIX)/rd890
-SB_CIMX_ROOT ?= $(CIMX_PREFIX)/sb700
diff --git a/src/mainboard/supermicro/h8qgi/OemCustomize.c b/src/mainboard/supermicro/h8qgi/OemCustomize.c
deleted file mode 100644
index c5327e6801..0000000000
--- a/src/mainboard/supermicro/h8qgi/OemCustomize.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <PlatformMemoryConfiguration.h>
-
-/*----------------------------------------------------------------------------------------
- *                        CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-//reference BKDG Table87: works
-#define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM.
-#define SEED_A 0x54
-#define SEED_B 0x4D
-#define SEED_C 0x45
-#define SEED_D 0x40
-
-#define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM.
-//4B 41 51
-
-/*
- *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *  use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
-	WRITE_LEVELING_SEED(
-			ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
-			F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
-			F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
-			F15_WL_SEED),
-
-	HW_RXEN_SEED(
-		ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
-		SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
-		SEED_A),
-	HW_RXEN_SEED(
-		ANY_SOCKET, CHANNEL_B, ALL_DIMMS,
-		SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B,
-		SEED_B),
-	HW_RXEN_SEED(
-		ANY_SOCKET, CHANNEL_C, ALL_DIMMS,
-		SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C,
-		SEED_C),
-	HW_RXEN_SEED(
-		ANY_SOCKET, CHANNEL_D, ALL_DIMMS,
-		SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
-		SEED_D),
-
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), //max 3
-	PSO_END
-};
-
-const struct OEM_HOOK OemCustomize = {
-};
diff --git a/src/mainboard/supermicro/h8qgi/OptionsIds.h b/src/mainboard/supermicro/h8qgi/OptionsIds.h
deleted file mode 100644
index 2ce76d9603..0000000000
--- a/src/mainboard/supermicro/h8qgi/OptionsIds.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDS_DEBUG_PORT
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_CONTROL_ENABLED TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-//#define IDSOPT_PERF_ANALYSIS   TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-//#undef IDSOPT_DEBUG_ENABLED
-//#define IDSOPT_DEBUG_ENABLED  FALSE
-//#undef IDSOPT_HOST_SIMNOW
-//#define IDSOPT_HOST_SIMNOW    FALSE
-//#undef IDSOPT_HOST_HDT
-//#define IDSOPT_HOST_HDT       FALSE
-//#define IDS_DEBUG_PORT    0x80
-
-#endif
diff --git a/src/mainboard/supermicro/h8qgi/acpi/routing.asl b/src/mainboard/supermicro/h8qgi/acpi/routing.asl
deleted file mode 100644
index 085c28f737..0000000000
--- a/src/mainboard/supermicro/h8qgi/acpi/routing.asl
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
-		)
-	{
-		#include "routing.asl"
-	}
-*/
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - SR5650 HT */
-		Package() { 0xFFFF, Zero, INTA, Zero },
-
-		/* Bus 0, Dev 1 - CLKCONFIG */
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
-		Package() {0x0002FFFF, 0, INTE, 0 },
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package() {0x0004FFFF, 0, INTE, 0 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-
-		/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
-
-		/* Bus 0, Dev 9 - PCIe Bridge */
-
-		/* Bus 0, Dev a - PCIe Bridge */
-
-		/* Bus 0, Dev b - PCIe Bridge */
-		Package() {0x000BFFFF, 0, INTG, 0 },
-
-		/* Bus 0, Dev c - PCIe Bridge */
-		Package() {0x000CFFFF, 0, INTG, 0 },
-
-		/* Bus 0, Dev d - PCIe Bridge for Intel 82576 Giga NIC*/
-		Package() {0x000DFFFF, 0, INTG, 0 },
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller */
-		Package() {0x0011FFFF, 0, INTG, 0 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package() {0x0012FFFF, 0, INTA, 0 },
-		Package() {0x0012FFFF, 1, INTB, 0 },
-		Package() {0x0012FFFF, 2, INTC, 0 },
-		Package() {0x0012FFFF, 3, INTD, 0 },
-
-		Package() {0x0013FFFF, 0, INTC, 0 },
-		Package() {0x0013FFFF, 1, INTD, 0 },
-		Package() {0x0013FFFF, 2, INTA, 0 },
-		Package() {0x0013FFFF, 2, INTB, 0 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - SR5650 HT */
-		Package() { 0xFFFF, Zero, Zero, 55 },
-
-		/* Bus 0, Dev 1 - CLKCONFIG */
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot (GFX0) */
-		Package() {0x0002FFFF, 0, 0, 0x34 },
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package() {0x0004FFFF, 0, 0, 0x34 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-
-		/* Bus 0, Dev 7 - PCIe Bridge */
-
-		/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
-
-		/* Bus 0, Dev 9 - PCIe Bridge */
-
-		/* Bus 0, Dev A - PCIe Bridge */
-
-		/* Bus 0, Dev B - PCIe Bridge */
-		Package() {0x000BFFFF, 0, 0, 0x36 },
-
-		/* Bus 0, Dev C - PCIe Bridge */
-		Package() {0x000CFFFF, 0, 0, 0x36 },
-
-		/* Bus 0, Dev D - PCIe Bridge For Intel 82576 Giga NIC*/
-		Package() {0x000DFFFF, 0, 0, 0x36 },
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller */
-		Package() {0x0011FFFF, 0, 0, 0x16 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package( ){0x0012FFFF, 0, 0, 16 },
-		Package() {0x0012FFFF, 1, 0, 17 },
-		Package() {0x0012FFFF, 2, 0, 18 },
-		Package() {0x0012FFFF, 3, 0, 19 },
-
-		Package() {0x0013FFFF, 0, 0, 18 },
-		Package() {0x0013FFFF, 1, 0, 19 },
-		Package() {0x0013FFFF, 2, 0, 16 },
-		Package() {0x0013FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package() {0x0014FFFF, 0, 0, 16 },
-		Package() {0x0014FFFF, 1, 0, 17 },
-		Package() {0x0014FFFF, 2, 0, 18 },
-		Package() {0x0014FFFF, 3, 0, 19 },
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 4 */
-		Package() {0x0000FFFF, 0, INTC, 0 },
-		Package() {0x0000FFFF, 1, INTD, 0 },
-		Package() {0x0000FFFF, 2, INTA, 0 },
-		Package() {0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 0x18 },
-		Package(){0x0000FFFF, 1, 0, 0x19 },
-		Package(){0x0000FFFF, 2, 0, 0x1A },
-		Package(){0x0000FFFF, 3, 0, 0x1B },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 0x2C },
-		Package(){0x0000FFFF, 1, 0, 0x2D },
-		Package(){0x0000FFFF, 2, 0, 0x2E },
-		Package(){0x0000FFFF, 3, 0, 0x2F },
-	})
-
-	Name(PSb, Package(){
-		/* PCIe slot - Hooked to PCIe slot 11 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APSb, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 0x20 },
-		Package(){0x0000FFFF, 1, 0, 0x21 },
-		Package(){0x0000FFFF, 2, 0, 0x22 },
-		Package(){0x0000FFFF, 3, 0, 0x23 },
-	})
-
-	Name(PSc, Package(){
-		/* PCIe slot - Hooked to PCIe slot 12 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APSc, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 0x24 },
-		Package(){0x0000FFFF, 1, 0, 0x25 },
-		Package(){0x0000FFFF, 2, 0, 0x26 },
-		Package(){0x0000FFFF, 3, 0, 0x27 },
-	})
-
-	Name(PSd, Package(){
-		/* PCIe slot - Hooked to PCIe slot 13 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APSd, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 0x28 },
-		Package(){0x0000FFFF, 1, 0, 0x29 },
-		Package(){0x0000FFFF, 2, 0, 0x2A },
-		Package(){0x0000FFFF, 3, 0, 0x2B },
-	})
-}
diff --git a/src/mainboard/supermicro/h8qgi/acpi/sata.asl b/src/mainboard/supermicro/h8qgi/acpi/sata.asl
deleted file mode 100644
index 9e0e535da6..0000000000
--- a/src/mainboard/supermicro/h8qgi/acpi/sata.asl
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (LGreater(P0IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (LGreater(P1IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (LGreater(P2IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (LGreater(P3IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (LGreater(\_SB.P0IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P0PR)
-		}
-
-		if (\_SB.P1PR) {
-			if (LGreater(\_SB.P1IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P1PR)
-		}
-
-		if (\_SB.P2PR) {
-			if (LGreater(\_SB.P2IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P2PR)
-		}
-
-		if (\_SB.P3PR) {
-			if (LGreater(\_SB.P3IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P3PR)
-		}
-	}
-}
diff --git a/src/mainboard/supermicro/h8qgi/acpi/usb.asl b/src/mainboard/supermicro/h8qgi/acpi/usb.asl
deleted file mode 100644
index 0f8ca9c0ab..0000000000
--- a/src/mainboard/supermicro/h8qgi/acpi/usb.asl
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
-		)
-	{
-		#include "usb.asl"
-	}
-*/
-Method(UCOC, 0) {
-	Sleep(20)
-	Store(0x13,CMTI)
-	Store(0,GPSL)
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if(LEqual(GPB0,PLC0)) {
-				Not(PLC0,PLC0)
-				Store(PLC0, \_SB.PT0D)
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (LEqual(GPB1,PLC1)) {
-				Not(PLC1,PLC1)
-				Store(PLC1, \_SB.PT1D)
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (LEqual(GPB2,PLC2)) {
-				Not(PLC2,PLC2)
-				Store(PLC2, \_SB.PT2D)
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (LEqual(GPB3,PLC3)) {
-				Not(PLC3,PLC3)
-				Store(PLC3, \_SB.PT3D)
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (LEqual(GPB4,PLC4)) {
-				Not(PLC4,PLC4)
-				Store(PLC4, \_SB.PT4D)
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (LLessEqual(UOM5,9)) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (LEqual(GPB5,PLC5)) {
-				Not(PLC5,PLC5)
-				Store(PLC5, \_SB.PT5D)
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (LEqual(GPB6,PLC6)) {
-				Not(PLC6,PLC6)
-				Store(PLC6, \_SB.PT6D)
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (LEqual(GPB7,PLC7)) {
-				Not(PLC7,PLC7)
-				Store(PLC7, \_SB.PT7D)
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (LEqual(G8IS,PLC8)) {
-				Not(PLC8,PLC8)
-				Store(PLC8, \_SB.PT8D)
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (LEqual(G9IS,0)) {
-			Store(1,\_SB.PT9D)
-			}
-		}
-	}
-}
diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c
deleted file mode 100644
index 4221992601..0000000000
--- a/src/mainboard/supermicro/h8qgi/acpi_tables.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <arch/ioapic.h>
-#include <arch/io.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	device_t dev;
-	u32 dword;
-	u32 gsi_base = 0;
-	u32 apicid_sp5100;
-	u32 apicid_sr5650;
-
-	/*
-	 * AGESA v5 Apply apic enumeration rules
-	 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
-	 * put the local-APICs at m..z
-	 * For systems with < 16 APICs, put the Local-APICs at 0..n and
-	 * put the IO-APICs at (n + 1)..z
-	 */
-	if (CONFIG_MAX_CPUS >= 16)
-		apicid_sp5100 = 0x0;
-	else
-		apicid_sp5100 = CONFIG_MAX_CPUS + 1;
-	apicid_sr5650 = apicid_sp5100 + 1;
-
-	/* create all subtables for processors */
-	current = acpi_create_madt_lapics(current);
-
-	/* Write sp5100 IOAPIC, only one */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-			apicid_sp5100,
-			IO_APIC_ADDR,
-			0
-			);
-
-	/* IOAPIC on rs5690 */
-	gsi_base += IO_APIC_INTERRUPTS;  /* SP5100 has 24 IOAPIC entries. */
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-	if (dev) {
-		pci_write_config32(dev, 0xF8, 0x1);
-		dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
-		current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				apicid_sr5650,
-				dword,
-				gsi_base
-				);
-	}
-
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current,
-			0, //BUS
-			0, //SOURCE
-			2, //gsirq
-			0  //flags
-			);
-
-	/* 0: mean bus 0--->ISA */
-	/* 0: PIC 0 */
-	/* 2: APIC 2 */
-	/* 5 mean: 0101 --> Edge-triggered, Active high */
-
-	/* create all subtables for processors */
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
-	/* 1: LINT1 connect to NMI */
-
-	return current;
-}
diff --git a/src/mainboard/supermicro/h8qgi/board_info.txt b/src/mainboard/supermicro/h8qgi/board_info.txt
deleted file mode 100644
index f50fae1f0e..0000000000
--- a/src/mainboard/supermicro/h8qgi/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Board name: H8QGI+-F
-Category: server
-Board URL: http://www.supermicro.com/Aplus/motherboard/Opteron6100/SR56x0/H8QGi_-F.cfm
-ROM package: SOIC-8
-ROM protocol: SPI
-ROM socketed: n
diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c
deleted file mode 100644
index 0b39b9cd07..0000000000
--- a/src/mainboard/supermicro/h8qgi/buildOpts.c
+++ /dev/null
@@ -1,426 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdlib.h>
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-
-/* AGESA will check the OEM configuration during preprocessing stage,
- * coreboot enable -Wundef option, so we should make sure we have all contanstand defined
- */
-/* MEMORY_BUS_SPEED */
-#define DDR400_FREQUENCY		200	///< DDR 400
-#define DDR533_FREQUENCY		266	///< DDR 533
-#define DDR667_FREQUENCY		333	///< DDR 667
-#define DDR800_FREQUENCY		400	///< DDR 800
-#define DDR1066_FREQUENCY		533	///< DDR 1066
-#define DDR1333_FREQUENCY		667	///< DDR 1333
-#define DDR1600_FREQUENCY		800	///< DDR 1600
-#define DDR1866_FREQUENCY		933	///< DDR 1866
-#define UNSUPPORTED_DDR_FREQUENCY	934	///< Highest limit of DDR frequency
-
-/* QUANDRANK_TYPE*/
-#define QUADRANK_REGISTERED		0	///< Quadrank registered DIMM
-#define QUADRANK_UNBUFFERED		1	///< Quadrank unbuffered DIMM
-
-/* USER_MEMORY_TIMING_MODE */
-#define TIMING_MODE_AUTO		0	///< Use best rate possible
-#define TIMING_MODE_LIMITED		1	///< Set user top limit
-#define TIMING_MODE_SPECIFIC		2	///< Set user specified speed
-
-/* POWER_DOWN_MODE */
-#define POWER_DOWN_BY_CHANNEL		0	///< Channel power down mode
-#define POWER_DOWN_BY_CHIP_SELECT	1	///< Chip select power down mode
-
-/* User makes option selections here
- * Comment out the items wanted to be included in the build.
- * Uncomment those items you with to REMOVE from the build.
- */
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
-//#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
-//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
-#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
-//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT      TRUE
-////#define BLDOPT_REMOVE_ACPI_PSTATES             TRUE
-////#define BLDOPT_REMOVE_SRAT                     TRUE
-////#define BLDOPT_REMOVE_SLIT                     TRUE
-//#define BLDOPT_REMOVE_WHEA                     TRUE
-//#define BLDOPT_REMOVE_DMI                      TRUE
-
-/*f15 Rev A1 ucode patch CpuF15OrMicrocodePatch0600011F */
-#define BLDOPT_REMOVE_EARLY_SAMPLES		FALSE
-
-//#define BLDOPT_REMOVE_HT_ASSIST                TRUE
-//#define BLDOPT_REMOVE_MSG_BASED_C1E            TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
-
-/* Build configuration values here.
- */
-#define BLDCFG_VRM_CURRENT_LIMIT                 120000
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD           0
-#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT          0
-#define BLDCFG_PLAT_NUM_IO_APICS                 3
-#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
-#define BLDCFG_MEM_INIT_PSTATE                   0
-#define BLDCFG_AMD_PSTATE_CAP_VALUE              0
-
-#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_SERVER
-
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1866_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
-#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
-#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_REGISTERED
-#define BLDCFG_MEMORY_RDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE              FALSE
-#define BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB          TRUE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    FALSE//TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE//TRUE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        FALSE//TRUE
-#define BLDCFG_MEMORY_POWER_DOWN                  FALSE
-#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHANNEL
-#define BLDCFG_ONLINE_SPARE                       FALSE
-#define BLDCFG_BANK_SWIZZLE                       TRUE
-#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1866_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
-#define BLDCFG_USE_BURST_MODE                     FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
-#define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
-#define BLDCFG_ECC_REDIRECTION                    FALSE
-#define BLDCFG_SCRUB_IC_RATE                      0
-#define BLDCFG_ECC_SYNC_FLOOD                     TRUE
-#define BLDCFG_ECC_SYMBOL_SIZE                    4
-
-#define BLDCFG_PCI_MMIO_BASE                    CONFIG_MMCONF_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_SIZE                    CONFIG_MMCONF_BUS_NUMBER
-
-/**
- * Enable Message Based C1e CPU feature in multi-socket systems.
- * BLDCFG_PLATFORM_C1E_OPDATA element be defined with a valid IO port value,
- * else the feature cannot be enabled.
- */
-#define BLDCFG_PLATFORM_C1E_MODE                  C1eModeMsgBased
-#define BLDCFG_PLATFORM_C1E_OPDATA                0x80//TODO
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1        0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2        0
-
-#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000
-#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    0xD0000000
-#define BLDCFG_1GB_ALIGN                          FALSE
-//#define BLDCFG_PROCESSOR_SCOPE_NAME0              'C'
-//#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
-//
-
-// Select the platform control flow mode for performance tuning.
-#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
-
-/**
- * Enable the probe filtering performance tuning feature.
- * The probe filter provides filtering of broadcast probes to
- * improve link bandwidth and performance for multi- node systems.
- *
- * This feature may interact with other performance features.
- *  TRUE  -Enable the feature (default) if supported by all processors,
- *         based on revision and presence of L3 cache.
- *         The feature is not enabled if there are no coherent HT links.
- *  FALSE -Do not enable the feature regardless of the configuration.
- */
-//TODO enable it,
-//but AGESA set PFMode = 0; //PF Disable, HW never set PFInitDone
-//hang in F10HtAssistInit() do{...} while(PFInitDone != 1)
-#define BLDCFG_USE_HT_ASSIST	FALSE
-
-/**
- * The socket and link match values are platform specific
- */
-CONST MANUAL_BUID_SWAP_LIST ROMDATA h8qgi_manual_swaplist[2] =
-{
-	{
-		/* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-
-		{ //BUID Swap List
-			{ //BUID Swaps
-				/* Each Non-coherent chain may have a list of device swaps,
-				 * Each item specify a device will be swap from its current id to a new one
-				 */
-				/* FromID 0x00 is the chain with the southbridge */
-				/* 'Move' device zero to device zero, All others are non applicable */
-				{0x00, 0x00}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-			},
-
-			{ //The ordered final BUIDs
-				/* Specify the final BUID to be zero, All others are non applicable */
-				0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-				0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-				0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-				0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-			}
-		}
-	},
-
-	/* The 2nd element in the array merely terminates the list */
-	{
-		HT_LIST_TERMINAL,
-	}
-};
-
-#define HYPERTRANSPORT_V31_SUPPORT 1
-
-#if HYPERTRANSPORT_V31_SUPPORT
-/**
- * The socket and link match values are platform specific
- *
- */
-CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8qgi_cpu2cpu_limit_list[2] =
-{
-	{
-		/* On the reference platform, these settings apply to all coherent links */
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-
-		/* Set incoming and outgoing links to 16 bit widths, and 3.2GHz frequencies */
-		HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M,
-	},
-
-	/* The 2nd element in the array merely terminates the list */
-	{
-		HT_LIST_TERMINAL,
-	}
-};
-
-CONST IO_PCB_LIMITS ROMDATA h8qgi_io_limit_list[2] =
-{
-	{
-		/* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-
-		/* Set upstream and downstream links to 16 bit widths, and limit frequencies to 3.2GHz */
-		HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, //Actually IO hub only support 2600M MAX
-	},
-
-	/* The 2nd element in the array merely terminates the list */
-	{
-		HT_LIST_TERMINAL,
-	}
-};
-#else /* HYPERTRANSPORT_V31_SUPPORT == 0 */
-CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8qgi_cpu2cpu_limit_list[2] =
-{
-	{
-		/* On the reference platform, these settings apply to all coherent links */
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-
-		/* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
-		HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
-	},
-
-	/* The 2nd element in the array merely terminates the list */
-	{
-		HT_LIST_TERMINAL,
-	}
-};
-
-CONST IO_PCB_LIMITS ROMDATA h8qgi_io_limit_list[2] =
-{
-	{
-		/* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-
-		/* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
-		HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
-	},
-
-	/* The 2nd element in the array merely terminates the list */
-	{
-		HT_LIST_TERMINAL
-	}
-};
-#endif /* HYPERTRANSPORT_V31_SUPPORT == 0 */
-
-/**
- * HyperTransport links will typically require an equalization at high frequencies.
- * This is called deemphasis.
- *
- * Deemphasis is specified as levels, for example, -3 db.
- * There are two levels for each link, its receiver deemphasis level and its DCV level,
- * which is based on the far side transmitter's deemphasis.
- * For each link, different levels may be required at each link frequency.
- *
- * Coherent connections between processors should have an entry for the port on each processor.
- * There should be one entry for the host root port of each non-coherent chain.
- *
- * AGESA initialization code does not set deemphasis on IO Devices.
- * A default is provided for internal links of MCM processors, and
- * those links will generally not need deemphasis structures.
- */
-CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA h8qgi_deemphasis_list[] =
-{
-	/* Socket, Link, LowFreq, HighFreq, Receiver Deemphasis, Dcv Deemphasis */
-
-	/* Non-coherent link deemphasis. */
-	{0, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
-	{0, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
-	{0, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
-	{0, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
-	{0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
-	{0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
-
-	{1, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
-	{1, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
-	{1, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
-	{1, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
-	{1, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
-	{1, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
-
-	{2, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
-	{2, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
-	{2, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
-	{2, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
-	{2, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
-	{2, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
-
-	{3, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
-	{3, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
-	{3, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
-	{3, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
-	{3, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
-	{3, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
-
-	/* Coherent link deemphasis. */
-	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
-	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3},
-	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus6},
-	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus6},
-	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus8},
-	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2600M, HT_FREQUENCY_MAX, DeemphasisLevelMinus11pre8, DcvLevelMinus11},
-
-	/* End of the list */
-	{
-		HT_LIST_TERMINAL
-	}
-};
-
-/**
- * For systems using socket infrastructure that permits strapping the SBI
- * address for each socket, this should be used to provide a socket ID value.
- * This is referred to as the hardware method for socket naming, and is the
- * preferred solution.
- */
-/*
- * I do NOT know howto config socket id in simnow,
- * so use this software way to make HT works in simnow,
- * real hardware do not need this Socket Map.
- *
- * A physical socket map for a 4 G34 Sockets MCM processors topology,
- * reference the mainboard schemantic in detail.
- *
- */
-CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA h8qgi_socket_map[] =
-{
-#define HT_SOCKET0	0
-#define HT_SOCKET1	1
-#define HT_SOCKET2	2
-#define HT_SOCKET3	3
-
-/**
- * 0-3 are sublink 0, 4-7 are sublink 1
- */
-#define HT_LINK0A	0
-#define HT_LINK1A	1
-#define HT_LINK2A	2
-#define HT_LINK3A	3
-#define HT_LINK0B	4
-#define HT_LINK1B	5
-#define HT_LINK2B	6
-#define HT_LINK3B	7
-
-	/* Source Socket, Link, Target Socket */
-	{HT_SOCKET0, HT_LINK0A, HT_SOCKET1},
-	{HT_SOCKET0, HT_LINK0B, HT_SOCKET3},
-	{HT_SOCKET0, HT_LINK1A, HT_SOCKET1},
-	{HT_SOCKET0, HT_LINK1B, HT_SOCKET3},
-	{HT_SOCKET0, HT_LINK3A, HT_SOCKET2},
-	{HT_SOCKET0, HT_LINK3B, HT_SOCKET2},
-
-	{HT_SOCKET1, HT_LINK0A, HT_SOCKET2},
-	{HT_SOCKET1, HT_LINK0B, HT_SOCKET3},
-	{HT_SOCKET1, HT_LINK1A, HT_SOCKET0},
-	{HT_SOCKET1, HT_LINK1B, HT_SOCKET2},
-	{HT_SOCKET1, HT_LINK3A, HT_SOCKET0},
-	{HT_SOCKET1, HT_LINK3B, HT_SOCKET3},
-
-	{HT_SOCKET2, HT_LINK0A, HT_SOCKET3},
-	{HT_SOCKET2, HT_LINK0B, HT_SOCKET0},
-	{HT_SOCKET2, HT_LINK1A, HT_SOCKET3},
-	{HT_SOCKET2, HT_LINK1B, HT_SOCKET1},
-	{HT_SOCKET2, HT_LINK3A, HT_SOCKET1},
-	{HT_SOCKET2, HT_LINK3B, HT_SOCKET0},
-
-	{HT_SOCKET3, HT_LINK0A, HT_SOCKET2},
-	{HT_SOCKET3, HT_LINK0B, HT_SOCKET1},
-	{HT_SOCKET3, HT_LINK1A, HT_SOCKET1},
-	{HT_SOCKET3, HT_LINK1B, HT_SOCKET0},
-	{HT_SOCKET3, HT_LINK3A, HT_SOCKET0},
-	{HT_SOCKET3, HT_LINK3B, HT_SOCKET2},
-};
-
-CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
-{
-	{AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E},
-	{AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E},
-	{AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_C0000,  0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_C8000,  0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_D0000,  0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_D8000,  0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_E0000,  0x1818181818181818},
-	{AMD_AP_MTRR_FIX4k_E8000,  0x1818181818181818},
-	{AMD_AP_MTRR_FIX4k_F0000,  0x1818181818181818},
-	{AMD_AP_MTRR_FIX4k_F8000,  0x1818181818181818},
-	{CPU_LIST_TERMINAL}
-};
-
-#define BLDCFG_BUID_SWAP_LIST			&h8qgi_manual_swaplist
-#define BLDCFG_HTFABRIC_LIMITS_LIST		&h8qgi_cpu2cpu_limit_list
-#define BLDCFG_HTCHAIN_LIMITS_LIST		&h8qgi_io_limit_list
-#define BLDCFG_PLATFORM_DEEMPHASIS_LIST		&h8qgi_deemphasis_list
-#define BLDCFG_AP_MTRR_SETTINGS_LIST		&h8qgi_ap_mtrr_list
-//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP	&h8qgi_socket_map
-
-
-/*  Process the options...
- * This file include MUST occur AFTER the user option selection settings
- */
-
-#include "MaranelloInstall.h"
diff --git a/src/mainboard/supermicro/h8qgi/cmos.layout b/src/mainboard/supermicro/h8qgi/cmos.layout
deleted file mode 100644
index 956aba3689..0000000000
--- a/src/mainboard/supermicro/h8qgi/cmos.layout
+++ /dev/null
@@ -1,68 +0,0 @@
-#*****************************************************************************
-#
-#  This file is part of the coreboot project.
-#
-#  Copyright (C) 2011 Advanced Micro Devices, Inc.
-#
-#  This program is free software; you can redistribute it and/or modify
-#  it under the terms of the GNU General Public License as published by
-#  the Free Software Foundation; version 2 of the License.
-#
-#  This program is distributed in the hope that it will be useful,
-#  but WITHOUT ANY WARRANTY; without even the implied warranty of
-#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-#  GNU General Public License for more details.
-#*****************************************************************************
-
-entries
-
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#392          3       r       0        unused
-395          1       e       1        hw_scrubber
-396          1       e       1        interleave_chip_selects
-397          2       e       8        max_mem_clock
-399          1       e       2        multi_core
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        iommu
-456          1       e       1        ECC_memory
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
-
-
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-8     0     400Mhz
-8     1     333Mhz
-8     2     266Mhz
-8     3     200Mhz
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb
deleted file mode 100644
index 5ba52b624a..0000000000
--- a/src/mainboard/supermicro/h8qgi/devicetree.cb
+++ /dev/null
@@ -1,222 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-chip northbridge/amd/agesa/family15/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family15
-			device lapic 0x20 on end #f15
-			#device lapic 0x10 on end #f10
-		end
-	end
-	device domain 0 on
-		subsystemid 0x15d9 0xab11 inherit #SuperMicro
-		chip northbridge/amd/agesa/family15 # CPU side of HT root complex
-			device pci 18.0 on     # Put IO-HUB at link_num 0, Instead of HT Link topology
-				chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex
-					device pci 0.0 on  end # HT Root Complex 0x9600
-					device pci 0.1 off end # CLKCONFIG
-					device pci 2.0 on  end # GPP1 Port0  x16 SLOT4, 0x5A16
-					device pci 3.0 off end # GPP1 Port1
-					device pci 4.0 off end # GPP3a Port0  x4 SAS
-					device pci 5.0 off end # GPP3a Port1
-					device pci 6.0 off end # GPP3a Port2
-					device pci 7.0 off end # GPP3a Port3
-					device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time
-					device pci 9.0 off end # GPP3a Port4  x1 NC
-					device pci a.0 off end # GPP3a Port5  x1 NC
-					device pci b.0 off end # GPP2 Port0 (Not for sr5650)
-					device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670)
-					device pci d.0 on  end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
-					register "gpp1_configuration" = "0"   # Configuration 16:0 default
-					register "gpp2_configuration" = "1"   # Configuration 8:8
-					register "gpp3a_configuration" = "2"   # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1
-					register "port_enable" = "0x2104"
-				end #northbridge/amd/cimx/rd890
-				chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus
-					device pci 11.0 on end # SATA
-					device pci 12.0 on end # USB1
-					device pci 12.1 on end # USB1
-					device pci 12.2 on end # USB1
-					device pci 13.0 on end # USB2
-					device pci 13.1 on end # USB2
-					device pci 13.2 on end # USB2
-					device pci 14.0 on end # SM
-					device pci 14.1 off end # IDE  0x439c
-					device pci 14.2 off end # HDA  0x4383, h8qgi not have codec.
-					device pci 14.3 on # LPC  0x439d
-						chip superio/winbond/w83627dhg
-							device pnp 2e.0 off #  Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off #  Parallel Port
-								io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 on  #  Com1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.3 on  #  Com2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							## though UARTs are on the NUVOTON BMC, superio only used to support PS2 KB/MS##
-							device pnp 2e.5 on #  PS/2 keyboard & mouse
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 0x01 #keyboard
-								irq 0x72 = 0x0C #mouse
-							end
-							device pnp 2e.6 off #  SPI
-							end
-							device pnp 2e.307 off #  GPIO6
-							end
-							device pnp 2e.8 off #  WDTO#, PLED
-							end
-							device pnp 2e.009 off #  GPIO2
-							end
-							device pnp 2e.109 off #  GPIO3
-							end
-							device pnp 2e.209 off #  GPIO4
-							end
-							device pnp 2e.309 off #  GPIO5
-							end
-							device pnp 2e.a off #  ACPI
-							end
-							device pnp 2e.b off # HWM
-								io 0x60 = 0x290
-							end
-							device pnp 2e.c off # PECI, SST
-							end
-						end #superio/winbond/w83627dhg
-						chip drivers/i2c/w83795
-							register "fanin_ctl1" = "0xff"			# Enable monitoring of FANIN1 - FANIN8
-							register "fanin_ctl2" = "0x00"			# Connect FANIN11 - FANIN14 to alternate functions
-							register "temp_ctl1" = "0x2a"			# Enable monitoring of DTS, VSEN12, and VSEN13
-							register "temp_ctl2" = "0x01"			# Enable monitoring of TD1/TR1
-							register "temp_dtse" = "0x03"			# Enable DTS1 and DTS2
-							register "volt_ctl1" = "0xff"			# Enable monitoring of VSEN1 - VSEN8
-							register "volt_ctl2" = "0xf7"			# Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT
-							register "temp1_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp1)
-							register "temp2_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp2)
-							register "temp3_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp3)
-							register "temp4_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp4)
-							register "temp5_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp5)
-							register "temp6_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp6)
-							register "temp1_source_select" = "0x00"		# Use TD1/TR1 as data source for Temp1
-							register "temp2_source_select" = "0x00"		# Use TD2/TR2 as data source for Temp2
-							register "temp3_source_select" = "0x00"		# Use TD3/TR3 as data source for Temp3
-							register "temp4_source_select" = "0x00"		# Use TD4/TR4 as data source for Temp4
-							register "temp5_source_select" = "0x00"		# Use TR5 as data source for Temp5
-							register "temp6_source_select" = "0x00"		# Use TR6 as data source for Temp6
-							register "tr1_critical_temperature" = "85"	# Set TD1/TR1 critical temperature to 85°C
-							register "tr1_critical_hysteresis" = "80"	# Set TD1/TR1 critical hysteresis temperature to 80°C
-							register "tr1_warning_temperature" = "70"	# Set TD1/TR1 warning temperature to 70°C
-							register "tr1_warning_hysteresis" = "65"	# Set TD1/TR1 warning hysteresis temperature to 65°C
-							register "dts_critical_temperature" = "85"	# Set DTS (CPU) critical temperature to 85°C
-							register "dts_critical_hysteresis" = "80"	# Set DTS (CPU) critical hysteresis temperature to 80°C
-							register "dts_warning_temperature" = "70"	# Set DTS (CPU) warning temperature to 70°C
-							register "dts_warning_hysteresis" = "65"	# Set DTS (CPU) warning hysteresis temperature to 65°C
-							register "temp1_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
-							register "temp2_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
-							register "temp3_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
-							register "temp4_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
-							register "temp5_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
-							register "temp6_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
-							register "temp1_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
-							register "temp2_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
-							register "temp3_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
-							register "temp4_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
-							register "temp5_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
-							register "temp6_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
-							register "fan1_nonstop" = "7"			# Set Fan 1 minimum speed
-							register "fan2_nonstop" = "7"			# Set Fan 2 minimum speed
-							register "fan3_nonstop" = "7"			# Set Fan 3 minimum speed
-							register "fan4_nonstop" = "7"			# Set Fan 4 minimum speed
-							register "fan5_nonstop" = "7"			# Set Fan 5 minimum speed
-							register "fan6_nonstop" = "7"			# Set Fan 6 minimum speed
-							register "fan7_nonstop" = "7"			# Set Fan 7 minimum speed
-							register "fan8_nonstop" = "7"			# Set Fan 8 minimum speed
-							register "default_speed" = "100"		# All fans to full speed on power up
-							register "fan1_duty" = "100"			# Fan 1 to full speed
-							register "fan2_duty" = "100"			# Fan 2 to full speed
-							register "fan3_duty" = "100"			# Fan 3 to full speed
-							register "fan4_duty" = "100"			# Fan 4 to full speed
-							register "fan5_duty" = "100"			# Fan 5 to full speed
-							register "fan6_duty" = "100"			# Fan 6 to full speed
-							register "fan7_duty" = "100"			# Fan 7 to full speed
-							register "fan8_duty" = "100"			# Fan 8 to full speed
-							register "vcore1_high_limit_mv" = "1500"	# VCORE1 (Node 0) high limit to 1.5V
-							register "vcore1_low_limit_mv" = "900"		# VCORE1 (Node 0) low limit to 0.9V
-							register "vcore2_high_limit_mv" = "1500"	# VCORE2 (Node 1) high limit to 1.5V
-							register "vcore2_low_limit_mv" = "900"		# VCORE2 (Node 1) low limit to 0.9V
-							register "vsen3_high_limit_mv" = "1600"		# VSEN1 (Node 0 RAM voltage) high limit to 1.6V
-							register "vsen3_low_limit_mv" = "1100"		# VSEN1 (Node 0 RAM voltage) low limit to 1.1V
-							register "vsen4_high_limit_mv" = "1600"		# VSEN2 (Node 1 RAM voltage) high limit to 1.6V
-							register "vsen4_low_limit_mv" = "1100"		# VSEN2 (Node 1 RAM voltage) low limit to 1.1V
-							register "vsen5_high_limit_mv" = "1250"		# VSEN5 (Node 0 HT link voltage) high limit to 1.25V
-							register "vsen5_low_limit_mv" = "1150"		# VSEN5 (Node 0 HT link voltage) low limit to 1.15V
-							register "vsen6_high_limit_mv" = "1250"		# VSEN6 (Node 1 HT link voltage) high limit to 1.25V
-							register "vsen6_low_limit_mv" = "1150"		# VSEN6 (Node 1 HT link voltage) low limit to 1.15V
-							register "vsen7_high_limit_mv" = "1150"		# VSEN7 (Northbridge core voltage) high limit to 1.15V
-							register "vsen7_low_limit_mv" = "1050"		# VSEN7 (Northbridge core voltage) low limit to 1.05V
-							register "vsen8_high_limit_mv" = "1900"		# VSEN8 (+1.8V) high limit to 1.9V
-							register "vsen8_low_limit_mv" = "1700"		# VSEN8 (+1.8V) low limit to 1.7V
-							register "vsen9_high_limit_mv" = "1250"		# VSEN9 (+1.2V) high limit to 1.25V
-							register "vsen9_low_limit_mv" = "1150"		# VSEN9 (+1.2V) low limit to 1.15V
-							register "vsen10_high_limit_mv" = "1150"	# VSEN10 (+1.1V) high limit to 1.15V
-							register "vsen10_low_limit_mv" = "1050"		# VSEN10 (+1.1V) low limit to 1.05V
-							register "vsen11_high_limit_mv" = "1625"	# VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V
-							register "vsen11_low_limit_mv" = "1500"		# VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V
-							register "vsen12_high_limit_mv" = "1083"	# VSEN12 (+12V, scaling factor ~12) high limit to 13V
-							register "vsen12_low_limit_mv" = "917"		# VSEN12 (+12V, scaling factor ~12) low limit to 11V
-							register "vsen13_high_limit_mv" = "1625"	# VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V
-							register "vsen13_low_limit_mv" = "1500"		# VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V
-							register "vdd_high_limit_mv" = "3500"		# 3VDD high limit to 3.5V
-							register "vdd_low_limit_mv" = "3100"		# 3VDD low limit to 3.1V
-							register "vsb_high_limit_mv" = "3500"		# 3VSB high limit to 3.5V
-							register "vsb_low_limit_mv" = "3100"		# 3VSB low limit to 3.1V
-							register "vbat_high_limit_mv" = "3500"		# VBAT (+3V) high limit to 3.5V
-							register "vbat_low_limit_mv" = "2500"		# VBAT (+3V) low limit to 2.5V
-							register "smbus_aux" = "0"			# Device located on primary SMBUS
-							device pnp 5e on #hwm
-							end
-						end #drivers/i2c/w83795
-					end # LPC
-					device pci 14.4 on
-						device pci 4.0 on end # onboard VGA
-					end # PCI 0x4384
-					device pci 14.5 on end # USB 3
-					register "boot_switch_sata_ide" = "0"   # 0: boot from SATA. 1: IDE
-				end # southbridge/amd/cimx/sb700
-			end # device pci 18.0
-
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end #f15
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 0
-				{ {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 1
-				{ {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 2
-				{ {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 3
-			}"
-		end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
-	end #domain
-end #northbridge/amd/agesa/family15/root_complex
diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl
deleted file mode 100644
index 036bc1b249..0000000000
--- a/src/mainboard/supermicro/h8qgi/dsdt.asl
+++ /dev/null
@@ -1,1671 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* DefinitionBlock Statement */
-DefinitionBlock (
-	"DSDT.AML",	/* Output filename */
-	"DSDT",		/* Signature */
-	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
-	"AMD   ",	/* OEMID */
-	"COREBOOT",	/* TABLE ID */
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	/* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
-
-	/* Data to be patched by the BIOS during POST */
-	/* FIXME the patching is not done yet! */
-	/* Memory related values */
-	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
-	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
-	Name(PBLN, 0x0)	/* Length of BIOS area */
-
-	Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
-	Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
-
-	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
-	/* USB overcurrent mapping pins.   */
-	Name(UOM0, 0)
-	Name(UOM1, 2)
-	Name(UOM2, 0)
-	Name(UOM3, 7)
-	Name(UOM4, 2)
-	Name(UOM5, 2)
-	Name(UOM6, 6)
-	Name(UOM7, 2)
-	Name(UOM8, 6)
-	Name(UOM9, 6)
-
-	/* Some global data */
-	Name(OSVR, 3)		/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
-	Name(OSV, Ones)	/* Assume nothing */
-	Name(PMOD, 0)	/* Default interrupt model is PIC */
-
-	/*
-	 * Processor Object
-	 *
-	 */
-	Scope (\_PR) {		/* define processor scope */
-		Processor(
-			C000,		/* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */
-			0x00,		/* Unique number for this processor */
-			0x810,		/* PBLK system I/O address !hardcoded! */
-			0x06		/* PBLKLEN for boot processor */
-			) {
-		}
-		Processor(C001, 0x01, 0x00000000, 0x00) {}
-		Processor(C002, 0x02, 0x00000000, 0x00) {}
-		Processor(C003, 0x03, 0x00000000, 0x00) {}
-		Processor(C004, 0x04, 0x00000000, 0x00) {}
-		Processor(C005, 0x05, 0x00000000, 0x00) {}
-		Processor(C006, 0x06, 0x00000000, 0x00) {}
-		Processor(C007, 0x07, 0x00000000, 0x00) {}
-		Processor(C008, 0x08, 0x00000000, 0x00) {}
-		Processor(C009, 0x09, 0x00000000, 0x00) {}
-		Processor(C00A, 0x0A, 0x00000000, 0x00) {}
-		Processor(C00B, 0x0B, 0x00000000, 0x00) {}
-		Processor(C00C, 0x0C, 0x00000000, 0x00) {}
-		Processor(C00D, 0x0D, 0x00000000, 0x00) {}
-		Processor(C00E, 0x0E, 0x00000000, 0x00) {}
-		Processor(C00F, 0x0F, 0x00000000, 0x00) {}
-		Processor(C010, 0x10, 0x00000000, 0x00) {}
-		Processor(C011, 0x11, 0x00000000, 0x00) {}
-		Processor(C012, 0x12, 0x00000000, 0x00) {}
-		Processor(C013, 0x13, 0x00000000, 0x00) {}
-		Processor(C014, 0x14, 0x00000000, 0x00) {}
-		Processor(C015, 0x15, 0x00000000, 0x00) {}
-		Processor(C016, 0x16, 0x00000000, 0x00) {}
-		Processor(C017, 0x17, 0x00000000, 0x00) {}
-		Processor(C018, 0x18, 0x00000000, 0x00) {}
-		Processor(C019, 0x19, 0x00000000, 0x00) {}
-		Processor(C01A, 0x1A, 0x00000000, 0x00) {}
-		Processor(C01B, 0x1B, 0x00000000, 0x00) {}
-		Processor(C01C, 0x1C, 0x00000000, 0x00) {}
-		Processor(C01D, 0x1D, 0x00000000, 0x00) {}
-		Processor(C01E, 0x1E, 0x00000000, 0x00) {}
-		Processor(C01F, 0x1F, 0x00000000, 0x00) {}
-		Processor(C020, 0x20, 0x00000000, 0x00) {}
-		Processor(C021, 0x21, 0x00000000, 0x00) {}
-		Processor(C022, 0x22, 0x00000000, 0x00) {}
-		Processor(C023, 0x23, 0x00000000, 0x00) {}
-		Processor(C024, 0x24, 0x00000000, 0x00) {}
-		Processor(C025, 0x25, 0x00000000, 0x00) {}
-		Processor(C026, 0x26, 0x00000000, 0x00) {}
-		Processor(C027, 0x27, 0x00000000, 0x00) {}
-		Processor(C028, 0x28, 0x00000000, 0x00) {}
-		Processor(C029, 0x29, 0x00000000, 0x00) {}
-		Processor(C02A, 0x2A, 0x00000000, 0x00) {}
-		Processor(C02B, 0x2B, 0x00000000, 0x00) {}
-		Processor(C02C, 0x2C, 0x00000000, 0x00) {}
-		Processor(C02D, 0x2D, 0x00000000, 0x00) {}
-		Processor(C02E, 0x2E, 0x00000000, 0x00) {}
-		Processor(C02F, 0x2F, 0x00000000, 0x00) {}
-		Alias (C000, CPU0)
-		Alias (C001, CPU1)
-		Alias (C002, CPU2)
-		Alias (C003, CPU3)
-		Alias (C004, CPU4)
-		Alias (C005, CPU5)
-		Alias (C006, CPU6)
-		Alias (C007, CPU7)
-		Alias (C008, CPU8)
-	} /* End _PR scope */
-
-	/* PIC IRQ mapping registers, C00h-C01h */
-	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
-		Field(PRQM, ByteAcc, NoLock, Preserve) {
-		PRQI, 0x00000008,
-		PRQD, 0x00000008,  /* Offset: 1h */
-	}
-	IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
-		PINA, 0x00000008,	/* Index 0 */
-		PINB, 0x00000008,	/* Index 1 */
-		PINC, 0x00000008,	/* Index 2 */
-		PIND, 0x00000008,	/* Index 3 */
-		AINT, 0x00000008,	/* Index 4 */
-		SINT, 0x00000008,	/* Index 5 */
-		    , 0x00000008,	/* Index 6 */
-		AAUD, 0x00000008,	/* Index 7 */
-		AMOD, 0x00000008,	/* Index 8 */
-		PINE, 0x00000008,	/* Index 9 */
-		PINF, 0x00000008,	/* Index A */
-		PING, 0x00000008,	/* Index B */
-		PINH, 0x00000008,	/* Index C */
-	}
-
-	/* PCI Error control register */
-	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
-		Field(PERC, ByteAcc, NoLock, Preserve) {
-		SENS, 0x00000001,
-		PENS, 0x00000001,
-		SENE, 0x00000001,
-		PENE, 0x00000001,
-	}
-
-	/* Client Management index/data registers */
-	OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
-		Field(CMT, ByteAcc, NoLock, Preserve) {
-		CMTI, 8,
-		/* Client Management Data register */
-		G64E, 1,
-		G64O, 1,
-		G32O, 2,
-		    , 2,
-		GPSL, 2,
-	}
-
-	/* GPM Port register */
-	OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
-		Field(GPT, ByteAcc, NoLock, Preserve) {
-		GPB0,1,
-		GPB1,1,
-		GPB2,1,
-		GPB3,1,
-		GPB4,1,
-		GPB5,1,
-		GPB6,1,
-		GPB7,1,
-	}
-
-	/* Flash ROM program enable register */
-	OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
-		Field(FRE, ByteAcc, NoLock, Preserve) {
-		    , 0x00000006,
-		FLRE, 0x00000001,
-	}
-
-	/* PM2 index/data registers */
-	OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
-		Field(PM2R, ByteAcc, NoLock, Preserve) {
-		PM2I, 0x00000008,
-		PM2D, 0x00000008,
-	}
-
-	/* Power Management I/O registers */
-	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
-		Field(PIOR, ByteAcc, NoLock, Preserve) {
-		PIOI, 0x00000008,
-		PIOD, 0x00000008,
-	}
-	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
-		Offset(0x00),	/* MiscControl */
-		, 1,
-		T1EE, 1,
-		T2EE, 1,
-		Offset(0x01),	/* MiscStatus */
-		, 1,
-		T1E, 1,
-		T2E, 1,
-		Offset(0x04),	/* SmiWakeUpEventEnable3 */
-		, 7,
-		SSEN, 1,
-		Offset(0x07),	/* SmiWakeUpEventStatus3 */
-		, 7,
-		CSSM, 1,
-		Offset(0x10),	/* AcpiEnable */
-		, 6,
-		PWDE, 1,
-		Offset(0x1C),	/* ProgramIoEnable */
-		, 3,
-		MKME, 1,
-		IO3E, 1,
-		IO2E, 1,
-		IO1E, 1,
-		IO0E, 1,
-		Offset(0x1D),	/* IOMonitorStatus */
-		, 3,
-		MKMS, 1,
-		IO3S, 1,
-		IO2S, 1,
-		IO1S, 1,
-		IO0S,1,
-		Offset(0x20),	/* AcpiPmEvtBlk */
-		APEB, 16,
-		Offset(0x36),	/* GEvtLevelConfig */
-		, 6,
-		ELC6, 1,
-		ELC7, 1,
-		Offset(0x37),	/* GPMLevelConfig0 */
-		, 3,
-		PLC0, 1,
-		PLC1, 1,
-		PLC2, 1,
-		PLC3, 1,
-		PLC8, 1,
-		Offset(0x38),	/* GPMLevelConfig1 */
-		, 1,
-		 PLC4, 1,
-		 PLC5, 1,
-		, 1,
-		 PLC6, 1,
-		 PLC7, 1,
-		Offset(0x3B),	/* PMEStatus1 */
-		GP0S, 1,
-		GM4S, 1,
-		GM5S, 1,
-		APS, 1,
-		GM6S, 1,
-		GM7S, 1,
-		GP2S, 1,
-		STSS, 1,
-		Offset(0x55),	/* SoftPciRst */
-		SPRE, 1,
-		, 1,
-		, 1,
-		PNAT, 1,
-		PWMK, 1,
-		PWNS, 1,
-
-		/* 	Offset(0x61), */	/*  Options_1 */
-		/* 		,7,  */
-		/* 		R617,1, */
-
-		Offset(0x65),	/* UsbPMControl */
-		, 4,
-		URRE, 1,
-		Offset(0x68),	/* MiscEnable68 */
-		, 3,
-		TMTE, 1,
-		, 1,
-		Offset(0x92),	/* GEVENTIN */
-		, 7,
-		E7IS, 1,
-		Offset(0x96),	/* GPM98IN */
-		G8IS, 1,
-		G9IS, 1,
-		Offset(0x9A),	/* EnhanceControl */
-		,7,
-		HPDE, 1,
-		Offset(0xA8),	/* PIO7654Enable */
-		IO4E, 1,
-		IO5E, 1,
-		IO6E, 1,
-		IO7E, 1,
-		Offset(0xA9),	/* PIO7654Status */
-		IO4S, 1,
-		IO5S, 1,
-		IO6S, 1,
-		IO7S, 1,
-	}
-
-	/* PM1 Event Block
-	* First word is PM1_Status, Second word is PM1_Enable
-	*/
-	OperationRegion(P1EB, SystemIO, APEB, 0x04)
-		Field(P1EB, ByteAcc, NoLock, Preserve) {
-		TMST, 1,
-		,    3,
-		BMST,    1,
-		GBST,   1,
-		Offset(0x01),
-		PBST, 1,
-		, 1,
-		RTST, 1,
-		, 3,
-		PWST, 1,
-		SPWS, 1,
-		Offset(0x02),
-		TMEN, 1,
-		, 4,
-		GBEN, 1,
-		Offset(0x03),
-		PBEN, 1,
-		, 1,
-		RTEN, 1,
-		, 3,
-		PWDA, 1,
-	}
-
-	OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
-		Field (GRAM, ByteAcc, Lock, Preserve)
-		{
-			Offset (0x10),
-			FLG0,   8
-		}
-
-	Scope(\_SB) {
-		/* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
-		OperationRegion(PCFG, SystemMemory, PCBA, PCLN)
-			Field(PCFG, ByteAcc, NoLock, Preserve) {
-			/* Byte offsets are computed using the following technique:
-			 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
-			 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
-			*/
-			Offset(0x00088024),	/* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
-			STB5, 32,
-			Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
-			PT0D, 1,
-			PT1D, 1,
-			PT2D, 1,
-			PT3D, 1,
-			PT4D, 1,
-			PT5D, 1,
-			PT6D, 1,
-			PT7D, 1,
-			PT8D, 1,
-			PT9D, 1,
-			Offset(0x000A0004),	/* Byte offset to SMBUS	register 4h - Bus 0, Device 20, Function 0 */
-			SBIE, 1,
-			SBME, 1,
-			Offset(0x000A0008),	/* Byte offset to SMBUS	register 8h - Bus 0, Device 20, Function 0 */
-			SBRI, 8,
-			Offset(0x000A0014),	/* Byte offset to SMBUS	register 14h - Bus 0, Device 20, Function 0 */
-			SBB1, 32,
-			Offset(0x000A0078),	/* Byte offset to SMBUS	register 78h - Bus 0, Device 20, Function 0 */
-			,14,
-			P92E, 1,		/* Port92 decode enable */
-		}
-
-		OperationRegion(SB5, SystemMemory, STB5, 0x1000)
-			Field(SB5, AnyAcc, NoLock, Preserve){
-			/* Port 0 */
-			Offset(0x120),		/* Port 0 Task file status */
-			P0ER, 1,
-			, 2,
-			P0DQ, 1,
-			, 3,
-			P0BY, 1,
-			Offset(0x128),		/* Port 0 Serial ATA status */
-			P0DD, 4,
-			, 4,
-			P0IS, 4,
-			Offset(0x12C),		/* Port 0 Serial ATA control */
-			P0DI, 4,
-			Offset(0x130),		/* Port 0 Serial ATA error */
-			, 16,
-			P0PR, 1,
-
-			/* Port 1 */
-			offset(0x1A0),		/* Port 1 Task file status */
-			P1ER, 1,
-			, 2,
-			P1DQ, 1,
-			, 3,
-			P1BY, 1,
-			Offset(0x1A8),		/* Port 1 Serial ATA status */
-			P1DD, 4,
-			, 4,
-			P1IS, 4,
-			Offset(0x1AC),		/* Port 1 Serial ATA control */
-			P1DI, 4,
-			Offset(0x1B0),		/* Port 1 Serial ATA error */
-			, 16,
-			P1PR, 1,
-
-			/* Port 2 */
-			Offset(0x220),		/* Port 2 Task file status */
-			P2ER, 1,
-			, 2,
-			P2DQ, 1,
-			, 3,
-			P2BY, 1,
-			Offset(0x228),		/* Port 2 Serial ATA status */
-			P2DD, 4,
-			, 4,
-			P2IS, 4,
-			Offset(0x22C),		/* Port 2 Serial ATA control */
-			P2DI, 4,
-			Offset(0x230),		/* Port 2 Serial ATA error */
-			, 16,
-			P2PR, 1,
-
-			/* Port 3 */
-			Offset(0x2A0),		/* Port 3 Task file status */
-			P3ER, 1,
-			, 2,
-			P3DQ, 1,
-			, 3,
-			P3BY, 1,
-			Offset(0x2A8),		/* Port 3 Serial ATA status */
-			P3DD, 4,
-			, 4,
-			P3IS, 4,
-			Offset(0x2AC),		/* Port 3 Serial ATA control */
-			P3DI, 4,
-			Offset(0x2B0),		/* Port 3 Serial ATA error */
-			, 16,
-			P3PR, 1,
-		}
-	}
-
-	#include "acpi/routing.asl"
-
-	Method(_PIC, 0x01, NotSerialized)
-	{
-		If (Arg0)
-		{
-			\_SB.CIRQ()
-		}
-		Store(Arg0, PMOD)
-	}
-
-	Scope(\_SB) {
-		Method(OSFL, 0){
-			if(LNotEqual(OSVR, Ones)) {Return(OSVR)}	/* OS version was already detected */
-			if(CondRefOf(\_OSI))
-			{
-				Store(1, OSVR)			/* Assume some form of XP */
-				if (\_OSI("Windows 2006"))      /* Vista */
-				{
-					Store(2, OSVR)
-				}
-			} else {
-				If(WCMP(\_OS,"Linux")) {
-					Store(3, OSVR)		/* Linux */
-				} Else {
-					Store(4, OSVR)		/* Gotta be WinCE */
-				}
-			}
-			Return(OSVR)
-		}
-
-		Method(CIRQ, 0x00, NotSerialized){
-			Store(0, PINA)
-			Store(0, PINB)
-			Store(0, PINC)
-			Store(0, PIND)
-			Store(0, PINE)
-			Store(0, PINF)
-			Store(0, PING)
-			Store(0, PINH)
-		}
-
-		Name(IRQB, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Shared){15}
-		})
-
-		Name(IRQP, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
-		})
-
-		Name(PITF, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Exclusive){9}
-		})
-
-		Device(INTA) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 1)
-
-			Method(_STA, 0) {
-				if (PINA) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTA._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_DIS\n") */
-				Store(0, PINA)
-			} /* End Method(_SB.INTA._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTA._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINA, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTA._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINA)
-			} /* End Method(_SB.INTA._SRS) */
-		} /* End Device(INTA) */
-
-		Device(INTB) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 2)
-
-			Method(_STA, 0) {
-				if (PINB) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTB._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_DIS\n") */
-				Store(0, PINB)
-			} /* End Method(_SB.INTB._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTB._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINB, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTB._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINB)
-			} /* End Method(_SB.INTB._SRS) */
-		} /* End Device(INTB)  */
-
-		Device(INTC) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 3)
-
-			Method(_STA, 0) {
-				if (PINC) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTC._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_DIS\n") */
-				Store(0, PINC)
-			} /* End Method(_SB.INTC._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTC._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINC, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTC._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINC)
-			} /* End Method(_SB.INTC._SRS) */
-		} /* End Device(INTC)  */
-
-		Device(INTD) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 4)
-
-			Method(_STA, 0) {
-				if (PIND) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTD._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_DIS\n") */
-				Store(0, PIND)
-			} /* End Method(_SB.INTD._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTD._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PIND, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTD._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PIND)
-			} /* End Method(_SB.INTD._SRS) */
-		} /* End Device(INTD)  */
-
-		Device(INTE) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 5)
-
-			Method(_STA, 0) {
-				if (PINE) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTE._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_DIS\n") */
-				Store(0, PINE)
-			} /* End Method(_SB.INTE._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTE._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINE, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTE._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINE)
-			} /* End Method(_SB.INTE._SRS) */
-		} /* End Device(INTE)  */
-
-		Device(INTF) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 6)
-
-			Method(_STA, 0) {
-				if (PINF) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTF._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_DIS\n") */
-				Store(0, PINF)
-			} /* End Method(_SB.INTF._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_PRS\n") */
-				Return(PITF)
-			} /* Method(_SB.INTF._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINF, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTF._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINF)
-			} /*  End Method(_SB.INTF._SRS) */
-		} /* End Device(INTF)  */
-
-		Device(INTG) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 7)
-
-			Method(_STA, 0) {
-				if (PING) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTG._STA)  */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_DIS\n") */
-				Store(0, PING)
-			} /* End Method(_SB.INTG._DIS)  */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTG._CRS)  */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PING, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTG._CRS)  */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PING)
-			} /* End Method(_SB.INTG._SRS)  */
-		} /* End Device(INTG)  */
-
-		Device(INTH) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 8)
-
-			Method(_STA, 0) {
-				if (PINH) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTH._STA)  */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_DIS\n") */
-				Store(0, PINH)
-			} /* End Method(_SB.INTH._DIS)  */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTH._CRS)  */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINH, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTH._CRS)  */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINH)
-			} /* End Method(_SB.INTH._SRS)  */
-		} /* End Device(INTH)   */
-
-	}   /* End Scope(_SB)  */
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Wake status package */
-	Name(WKST,Package(){Zero, Zero})
-
-	/*
-	* \_PTS - Prepare to Sleep method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-	*
-	* Exit:
-	*		-none-
-	*
-	* The _PTS control method is executed at the beginning of the sleep process
-	* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-	* control method may be executed a relatively long time before entering the
-	* sleep state and the OS may abort the operation without notification to
-	* the ACPI driver.  This method cannot modify the configuration or power
-	* state of any device in the system.
-	*/
-	Method(\_PTS, 1) {
-		/* DBGO("\\_PTS\n") */
-		/* DBGO("From S0 to S") */
-		/* DBGO(Arg0) */
-		/* DBGO("\n") */
-
-		/* Don't allow PCIRST# to reset USB */
-		if (LEqual(Arg0,3)){
-			Store(0,URRE)
-		}
-
-		/* Clear sleep SMI status flag and enable sleep SMI trap. */
-		/*Store(One, CSSM)
-		Store(One, SSEN)*/
-
-		/* On older chips, clear PciExpWakeDisEn */
-		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
-		*    	Store(0,\_SB.PWDE)
-		*}
-		*/
-
-		/* Clear wake status structure. */
-		Store(0, Index(WKST,0))
-		Store(0, Index(WKST,1))
-		\_SB.PCI0.SIOS (Arg0)
-	} /* End Method(\_PTS) */
-
-	/*
-	*  The following method results in a "not a valid reserved NameSeg"
-	*  warning so I have commented it out for the duration.  It isn't
-	*  used, so it could be removed.
-	*
-	*
-	*  	\_GTS OEM Going To Sleep method
-	*
-	*  	Entry:
-	*  		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*  	Exit:
-	*  		-none-
-	*
-	*  Method(\_GTS, 1) {
-	*  DBGO("\\_GTS\n")
-	*  DBGO("From S0 to S")
-	*  DBGO(Arg0)
-	*  DBGO("\n")
-	*  }
-	*/
-
-	/*
-	*	\_BFS OEM Back From Sleep method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*	Exit:
-	*		-none-
-	*/
-	Method(\_BFS, 1) {
-		/* DBGO("\\_BFS\n") */
-		/* DBGO("From S") */
-		/* DBGO(Arg0) */
-		/* DBGO(" to S0\n") */
-	}
-
-	/*
-	*  \_WAK System Wake method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*	Exit:
-	*		Return package of 2 DWords
-	*		Dword 1 - Status
-	*			0x00000000	wake succeeded
-	*			0x00000001	Wake was signaled but failed due to lack of power
-	*			0x00000002	Wake was signaled but failed due to thermal condition
-	*		Dword 2 - Power Supply state
-	*			if non-zero the effective S-state the power supply entered
-	*/
-	Method(\_WAK, 1) {
-		/* DBGO("\\_WAK\n") */
-		/* DBGO("From S") */
-		/* DBGO(Arg0) */
-		/* DBGO(" to S0\n") */
-
-		/* Re-enable HPET */
-		Store(1,HPDE)
-
-		/* Restore PCIRST# so it resets USB */
-		if (LEqual(Arg0,3)){
-			Store(1,URRE)
-		}
-
-		/* Arbitrarily clear PciExpWakeStatus */
-		Store(PWST, Local1)
-		Store(Local1, PWST)
-
-		/* if(DeRefOf(Index(WKST,0))) {
-		*	Store(0, Index(WKST,1))
-		* } else {
-		*	Store(Arg0, Index(WKST,1))
-		* }
-		*/
-		\_SB.PCI0.SIOW (Arg0)
-		Return(WKST)
-	} /* End Method(\_WAK) */
-
-	Scope(\_GPE) {	/* Start Scope GPE */
-		/*  General event 0  */
-		Method(_L00) {
-		      //DBGO("\\_GPE\\_L00\n")
-		}
-
-		/*  General event 1  */
-		Method(_L01) {
-		      //DBGO("\\_GPE\\_L01\n")
-		}
-
-		/*  General event 2  */
-		Method(_L02) {
-		      //DBGO("\\_GPE\\_L02\n")
-		}
-
-		/*  General event 3  */
-		Method(_L03) {
-			//DBGO("\\_GPE\\_L00\n")
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  General event 4  */
-		Method(_L04) {
-		      //DBGO("\\_GPE\\_L04\n")
-		}
-
-		/*  General event 5  */
-		Method(_L05) {
-		      //DBGO("\\_GPE\\_L05\n")
-		}
-
-		/* _L06 General event 6 - Used for GPM6, moved to USB.asl */
-		/* _L07 General event 7 - Used for GPM7, moved to USB.asl */
-
-		/*  Legacy PM event  */
-		Method(_L08) {
-			//DBGO("\\_GPE\\_L08\n")
-		}
-
-		/*  Temp warning (TWarn) event  */
-		Method(_L09) {
-			//DBGO("\\_GPE\\_L09\n")
-			Notify (\_TZ.TZ00, 0x80)
-		}
-
-		/*  Reserved  */
-		Method(_L0A) {
-		      //DBGO("\\_GPE\\_L0A\n")
-		}
-
-		/*  USB controller PME#  */
-		Method(_L0B) {
-			//DBGO("\\_GPE\\_L0B\n")
-			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  AC97 controller PME#  */
-		Method(_L0C) {
-		      //DBGO("\\_GPE\\_L0C\n")
-		}
-
-		/*  OtherTherm PME#  */
-		Method(_L0D) {
-		      //DBGO("\\_GPE\\_L0D\n")
-		}
-
-		/* _L0E GPM9 SCI event - Moved to USB.asl */
-
-		/*  PCIe HotPlug event  */
-		Method(_L0F) {
-			//DBGO("\\_GPE\\_L0F\n")
-		}
-
-		/*  ExtEvent0 SCI event  */
-		Method(_L10) {
-			//DBGO("\\_GPE\\_L10\n")
-		}
-
-
-		/*  ExtEvent1 SCI event  */
-		Method(_L11) {
-			//DBGO("\\_GPE\\_L11\n")
-		}
-
-		/*  PCIe PME# event  */
-		Method(_L12) {
-		      //DBGO("\\_GPE\\_L12\n")
-		}
-
-		/* _L13 GPM0 SCI event - Moved to USB.asl */
-		/* _L14 GPM1 SCI event - Moved to USB.asl */
-		/* _L15 GPM2 SCI event - Moved to USB.asl */
-		/* _L16 GPM3 SCI event - Moved to USB.asl */
-		/* _L17 GPM8 SCI event - Moved to USB.asl */
-
-		/*  GPIO0 or GEvent8 event  */
-		Method(_L18) {
-			//DBGO("\\_GPE\\_L18\n")
-			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBRb, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBRc, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBRd, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/* _L19 GPM4 SCI event - Moved to USB.asl */
-		/* _L1A GPM5 SCI event - Moved to USB.asl */
-
-		/*  Azalia SCI event  */
-		Method(_L1B) {
-			//DBGO("\\_GPE\\_L1B\n")
-			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  GPM6 SCI event - Reassigned to _L06 */
-		Method(_L1C) {
-		      //DBGO("\\_GPE\\_L1C\n")
-		}
-
-		/*  GPM7 SCI event - Reassigned to _L07 */
-		Method(_L1D) {
-		      //DBGO("\\_GPE\\_L1D\n")
-		}
-
-		/*  GPIO2 or GPIO66 SCI event  */
-		Method(_L1E) {
-			//DBGO("\\_GPE\\_L1E\n")
-		}
-
-		/* _L1F SATA SCI event - Moved to sata.asl */
-
-	} 	/* End Scope GPE */
-
-	#include "acpi/usb.asl"
-
-	/* System Bus */
-	Scope(\_SB) { /* Start \_SB scope */
-		#include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
-
-		/*  _SB.PCI0 */
-		/* Note: Only need HID on Primary Bus */
-		Device(PCI0) {
-			External (TOM1) //assigned when update_ssdt()
-			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
-
-			Name(_HID, EISAID("PNP0A03"))
-			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
-			Method(_BBN, 0) { /* Bus number = 0 */
-				Return(0)
-			}
-			Method(_STA, 0) {
-				/* DBGO("\\_SB\\PCI0\\_STA\n") */
-				Return(0x0B)     /* Status is visible */
-			}
-
-			Method(_PRT,0) {
-				If(PMOD){ Return(APR0) }	/* APIC mode */
-				Return (PR0)			/* PIC Mode */
-			} /* end _PRT */
-
-			/* Describe the Northbridge devices */
-			Device(AMRT) {
-				Name(_ADR, 0x00000000)
-			} /* end AMRT */
-
-			/* The external GFX bridge */
-			Device(PBR2) {
-				Name(_ADR, 0x00020000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APS2) }	/* APIC mode */
-					Return (PS2)			/* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR2 */
-
-			/* Dev3 is also an external GFX bridge */
-
-			Device(PBR4) {
-				Name(_ADR, 0x00040000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APS4) }	/* APIC mode */
-					Return (PS4)			/* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR4 */
-
-			Device(PBRb) {
-				Name(_ADR, 0x000b0000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APSb) }	/* APIC mode */
-					Return (PSb)			/* PIC Mode */
-				} /* end _PRT */
-			} /* end PBRb */
-
-			Device(PBRc) {
-				Name(_ADR, 0x000c0000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APSc) }	/* APIC mode */
-					Return (PSc)			/* PIC Mode */
-				} /* end _PRT */
-			} /* end PBRc */
-
-			Device(PBRd) {
-				Name(_ADR, 0x000d0000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APSd) }	/* APIC mode */
-					Return (PSd)			/*  PIC Mode */
-				} /* end _PRT */
-			} /* end PBRd */
-
-			/* Describe the Southbridge devices */
-			Device(STCR) {
-				Name(_ADR, 0x00110000)
-				#include "acpi/sata.asl"
-			} /* end STCR */
-
-			Device(UOH1) {
-				Name(_ADR, 0x00130000)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH1 */
-
-			Device(UOH2) {
-				Name(_ADR, 0x00130001)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH2 */
-
-			Device(UOH3) {
-				Name(_ADR, 0x00130002)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH3 */
-
-			Device(UOH4) {
-				Name(_ADR, 0x00130003)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH4 */
-
-			Device(UOH5) {
-				Name(_ADR, 0x00130004)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH5 */
-
-			Device(UEH1) {
-				Name(_ADR, 0x00130005)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UEH1 */
-
-			Device(SBUS) {
-				Name(_ADR, 0x00140000)
-			} /* end SBUS */
-
-			Device(AZHD) {
-				Name(_ADR, 0x00140002)
-				OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
-					Field(AZPD, AnyAcc, NoLock, Preserve) {
-					offset (0x42),
-					NSDI, 1,
-					NSDO, 1,
-					NSEN, 1,
-					offset (0x44),
-					IPCR, 4,
-					offset (0x54),
-					PWST, 2,
-					, 6,
-					PMEB, 1,
-					, 6,
-					PMST, 1,
-					offset (0x62),
-					MMCR, 1,
-					offset (0x64),
-					MMLA, 32,
-					offset (0x68),
-					MMHA, 32,
-					offset (0x6C),
-					MMDT, 16,
-				}
-
-				Method(_INI) {
-					If(LEqual(OSVR,3)){   /* If we are running Linux */
-						Store(zero, NSEN)
-						Store(one, NSDO)
-						Store(one, NSDI)
-					}
-				}
-			} /* end AZHD */
-
-			Device(LIBR) {
-				Name(_ADR, 0x00140003)
-				/* Method(_INI) {
-				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
-				} */ /* End Method(_SB.SBRDG._INI) */
-
-				/* Real Time Clock Device */
-				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
-					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){8}
-						IO(Decode16,0x0070, 0x0070, 0, 2)
-						/* IO(Decode16,0x0070, 0x0070, 0, 4) */
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
-				Device(TMR) {	/* Timer */
-					Name(_HID,EISAID("PNP0100"))	/* System Timer */
-					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){0}
-						IO(Decode16, 0x0040, 0x0040, 0, 4)
-						/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
-				Device(SPKR) {	/* Speaker */
-					Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
-					Name(_CRS, ResourceTemplate() {
-						IO(Decode16, 0x0061, 0x0061, 0, 1)
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
-				Device(PIC) {
-					Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
-					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){2}
-						IO(Decode16,0x0020, 0x0020, 0, 2)
-						IO(Decode16,0x00A0, 0x00A0, 0, 2)
-						/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
-						/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
-				Device(MAD) { /* 8257 DMA */
-					Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
-					Name(_CRS, ResourceTemplate() {
-						DMA(Compatibility,BusMaster,Transfer8){4}
-						IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
-						IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
-						IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
-						IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
-						IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
-						IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
-					}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
-				} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
-				Device(COPR) {
-					Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
-					Name(_CRS, ResourceTemplate() {
-						IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
-						IRQNoFlags(){13}
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
-				Device (PS2M) {
-					Name (_HID, EisaId ("PNP0F13"))
-					Name (_CRS, ResourceTemplate () {
-						IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
-						IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
-						IRQNoFlags () {12}
-					})
-					Method (_STA, 0, NotSerialized) {
-						And (FLG0, 0x04, Local0)
-						If (LEqual (Local0, 0x04)) {
-							Return (0x0F)
-						} Else {
-							Return (0x00)
-						}
-					}
-				}
-
-				Device (PS2K) {
-					Name (_HID, EisaId ("PNP0303"))
-					Method (_STA, 0, NotSerialized) {
-						And (FLG0, 0x04, Local0)
-						If (LEqual (Local0, 0x04)) {
-							Return (0x0F)
-						} Else {
-							Return (0x00)
-						}
-					}
-					Name (_CRS, ResourceTemplate () {
-						IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
-						IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
-						IRQNoFlags () {1}
-					})
-				}
-
-#if 0 //acpi_create_hpet
-				Device(HPET) {
-					Name(_HID,EISAID("PNP0103"))
-					Name(CRS, ResourceTemplate() {
-		    				IRQNoFlags () {0}
-		    				IRQNoFlags () {2}
-		   			 	IRQNoFlags () {8}
-						Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, MNT)	/* 1kb reserved space */
-					})
-					Method(_STA, 0, NotSerialized) {
-						Return(0x0F) /* sata is visible */
-					}
-					Method(_CRS, 0, NotSerialized) {
-						CreateDwordField(CRS, ^MNT._BAS, HPT)
-						Store(HPBA, HPT)
-						Return(CRS)
-					}
-				} /* End Device(_SB.PCI0.LIBR.HPET) */
-#endif
-			} /* end LIBR */
-
-			Device(HPBR) {
-				Name(_ADR, 0x00140004)
-			} /* end HostPciBr */
-
-			Device(ACAD) {
-				Name(_ADR, 0x00140005)
-			} /* end Ac97audio */
-
-			Device(ACMD) {
-				Name(_ADR, 0x00140006)
-			} /* end Ac97modem */
-
-			/* ITE8718 Support */
-			OperationRegion (IOID, SystemIO, 0x2E, 0x02)	/* sometimes it is 0x4E */
-				Field (IOID, ByteAcc, NoLock, Preserve)
-				{
-					SIOI,   8,    SIOD,   8		/* 0x2E and 0x2F */
-				}
-
-			IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
-			{
-					Offset (0x07),
-				LDN,	8,	/* Logical Device Number */
-					Offset (0x20),
-				CID1,	8,	/* Chip ID Byte 1, 0x87 */
-				CID2,	8,	/* Chip ID Byte 2, 0x12 */
-					Offset (0x30),
-				ACTR,	8,	/* Function activate */
-					Offset (0xF0),
-				APC0,	8,	/* APC/PME Event Enable Register */
-				APC1,	8,	/* APC/PME Status Register */
-				APC2,	8,	/* APC/PME Control Register 1 */
-				APC3,	8,	/* Environment Controller Special Configuration Register */
-				APC4,	8	/* APC/PME Control Register 2 */
-			}
-
-			/* Enter the 8718 MB PnP Mode */
-			Method (EPNP)
-			{
-				Store(0x87, SIOI)
-				Store(0x01, SIOI)
-				Store(0x55, SIOI)
-				Store(0x55, SIOI) /* 8718 magic number */
-			}
-			/* Exit the 8718 MB PnP Mode */
-			Method (XPNP)
-			{
-				Store (0x02, SIOI)
-				Store (0x02, SIOD)
-			}
-			/*
-			 * Keyboard PME is routed to SB700 Gevent3. We can wake
-			 * up the system by pressing the key.
-			 */
-			Method (SIOS, 1)
-			{
-				/* We only enable KBD PME for S5. */
-				If (LLess (Arg0, 0x05))
-				{
-					EPNP()
-					/* DBGO("8718F\n") */
-
-					Store (0x4, LDN)
-					Store (One, ACTR)  /* Enable EC */
-					/*
-					Store (0x4, LDN)
-					Store (0x04, APC4)
-					*/  /* falling edge. which mode? Not sure. */
-
-					Store (0x4, LDN)
-					Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
-					Store (0x4, LDN)
-					Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
-
-					XPNP()
-				}
-			}
-			Method (SIOW, 1)
-			{
-				EPNP()
-				Store (0x4, LDN)
-				Store (Zero, APC0) /* disable keyboard PME */
-				Store (0x4, LDN)
-				Store (0xFF, APC1) /* clear keyboard PME status */
-				XPNP()
-			}
-
-			Name (CRS, ResourceTemplate ()
-			{
-				WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
-					0x0000,             // Granularity
-					0x0000,             // Range Minimum
-					0x00FF,             // Range Maximum
-					0x0000,             // Translation Offset
-					0x0100,             // Length
-					,,)
-				IO (Decode16,
-					0x0CF8,             // Range Minimum
-					0x0CF8,             // Range Maximum
-					0x01,               // Alignment
-					0x08,               // Length
-					)
-
-				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,             // Granularity
-					0x0000,             // Range Minimum
-					0x03AF,             // Range Maximum
-					0x0000,             // Translation Offset
-					0x03B0,             // Length
-					,, , TypeStatic)
-				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,             // Granularity
-					0x03E0,             // Range Minimum
-					0x0CF7,             // Range Maximum
-					0x0000,             // Translation Offset
-					0x0918,             // Length
-					,, , TypeStatic)
-
-				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,             // Granularity
-					0x03B0,             // Range Minimum
-					0x03BB,             // Range Maximum
-					0x0000,             // Translation Offset
-					0x000C,             // Length
-					,, , TypeStatic)
-				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,             // Granularity
-					0x03C0,             // Range Minimum
-					0x03DF,             // Range Maximum
-					0x0000,             // Translation Offset
-					0x0020,             // Length
-					,, , TypeStatic)
-				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,             // Granularity
-					0x0D00,             // Range Minimum
-					0xFFFF,             // Range Maximum
-					0x0000,             // Translation Offset
-					0xF300,             // Length
-					,, , TypeStatic)
-				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	// VGA memory space
-
-				Memory32Fixed (ReadOnly,
-						0xE0000000,         // Address Base
-						0x10000000,         // Address Length, (1MB each Bus, 256 Buses by default)
-						MMIO)
-			})
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1)
-				CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1)
-
-				/*
-				 * Declare memory between TOM1 and 4GB as available
-				 * for PCI MMIO.
-				 * Use ShiftLeft to avoid 64bit constant (for XP).
-				 * This will work even if the OS does 32bit arithmetic, as
-				 * 32bit (0x00000000 - TOM1) will wrap and give the same
-				 * result as 64bit (0x100000000 - TOM1).
-				 */
-				Store(TOM1, BAS1)
-				ShiftLeft(0x10000000, 4, Local0)
-				Subtract(Local0, TOM1, Local0)
-				Store(Local0, LEN1)
-				//DBGO(TOM1)
-
-				Return (CRS)
-			}
-
-			/*
-			 *
-			 *               FIRST METHOD CALLED UPON BOOT
-			 *
-			 *  1. If debugging, print current OS and ACPI interpreter.
-			 *  2. Get PCI Interrupt routing from ACPI VSM, this
-			 *     value is based on user choice in BIOS setup.
-			 */
-			Method(_INI, 0) {
-				/* DBGO("\\_SB\\_INI\n") */
-				/* DBGO("   DSDT.ASL code from ") */
-				/* DBGO(__DATE__) */
-				/* DBGO(" ") */
-				/* DBGO(__TIME__) */
-				/* DBGO("\n   Sleep states supported: ") */
-				/* DBGO("\n") */
-				/* DBGO("   \\_OS=") */
-				/* DBGO(\_OS) */
-				/* DBGO("\n   \\_REV=") */
-				/* DBGO(\_REV) */
-				/* DBGO("\n") */
-
-				/* Determine the OS we're running on */
-				OSFL()
-				/* On older chips, clear PciExpWakeDisEn */
-				/*if (LLessEqual(\SBRI, 0x13)) {
-				 *    	Store(0,\PWDE)
-				 *}
-				 */
-			} /* End Method(_SB._INI) */
-		} /* End Device(PCI0)  */
-
-		Device(PWRB) {	/* Start Power button device */
-			Name(_HID, EISAID("PNP0C0C"))
-			Name(_UID, 0xAA)
-			Name(_PRW, Package () {3, 0x04})	/* wake from S1-S4 */
-			Name(_STA, 0x0B) /* sata is invisible */
-		}
-	} /* End \_SB scope */
-
-	Scope(\_SI) {
-		Method(_SST, 1) {
-			/* DBGO("\\_SI\\_SST\n") */
-			/* DBGO("   New Indicator state: ") */
-			/* DBGO(Arg0) */
-			/* DBGO("\n") */
-		}
-	} /* End Scope SI */
-
-	#include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
-
-	/* THERMAL */
-	Scope(\_TZ) {
-		Name (KELV, 2732)
-		Name (THOT, 800)
-		Name (TCRT, 850)
-
-		ThermalZone(TZ00) {
-			Method(_AC0,0) {	/* Active Cooling 0 (0=highest fan speed) */
-				/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
-				Return(Add(0, 2730))
-			}
-			Method(_AL0,0) {	/* Returns package of cooling device to turn on */
-				/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
-				Return(Package() {\_TZ.TZ00.FAN0})
-			}
-			Device (FAN0) {
-				Name(_HID, EISAID("PNP0C0B"))
-				Name(_PR0, Package() {PFN0})
-			}
-
-			PowerResource(PFN0,0,0) {
-				Method(_STA) {
-					Store(0xF,Local0)
-					Return(Local0)
-				}
-				Method(_ON) {
-					/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
-				}
-				Method(_OFF) {
-					/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
-				}
-			}
-
-			Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
-				/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
-				Return (Add (THOT, KELV))
-			}
-			Method(_CRT,0) {	/* return critical temp in tenths degree Kelvin */
-				/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
-				Return (Add (TCRT, KELV))
-			}
-			Method(_TMP,0) {	/* return current temp of this zone */
-				Store (SMBR (0x07, 0x4C,, 0x00), Local0)
-				If (LGreater (Local0, 0x10)) {
-					Store (Local0, Local1)
-				}
-				Else {
-					Add (Local0, THOT, Local0)
-					Return (Add (400, KELV))
-				}
-
-				Store (SMBR (0x07, 0x4C, 0x01), Local0)
-				/* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
-				/* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
-				If (LGreater (Local0, 0x10)) {
-					If (LGreater (Local0, Local1)) {
-						Store (Local0, Local1)
-					}
-
-					Multiply (Local1, 10, Local1)
-					Return (Add (Local1, KELV))
-				}
-				Else {
-					Add (Local0, THOT, Local0)
-					Return (Add (400 , KELV))
-				}
-			} /* end of _TMP */
-		} /* end of TZ00 */
-	}
-}
-/* End of ASL file */
diff --git a/src/mainboard/supermicro/h8qgi/fadt.c b/src/mainboard/supermicro/h8qgi/fadt.c
deleted file mode 100644
index ae6991f56c..0000000000
--- a/src/mainboard/supermicro/h8qgi/fadt.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- */
-
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include "Platform.h" /*sb700 platform header*/
-
-#ifndef ACPI_BLK_BASE
-  #define ACPI_BLK_BASE	PM1_EVT_BLK_ADDRESS
-#endif
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
-	acpi_header_t *header = &(fadt->header);
-
-	printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
-	/* Prepare the header */
-	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
-	memcpy(header->signature, "FACP", 4);
-	header->length = 244;
-	header->revision = 3;
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-	header->asl_compiler_revision = 0;
-
-	if ((uintptr_t)facs > 0xffffffff)
-		printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n");
-	else
-		fadt->firmware_ctrl = (uintptr_t)facs;
-
-	if ((uintptr_t)dsdt > 0xffffffff)
-		printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n");
-	else
-		fadt->dsdt = (uintptr_t)dsdt;
-
-	/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
-	fadt->preferred_pm_profile = 0x03;
-	fadt->sci_int = 9;
-	/* disable system management mode by setting to 0: */
-	fadt->smi_cmd = 0;
-	fadt->acpi_enable = 0xf0;
-	fadt->acpi_disable = 0xf1;
-	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = 0xe2;
-
-	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
-	outl(0x1, PM1_CNT_BLK_ADDRESS);           /* set SCI_EN */
-	fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
-	fadt->pm1b_evt_blk = 0x0000;
-	fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
-	fadt->pm1b_cnt_blk = 0x0000;
-	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
-	fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
-	fadt->gpe0_blk = GPE0_BLK_ADDRESS;
-	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
-
-	fadt->pm1_evt_len = 4;
-	fadt->pm1_cnt_len = 2;
-	fadt->pm2_cnt_len = 1;
-	fadt->pm_tmr_len = 4;
-	fadt->gpe0_blk_len = 8;
-	fadt->gpe1_blk_len = 0;
-	fadt->gpe1_base = 0;
-
-	fadt->cst_cnt = 0xe3;
-	fadt->p_lvl2_lat = 101;
-	fadt->p_lvl3_lat = 1001;
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
-	fadt->duty_offset = 1;
-	fadt->duty_width = 3;
-	fadt->day_alrm = 0;	/* 0x7d these have to be */
-	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
-	fadt->century = 0;	/* 0x7f to make rtc alrm work */
-	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
-	fadt->flags = 0x0001c1a5;/* 0x25; */
-
-	fadt->res2 = 0;
-
-	fadt->reset_reg.space_id = 1;
-	fadt->reset_reg.bit_width = 8;
-	fadt->reset_reg.bit_offset = 0;
-	fadt->reset_reg.resv = 0;
-	fadt->reset_reg.addrl = 0xcf9;
-	fadt->reset_reg.addrh = 0x0;
-
-	fadt->reset_value = 6;
-	fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff;
-	fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32;
-	fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff;
-	fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32;
-
-	fadt->x_pm1a_evt_blk.space_id = 1;
-	fadt->x_pm1a_evt_blk.bit_width = 32;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.resv = 0;
-	fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
-	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_evt_blk.space_id = 1;
-	fadt->x_pm1b_evt_blk.bit_width = 4;
-	fadt->x_pm1b_evt_blk.bit_offset = 0;
-	fadt->x_pm1b_evt_blk.resv = 0;
-	fadt->x_pm1b_evt_blk.addrl = 0x0;
-	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-
-	fadt->x_pm1a_cnt_blk.space_id = 1;
-	fadt->x_pm1a_cnt_blk.bit_width = 16;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.resv = 0;
-	fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
-	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_cnt_blk.space_id = 1;
-	fadt->x_pm1b_cnt_blk.bit_width = 2;
-	fadt->x_pm1b_cnt_blk.bit_offset = 0;
-	fadt->x_pm1b_cnt_blk.resv = 0;
-	fadt->x_pm1b_cnt_blk.addrl = 0x0;
-	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-
-	fadt->x_pm2_cnt_blk.space_id = 1;
-	fadt->x_pm2_cnt_blk.bit_width = 0;
-	fadt->x_pm2_cnt_blk.bit_offset = 0;
-	fadt->x_pm2_cnt_blk.resv = 0;
-	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
-	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-
-	fadt->x_pm_tmr_blk.space_id = 1;
-	fadt->x_pm_tmr_blk.bit_width = 32;
-	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.resv = 0;
-	fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
-	fadt->x_pm_tmr_blk.addrh = 0x0;
-
-
-	fadt->x_gpe0_blk.space_id = 1;
-	fadt->x_gpe0_blk.bit_width = 32;
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.resv = 0;
-	fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
-	fadt->x_gpe0_blk.addrh = 0x0;
-
-
-	fadt->x_gpe1_blk.space_id = 1;
-	fadt->x_gpe1_blk.bit_width = 0;
-	fadt->x_gpe1_blk.bit_offset = 0;
-	fadt->x_gpe1_blk.resv = 0;
-	fadt->x_gpe1_blk.addrl = 0;
-	fadt->x_gpe1_blk.addrh = 0x0;
-
-	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-}
diff --git a/src/mainboard/supermicro/h8qgi/irq_tables.c b/src/mainboard/supermicro/h8qgi/irq_tables.c
deleted file mode 100644
index 52a99e77dd..0000000000
--- a/src/mainboard/supermicro/h8qgi/irq_tables.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr += 15;
-	addr &= ~15;
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
-	return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c
deleted file mode 100644
index af7fc43ccd..0000000000
--- a/src/mainboard/supermicro/h8qgi/mainboard.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <device/pci_def.h>
-#include <NbPlatform.h>
-
-void set_pcie_dereset(void *nbconfig);
-void set_pcie_reset(void *nbconfig);
-
-/**
- *
- */
-void set_pcie_reset(void *nbconfig)
-{
-}
-
-/**
- * Mainboard specific RD890 CIMx callback
- * Release Resets to PCIe Links
- * For Both SR56X0 chips, PCIE_RESET_GPIO1 to reset pcie
- */
-void set_pcie_dereset(void *nbconfig)
-{
-	//u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
-	u32 i;
-	u32 val;
-	u32 nb_addr;
-
-	val = 0x00000007UL;
-	AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig;
-	for (i = 0; i < MAX_NB_COUNT; i ++) {
-		nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX;
-		LibNbPciIndexRMW(nb_addr,
-				NB_HTIU_REGA8,
-				AccessS3SaveWidth32,
-				~val,
-				val,
-				 &(pConfig->Northbridges[i]));
-	}
-}
-
-
-/*************************************************
- * enable the dedicated function in h8qgi board.
- *************************************************/
-static void mainboard_enable(device_t dev)
-{
-	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-}
-
-struct chip_operations mainboard_ops = {
-		.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
deleted file mode 100644
index 31379a6f56..0000000000
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-	u32 apicid_sp5100;
-	u32 apicid_sr5650;
-	device_t dev;
-	u32 *dword;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/*
-	 * AGESA v5 Apply apic enumeration rules
-	 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
-	 * put the local-APICs at m..z
-	 * For systems with < 16 APICs, put the Local-APICs at 0..n and
-	 * put the IO-APICs at (n + 1)..z
-	 */
-	if (CONFIG_MAX_CPUS >= 16)
-		apicid_sp5100 = 0x0;
-	else
-		apicid_sp5100 = CONFIG_MAX_CPUS + 1;
-	apicid_sr5650 = apicid_sp5100 + 1;
-
-	dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	if (dev) {
-		/* Set SP5100 IOAPIC ID */
-		dword = (u32 *)(uintptr_t)(pci_read_config32(dev, 0x74) & 0xfffffff0);
-		smp_write_ioapic(mc, apicid_sp5100, 0x20, dword);
-
-#ifdef UNUSED_CODE
-		u8 byte;
-		/* Initialize interrupt mapping */
-		/* aza */
-		byte = pci_read_config8(dev, 0x63);
-		byte &= 0xf8;
-		byte |= 0; /* 0: INTA, ...., 7: INTH */
-		pci_write_config8(dev, 0x63, byte);
-		/* SATA */
-		dword = pci_read_config32(dev, 0xAC);
-		dword = dword & ~(7 << 26);
-		dword = dword | (6 << 26); /* 0: INTA, ...., 7: INTH */
-		/* dword |= 1 << 22; PIC and APIC co exists */
-		pci_write_config32(dev, 0xAC, dword);
-#endif
-
-		/*
-		 * 00:12.0: PROG SATA : INT F
-		 * 00:13.0: INTA USB_0
-		 * 00:13.1: INTB USB_1
-		 * 00:13.2: INTC USB_2
-		 * 00:13.3: INTD USB_3
-		 * 00:13.4: INTC USB_4
-		 * 00:13.5: INTD USB2
-		 * 00:14.1: INTA IDE
-		 * 00:14.2: Prog HDA : INT E
-		 * 00:14.5: INTB ACI
-		 * 00:14.6: INTB MCI
-		 */
-
-		/* Set RS5650 IOAPIC ID */
-		dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-		if (dev) {
-			pci_write_config32(dev, 0xF8, 0x1);
-			dword = (u32 *)(uintptr_t)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
-			smp_write_ioapic(mc, apicid_sr5650, 0x20, dword);
-		}
-
-	}
-
-	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
-	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0);
-
-	/* PCI interrupts are level triggered, and are
-	 * associated with a specific bus/device/function tuple.
-	 */
-#define PCI_INT(bus, dev, int_sign, pin) \
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sp5100, (pin))
-
-	/* SMBUS */
-	//PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0
-
-	/* HD Audio */
-	PCI_INT(0x0, 0x14, 0x2, 0x10);
-
-	/* USB */
-	/* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */
-	/* EHCI hard-wired to 02h, corresponding to using INTB# */
-	/* USB1 */
-	PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */
-	PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */
-	PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */
-
-	/* USB2 */
-	PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */
-	PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */
-	PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */
-
-	/* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */
-	PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */
-
-	/* SATA */
-	PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
-
-	/* PCI slots */
-	dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-	if (dev && dev->enabled) {
-		u8 bus_pci = dev->link_list->secondary;
-		/* PCI_SLOT 0. */
-		PCI_INT(bus_pci, 0x5, 0x0, 0x14);
-		PCI_INT(bus_pci, 0x5, 0x1, 0x15);
-		PCI_INT(bus_pci, 0x5, 0x2, 0x16);
-		PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
-		/* PCI_SLOT 1. */
-		PCI_INT(bus_pci, 0x6, 0x0, 0x15);
-		PCI_INT(bus_pci, 0x6, 0x1, 0x16);
-		PCI_INT(bus_pci, 0x6, 0x2, 0x17);
-		PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
-		/* PCI_SLOT 2. */
-		PCI_INT(bus_pci, 0x7, 0x0, 0x16);
-		PCI_INT(bus_pci, 0x7, 0x1, 0x17);
-		PCI_INT(bus_pci, 0x7, 0x2, 0x14);
-		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
-	}
-
-	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
-	IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/supermicro/h8qgi/platform_cfg.h b/src/mainboard/supermicro/h8qgi/platform_cfg.h
deleted file mode 100644
index f5a5c73882..0000000000
--- a/src/mainboard/supermicro/h8qgi/platform_cfg.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-
-/* northbridge customize options */
-/**
- * Max number of northbridges in the system
- */
-#define MAX_NB_COUNT		1 //TODO: only 1 NB tested
-
-/**
- *  Enable check for PCIe endpoint to be ready for PCI enumeration.
- *
- */
-//#define EPREADY_WORKAROUND_DISABLED
-
-/**
- *  Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table.
- *
- */
-#define IOMMU_SUPPORT_DISABLE //TODO: enable it
-
-/**
- *  Disable server PCIe hotplug support.
- */
-
-//#define HOTPLUG_SUPPORT_DISABLED
-
-/**
- *  Disable support for device number remapping for PCIe portsserver PCIe hotplug support.
- */
-
-//#define DEVICE_REMAP_DISABLE
-
-#endif //_PLATFORM_CFG_H_
diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.c b/src/mainboard/supermicro/h8qgi/rd890_cfg.c
deleted file mode 100644
index 9bbb02a50c..0000000000
--- a/src/mainboard/supermicro/h8qgi/rd890_cfg.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "NbPlatform.h"
-#include "rd890_cfg.h"
-#include "northbridge/amd/cimx/rd890/chip.h"
-#include "nbInitializer.h"
-#include <string.h>
-#include <arch/ioapic.h>
-
-#ifndef __PRE_RAM__
-#include <device/device.h>
-extern void set_pcie_reset(void *config);
-extern void set_pcie_dereset(void *config);
-
-/**
- * Platform dependent configuration at ramstage
- */
-static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr)
-{
-	u16 i;
-	PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig;
-	//AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr);
-	struct northbridge_amd_cimx_rd890_config *rd890_info = NULL;
-	DEFAULT_PLATFORM_CONFIG(platform_config);
-
-	/* update the platform depentent configuration by devicetree */
-	rd890_info  = nb_dev->chip_info;
-	platform_config.PortEnableMap = rd890_info->port_enable;
-	if (rd890_info->gpp1_configuration == 0) {
-		platform_config.Gpp1Config = GFX_CONFIG_AAAA;
-	} else if (rd890_info->gpp1_configuration == 1) {
-		platform_config.Gpp1Config = GFX_CONFIG_AABB;
-	}
-	if (rd890_info->gpp2_configuration == 0) {
-		platform_config.Gpp2Config = GFX_CONFIG_AAAA;
-	} else if (rd890_info->gpp2_configuration == 1) {
-		platform_config.Gpp2Config = GFX_CONFIG_AABB;
-	}
-	platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration;
-
-	if (platform_config.Gpp1Config != 0) {
-		pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config;
-	}
-	if (platform_config.Gpp2Config != 0) {
-		pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config;
-	}
-	if (platform_config.Gpp3aConfig != 0) {
-		pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig;
-	}
-
-	pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20);
-	for (i = 0; i <= MAX_CORE_ID; i++) {
-		NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF;
-		NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF;
-	}
-	for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
-		NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2;
-	}
-
-	for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
-		if ((platform_config.PortEnableMap & (1 << i)) != 0) {
-			pPcieConfig->PortConfiguration[i].PortPresent = ON;
-			if ((platform_config.PortGen1Map & (1 << i)) != 0) {
-				pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1;
-			}
-			if ((platform_config.PortHotplugMap & (1 << i)) != 0) {
-				u16 j;
-				pPcieConfig->PortConfiguration[i].PortHotplug = ON; /* Enable Hotplug */
-				/* Set Hotplug descriptor info */
-				for (j = 0; j < 8; j++) {
-					u32 PortDescriptor;
-					PortDescriptor = platform_config.PortHotplugDescriptors[j];
-					if ((PortDescriptor & 0xF) == j) {
-						pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap  = (PortDescriptor >> 4)  & 3;
-						pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6)  & 1;
-						break;
-					}
-				}
-			}
-		}
-	}
-}
-#endif // __PRE_RAM__
-
-/**
- * @brief Entry point of Northbridge CIMx callout/CallBack
- *
- * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr);
- *
- * @param[in] func     Northbridge CIMx CallBackId
- * @param[in] data     Northbridge Input Data.
- * @param[in] *config  Northbridge configuration structure pointer.
- *
- */
-static u32 rd890_callout_entry(u32 func, uintptr_t data, void *config)
-{
-	u32 ret = 0;
-#ifndef __PRE_RAM__
-	device_t nb_dev = (device_t)data;
-#endif
-	AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config;
-
-	switch (func) {
-		case PHCB_AmdPortTrainingCompleted:
-			break;
-
-		case PHCB_AmdPortResetDeassert:
-#ifndef __PRE_RAM__
-			set_pcie_dereset(config);
-#endif
-			break;
-
-		case PHCB_AmdPortResetAssert:
-#ifndef __PRE_RAM__
-			set_pcie_reset(config);
-#endif
-			break;
-
-		case PHCB_AmdPortResetSupported:
-			break;
-		case PHCB_AmdGeneratePciReset:
-			break;
-		case PHCB_AmdGetExclusionTable:
-			break;
-		case PHCB_AmdAllocateBuffer:
-			break;
-		case PHCB_AmdUpdateApicInterruptMapping:
-			break;
-		case PHCB_AmdFreeBuffer:
-			break;
-		case PHCB_AmdLocateBuffer:
-			break;
-		case PHCB_AmdReportEvent:
-			break;
-		case PHCB_AmdPcieAsmpInfo:
-			break;
-
-		case CB_AmdSetNbPorConfig:
-			break;
-		case CB_AmdSetHtConfig:
-			/*TODO: different HT path and deempasis for each NB */
-			nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES;
-
-			break;
-		case CB_AmdSetPcieEarlyConfig:
-#ifndef __PRE_RAM__
-			nb_platform_config(nb_dev, nbConfigPtr);
-#endif
-			break;
-
-		case CB_AmdSetEarlyPostConfig:
-			break;
-
-		case CB_AmdSetMidPostConfig:
-			nbConfigPtr->pNbConfig->IoApicBaseAddress = IO_APIC_ADDR;
-#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu
-			/* SBIOS must alloc 16K memory for IOMMU MMIO */
-			UINT32  MmcfgBarAddress; //using default IOmmuBaseAddress
-			LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C,
-					AccessWidth32,
-					&MmcfgBarAddress,
-					nbConfigPtr);
-			MmcfgBarAddress &= ~0xf;
-			if (MmcfgBarAddress != 0) {
-				nbConfigPtr->IommuBaseAddress = MmcfgBarAddress;
-			}
-			nbConfigPtr->IommuBaseAddress = 0; //disable iommu
-#endif
-			break;
-
-		case CB_AmdSetLatePostConfig:
-			break;
-
-		case CB_AmdSetRecoveryConfig:
-			break;
-	}
-
-	return ret;
-}
-
-
-/**
- * @brief North Bridge CIMx configuration
- *
- * should be called before exeucte CIMx function.
- * this function will be called in romstage and ramstage.
- */
-void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig)
-{
-	u16 i = 0;
-	PCI_ADDR PciAddress;
-	u32 val, sbNode, sbLink;
-
-	if (!pConfig) {
-		return;
-	}
-
-	memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK));
-	for (i = 0; i < MAX_NB_COUNT; i++) {
-		pConfig->Northbridges[i].pNbConfig	= &nbConfig[i];
-		pConfig->Northbridges[i].pHtConfig	= &htConfig[i];
-		pConfig->Northbridges[i].pPcieConfig	= &pcieConfig[i];
-		pConfig->Northbridges[i].ConfigPtr	= &pConfig;
-	}
-
-	/* Initialize all NB structures */
-	AmdInitializer(pConfig);
-
-	pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
-	pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
-	pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;
-
-	/*
-	 * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform.
-	 * Always 0:0:0 on single NB platform.
-	 */
-	pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
-
-	/* Set HT path to NB by SbNode and SbLink */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
-	LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
-	sbNode = (val >> 8) & 0x07;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
-	LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
-	sbLink = (val >> 8) & 0x07; //assum ganged
-	pConfig->Northbridges[0].NbHtPath.NodeID = sbNode;
-	pConfig->Northbridges[0].NbHtPath.LinkID = sbLink;
-	//TODO: other NBs
-
-#ifndef __PRE_RAM__
-	/* If temporrary MMIO enable set up CPU MMIO */
-	for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) {
-		UINT32  MmioBase;
-		UINT32  LinkId;
-		UINT32  SubLinkId;
-		MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress;
-		if (MmioBase != 0) {
-			LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf;
-			SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0;
-			/* Set Limit */
-			LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84),
-					AccessWidth32,
-					0x0,
-					((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6),
-					&(pConfig->Northbridges[i]));
-			/* Set Base */
-			LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80),
-					AccessWidth32,
-					0x0,
-					(MmioBase << 12) | 0x3,
-					&(pConfig->Northbridges[i]));
-		}
-	}
-#endif
-}
diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.h b/src/mainboard/supermicro/h8qgi/rd890_cfg.h
deleted file mode 100644
index 0227c3f54d..0000000000
--- a/src/mainboard/supermicro/h8qgi/rd890_cfg.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef  _RD890_CFG_H_
-#define _RD890_CFG_H_
-
-#include "NbPlatform.h"
-
-/* platform dependent configuration default value */
-
-/**
- * Path from CPU to NB
- * [0..7]   - Node  (0..8)
- * [8..11]  - Link  (0..3)
- * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
- */
-#ifndef DEFAULT_HT_PATH
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
-#define DEFAULT_HT_PATH		{0x0, 0x1}
-#else /* FAMILY10 */
-#define DEFAULT_HT_PATH		{0x0, 0x3}
-#endif
-#endif
-
-/**
- * Bitmap of enabled ports on NB #0/1/2/3
- * Bit[0] - Reserved
- * Bit[1] - Reserved
- * Bit[2] - Enable PCIe port 2
- * Bit[3] - Enable PCIe port 3
- * Bit[4] - Enable PCIe port 4
- * Bit[5] - Enable PCIe port 5
- * Bit[6] - Enable PCIe port 2
- * Bit[7] - Enable PCIe port 7
- * Bit[8] - Reserved
- * Bit[9] - Enable PCIe port 9
- * Bit[10]- Enable PCIe port 10
- * Bit[11]- Enable PCIe port 11
- * Bit[12]- Enable PCIe port 12
- * Bit[13]- Enable PCIe port 13
- * Example:
- *  port_enable = 0x14
- *  Port 2 and 4 enabled for training/initialization
- */
-#ifndef DEFAULT_PORT_ENABLE_MAP
-#define DEFAULT_PORT_ENABLE_MAP		0x0014
-#endif
-
-/**
- * Bitmap of ports that have slot or onboard device connected.
- * Example force PCIe Gen1 supporton port 2 and 4  (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4)
- * define DEFAULT_PORT_FORCE_GEN1        0x604
- */
-#ifndef DEFAULT_PORT_FORCE_GEN1
-#define DEFAULT_PORT_FORCE_GEN1		0x0
-#endif
-
-/**
- * Bitmap of ports that have server hotplug support
- */
-#ifndef DEFAULT_HOTPLUG_SUPPORT
-#define DEFAULT_HOTPLUG_SUPPORT		0x0
-#endif
-
-#ifndef DEFAULT_HOTPLUG_DESCRIPTOR
-#define DEFAULT_HOTPLUG_DESCRIPTOR		{0, 0, 0, 0, 0, 0, 0, 0}
-#endif
-
-#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS
-#define DEFAULT_TEMPMMIO_BASE_ADDRESS		0xD0000000
-#endif
-
-/**
- * Default GPP1 core configuraton on NB #0/1/2/3.
- *  2  x8 slot, GFX_CONFIG_AABB
- *  1 x16 slot, GFX_CONFIG_AAAA
- */
-#ifndef DEFAULT_GPP1_CONFIG
-#define DEFAULT_GPP1_CONFIG		GFX_CONFIG_AABB
-#endif
-
-/**
- * Default GPP2 core configuraton on NB #0/1/2/3.
- *  2  x8 slot, GFX_CONFIG_AABB
- *  1 x16 slot, GFX_CONFIG_AAAA
- */
-#ifndef DEFAULT_GPP2_CONFIG
-#define DEFAULT_GPP2_CONFIG		GFX_CONFIG_AABB
-#endif
-
-/**
- * Default GPP3a core configuraton on NB #0/1/2/3.
- * 4:2:0:0:0:0   - GPP_CONFIG_GPP420000, 0x1
- * 4:1:1:0:0:0   - GPP_CONFIG_GPP411000, 0x2
- * 2:2:2:0:0:0   - GPP_CONFIG_GPP222000, 0x3
- * 2:2:1:1:0:0   - GPP_CONFIG_GPP221100, 0x4
- * 2:1:1:1:1:0   - GPP_CONFIG_GPP211110, 0x5
- * 1:1:1:1:1:1   - GPP_CONFIG_GPP111111, 0x6
- */
-#ifndef DEFAULT_GPP3A_CONFIG
-#define DEFAULT_GPP3A_CONFIG		GPP_CONFIG_GPP111111
-#endif
-
-
-/**
- * Default HT Transmitter de-emphasis setting
- */
-#ifndef DEFAULT_HT_DEEMPASIES
-#define DEFAULT_HT_DEEMPASIES		0x3
-#endif
-
-/**
- * Default APIC nterrupt base for IOAPIC
- */
-#ifndef DEFAULT_APIC_INTERRUPT_BASE
-#define DEFAULT_APIC_INTERRUPT_BASE	24
-#endif
-
-
-#define DEFAULT_PLATFORM_CONFIG(name) \
-	NB_PLATFORM_CONFIG name = { \
-		DEFAULT_PORT_ENABLE_MAP, \
-		DEFAULT_PORT_FORCE_GEN1, \
-		DEFAULT_HOTPLUG_SUPPORT, \
-		DEFAULT_HOTPLUG_DESCRIPTOR, \
-		DEFAULT_TEMPMMIO_BASE_ADDRESS, \
-		DEFAULT_GPP1_CONFIG, \
-		DEFAULT_GPP2_CONFIG, \
-		DEFAULT_GPP3A_CONFIG, \
-		DEFAULT_HT_DEEMPASIES, \
-		/*DEFAULT_HT_PATH,*/ \
-		DEFAULT_APIC_INTERRUPT_BASE, \
-	}
-
-/**
- * Platform configuration
- */
-typedef struct {
-	UINT16  PortEnableMap;            ///< Bitmap of enabled ports
-	UINT16  PortGen1Map;              ///< Bitmap of ports to disable Gen2
-	UINT16  PortHotplugMap;           ///< Bitmap of ports support hotplug
-	UINT8   PortHotplugDescriptors[8];///< Ports Hotplug descriptors
-	UINT32  TemporaryMmio;            ///< Temporary MMIO
-	UINT32  Gpp1Config;               ///< Default PCIe GFX core configuration
-	UINT32  Gpp2Config;               ///< Default PCIe GPP2 core configuration
-	UINT32  Gpp3aConfig;              ///< Default PCIe GPP3a core configuration
-	UINT8   NbTransmitterDeemphasis;  ///< HT transmitter de-emphasis level
-	//	HT_PATH NbHtPath;                 ///< HT path to NB
-	UINT8   GlobalApicInterruptBase;  ///< Global APIC interrupt base that is used in MADT table for IO APIC.
-} NB_PLATFORM_CONFIG;
-
-/**
- * Bridge CIMx configuration
- */
-void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig);
-
-#endif //_RD890_CFG_H_
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
deleted file mode 100644
index ea16396d3d..0000000000
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <lib.h>
-#include <reset.h>
-#include <stdint.h>
-#include <arch/io.h>
-#include <arch/cpu.h>
-#include <console/console.h>
-#include <arch/stages.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <northbridge/amd/agesa/family15/reset_test.h>
-#include <nb_cimx.h>
-#include <sb_cimx.h>
-#include <superio/nuvoton/wpcm450/wpcm450.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627dhg/w83627dhg.h>
-
-/* though UARTs are on the NUVOTON BMC, port 0x164E
- * PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E
- */
-#define SIO_PORT 0x164e
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	u32 val;
-
-	/* Must come first to enable PCI MMCONF. */
-	amd_initmmio();
-
-	post_code(0x31);
-
-	/* Halt if there was a built in self test failure */
-	post_code(0x33);
-	report_bist_failure(bist);
-
-	sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
-	wpcm450_enable_dev(WPCM450_SP1, SIO_PORT, CONFIG_TTYS0_BASE);
-	sb7xx_51xx_disable_wideio(0);
-	post_code(0x34);
-
-	post_code(0x35);
-	console_init();
-
-	val = cpuid_eax(1);
-	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
-	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
-	post_code(0x37);
-	agesawrapper_amdinitreset();
-
-	if (!cpu_init_detectedx && boot_cpu()) {
-		post_code(0x38);
-		/*
-		 * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
-		 * Disable all Pcie Bridges to work around It.
-		 */
-		sr56x0_rd890_disable_pcie_bridge();
-		post_code(0x39);
-		nb_Poweron_Init();
-		post_code(0x3A);
-		sb_Poweron_Init();
-	}
-	post_code(0x3B);
-	agesawrapper_amdinitearly();
-
-	post_code(0x3C);
-	/* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default.
-	 * In order to access W83795G/ADG HWM using I2C protocol,
-	 * we select function to SDA, SCL function (or GP33, GP32 function).
-	 */
-	w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI));
-
-	nb_Ht_Init();
-	post_code(0x3D);
-	/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
-	if (!warm_reset_detect(0)) {
-		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
-		distinguish_cpu_resets(0);
-		soft_reset();
-		die("After soft_reset - shouldn't see this message!!!\n");
-	}
-
-	post_code(0x40);
-	agesawrapper_amdinitpost();
-
-	post_code(0x41);
-	agesawrapper_amdinitenv();
-	post_code(0x42);
-
-	post_code(0x50);
-	printk(BIOS_DEBUG, "Disabling cache as RAM ");
-	disable_cache_as_ram();
-	printk(BIOS_DEBUG, "done\n");
-
-	post_code(0x51);
-	copy_and_run();
-
-	/* We will not return,  Should never see this message and post code. */
-	printk(BIOS_DEBUG, "should not be here -\n");
-	post_code(0x54);
-}
diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.c b/src/mainboard/supermicro/h8qgi/sb700_cfg.c
deleted file mode 100644
index 65fe023f7d..0000000000
--- a/src/mainboard/supermicro/h8qgi/sb700_cfg.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#include <string.h>
-#include <console/console.h>    /* printk */
-#include "Platform.h"
-#include "sb700_cfg.h"
-
-
-/**
- * @brief South Bridge CIMx configuration
- *
- * should be called before exeucte CIMx function.
- * this function will be called in romstage and ramstage.
- */
-void sb700_cimx_config(AMDSBCFG *sb_config)
-{
-	if (!sb_config) {
-		printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - No sb_config.\n");
-		return;
-	}
-	printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - Start.\n");
-	memset(sb_config, 0, sizeof(AMDSBCFG));
-
-	/* SB_POWERON_INIT */
-	sb_config->StdHeader.Func = SB_POWERON_INIT;
-
-	/* header */
-	sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS;
-
-	/* static Build Parameters */
-	sb_config->BuildParameters.BiosSize = BIOS_SIZE;
-	sb_config->BuildParameters.LegacyFree = LEGACY_FREE;
-	sb_config->BuildParameters.EcKbd = 0;
-	sb_config->BuildParameters.EcChannel0 = 0;
-	sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS;
-	sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS;
-	sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS;
-	sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS;
-	sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS;
-
-	sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS;
-	sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS;
-	sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS;
-	sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS;
-	sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS;
-	sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT;
-	sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS;
-
-	sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID;
-	sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID;
-	sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID;
-	sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID;
-	sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID;
-	sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID;
-	sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID;
-	sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID;
-	sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID;
-	sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID;
-	sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID;
-	sb_config->BuildParameters.SmbusSsid = SMBUS_SSID;
-	sb_config->BuildParameters.IdeSsid = IDE_SSID;
-	sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID;
-	sb_config->BuildParameters.LpcSsid = LPC_SSID;
-
-	sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS;
-
-	/* General */
-	sb_config->Spi33Mhz = 1;
-	sb_config->SpreadSpectrum = 0;
-	sb_config->PciClk5 = 0;
-	sb_config->PciClks = 0x1F;
-	sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood
-	sb_config->TimerClockSource = 2;  // Auto
-	sb_config->S3Resume = 0;
-	sb_config->RebootRequired = 0;
-
-	/* HPET */
-	sb_config->HpetTimer = HPET_TIMER;
-
-	/* USB */
-	sb_config->UsbIntClock = 0;     // Use external clock
-	sb_config->Usb1Ohci0 = 1; //0:disable  1:enable Bus 0 Dev 18 Func0
-	sb_config->Usb1Ohci1 = 1; //0:disable  1:enable Bus 0 Dev 18 Func1
-	sb_config->Usb1Ehci  = 1; //0:disable  1:enable Bus 0 Dev 18 Func2
-	sb_config->Usb2Ohci0 = 1; //0:disable  1:enable Bus 0 Dev 19 Func0
-	sb_config->Usb2Ohci1 = 1; //0:disable  1:enable Bus 0 Dev 19 Func1
-	sb_config->Usb2Ehci  = 1; //0:disable  1:enable Bus 0 Dev 19 Func2
-	sb_config->Usb3Ohci  = 1; //0:disable  1:enable Bus 0 Dev 20 Func5
-	sb_config->UsbOhciLegacyEmulation = 1; //0:Enable  1:Disable
-
-	sb_config->AcpiS1Supported = 1;
-
-	/* SATA */
-	sb_config->SataController = 1;
-	sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci
-	sb_config->SataSmbus = 0;
-	sb_config->SataAggrLinkPmCap = 1;
-	sb_config->SataPortMultCap = 1;
-	sb_config->SataClkAutoOff = 1;
-	sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
-	//TODO: set to secondary not take effect.
-	sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled
-	sb_config->SataEspPort = 0;
-	sb_config->SataClkAutoOffAhciMode = 1;
-	sb_config->SataHpcpButNonESP = 0;
-	sb_config->SataHideUnusedPort = 0;
-
-	/* Azalia HDA */
-	sb_config->AzaliaController = AZALIA_CONTROLLER;
-	sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG;
-	sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN_0;
-	sb_config->AzaliaSdin1 = AZALIA_SDIN_PIN_1;
-	sb_config->AzaliaSdin2 = AZALIA_SDIN_PIN_2;
-	sb_config->AzaliaSdin3 = AZALIA_SDIN_PIN_3;
-	sb_config->pAzaliaOemCodecTablePtr = NULL;
-
-#ifndef __PRE_RAM__
-	/* ramstage cimx config here */
-	if (!sb_config->StdHeader.pCallBack) {
-		sb_config->StdHeader.pCallBack = sb700_callout_entry;
-	}
-
-	//sb_config->
-#endif //!__PRE_RAM__
-	printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - End.\n");
-}
diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.h b/src/mainboard/supermicro/h8qgi/sb700_cfg.h
deleted file mode 100644
index 62b618f70a..0000000000
--- a/src/mainboard/supermicro/h8qgi/sb700_cfg.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#ifndef _SB700_CFG_H_
-#define _SB700_CFG_H_
-
-#include <stdint.h>
-
-
-/**
- * @def BIOS_SIZE_1M
- * @def BIOS_SIZE_2M
- * @def BIOS_SIZE_4M
- * @def BIOS_SIZE_8M
- */
-#define BIOS_SIZE_1M                    0
-#define BIOS_SIZE_2M                    1
-#define BIOS_SIZE_4M                    3
-#define BIOS_SIZE_8M                    7
-
-/* In SB700, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024)
-#define BIOS_SIZE BIOS_SIZE_1M
-#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048)
-#define BIOS_SIZE BIOS_SIZE_2M
-#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096)
-#define BIOS_SIZE BIOS_SIZE_4M
-#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192)
-#define BIOS_SIZE BIOS_SIZE_8M
-#endif
-#endif
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- *  0 - Disable Spread Spectrum function
- *  1 - Enable  Spread Spectrum function
- */
-#define SPREAD_SPECTRUM                 0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- *  0 - Disable hpet
- *  1 - Enable  hpet
- */
-#define HPET_TIMER                      1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- *   0 - Disable
- *   1 - Enable
- *  Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
- *  Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
- *  Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
- *  Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
- *  Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
- *  Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
- *  Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
- */
-#define USB_CINFIG              0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- *   0 - disable
- *   1 - enable
- *  PCI SLOT 0 define at BIT0
- *  PCI SLOT 1 define at BIT1
- *  PCI SLOT 2 define at BIT2
- *  PCI SLOT 3 define at BIT3
- *  PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL                  0x1F
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#ifndef SATA_CONTROLLER
-#define SATA_CONTROLLER               1
-#endif
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#ifndef SATA_MODE
-#define SATA_MODE                     NATIVE_IDE_MODE
-#endif
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE                 0
-#define IDE_NATIVE_MODE                 1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#ifndef SATA_IDE_MODE
-#define SATA_IDE_MODE                 IDE_LEGACY_MODE
-#endif
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- *  PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK          0x00
-#define INTERNAL_CLOCK          0x01
-
-#define SATA_CLOCK_SOURCE       EXTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED     1
-
-
-/**
- * @def   AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def   AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def   AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO                     0
-#define AZALIA_DISABLE                  1
-#define AZALIA_ENABLE                   2
-
-/**
- * @brief INCHIP HDA controller
- */
-#ifndef AZALIA_CONTROLLER
-#define AZALIA_CONTROLLER             AZALIA_AUTO
-#endif
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- *  0 - disable
- *  1 - enable
- */
-#ifndef AZALIA_PIN_CONFIG
-#define AZALIA_PIN_CONFIG             1
-#endif
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- *  SDIN0 is define at BIT0 & BIT1
- *   00 - GPIO PIN
- *   01 - Reserved
- *   10 - As a Azalia SDIN pin
- *  SDIN1 is define at BIT2 & BIT3
- *  SDIN2 is define at BIT4 & BIT5
- *  SDIN3 is define at BIT6 & BIT7
- */
-#ifndef AZALIA_SDIN_PIN
-//#define AZALIA_SDIN_PIN             0xAA
-#define AZALIA_SDIN_PIN
-#define AZALIA_SDIN_PIN_0             0x2
-#define AZALIA_SDIN_PIN_1             0x2
-#define AZALIA_SDIN_PIN_2             0x2
-#define AZALIA_SDIN_PIN_3             0x0
-#endif
-
-/**
- * @def GPP_CONTROLLER
- */
-#ifndef GPP_CONTROLLER
-#define GPP_CONTROLLER                1
-#endif
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- *  GPP_CFGMODE_X4000
- *  GPP_CFGMODE_X2200
- *  GPP_CFGMODE_X2110
- *  GPP_CFGMODE_X1111
- */
-#ifndef GPP_CFGMODE
-#define GPP_CFGMODE                   GPP_CFGMODE_X1111
-#endif
-
-
-/**
- * @brief South Bridge CIMx configuration
- *
- */
-void sb700_cimx_config(AMDSBCFG *sb_cfg);
-
-/**
- * @brief Entry point of Southbridge CIMx callout
- *
- * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
- *
- * @param[in] func    Southbridge CIMx Function ID.
- * @param[in] data    Southbridge Input Data.
- * @param[in] config  Southbridge configuration structure pointer.
- *
- */
-u32 sb700_callout_entry(u32 func, u32 data, void* config);
-
-#endif //_SB700_CFG_H_
diff --git a/src/mainboard/supermicro/h8scm/BiosCallOuts.c b/src/mainboard/supermicro/h8scm/BiosCallOuts.c
deleted file mode 100644
index 3a5044b58e..0000000000
--- a/src/mainboard/supermicro/h8scm/BiosCallOuts.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "AGESA.h"
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <stdlib.h>
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			agesa_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_GET_IDS_INIT_DATA,		agesa_EmptyIdsInitData },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
diff --git a/src/mainboard/supermicro/h8scm/Kconfig b/src/mainboard/supermicro/h8scm/Kconfig
deleted file mode 100644
index a8a8bf8ceb..0000000000
--- a/src/mainboard/supermicro/h8scm/Kconfig
+++ /dev/null
@@ -1,76 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-if BOARD_SUPERMICRO_H8SCM
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select AGESA_LEGACY
-	select CPU_AMD_AGESA_FAMILY15
-	select CPU_AMD_SOCKET_C32
-	select NORTHBRIDGE_AMD_AGESA_FAMILY15
-	select NORTHBRIDGE_AMD_CIMX_RD890
-	select SOUTHBRIDGE_AMD_CIMX_SB700
-	select SUPERIO_WINBOND_W83627DHG
-	select SUPERIO_NUVOTON_WPCM450
-	select DRIVERS_I2C_W83795
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_4096
-
-config MAINBOARD_DIR
-	string
-	default supermicro/h8scm
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "H8SCM"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 64
-
-config CPU_ADDR_BITS
-	int
-	default 36  # TODO: Set it conservatively to match both fam10 & 15
-
-config HW_MEM_HOLE_SIZE_AUTO_INC
-	bool
-	default n
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config VGA_BIOS
-	bool
-	default n
-
-config VGA_BIOS_ID
-	string
-	depends on VGA_BIOS
-	default "102b,0532"
-
-endif # BOARD_SUPERMICRO_H8SCM_FAM15
diff --git a/src/mainboard/supermicro/h8scm/Kconfig.name b/src/mainboard/supermicro/h8scm/Kconfig.name
deleted file mode 100644
index 4c5cbd90a2..0000000000
--- a/src/mainboard/supermicro/h8scm/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_SUPERMICRO_H8SCM
-	bool "H8SCM"
diff --git a/src/mainboard/supermicro/h8scm/Makefile.inc b/src/mainboard/supermicro/h8scm/Makefile.inc
deleted file mode 100644
index 0868bc22d0..0000000000
--- a/src/mainboard/supermicro/h8scm/Makefile.inc
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-romstage-y += rd890_cfg.c
-romstage-y += sb700_cfg.c
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += rd890_cfg.c
-ramstage-y += sb700_cfg.c
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
-
-AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa
-CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx
-AGESA_ROOT ?= $(AGESA_PREFIX)/f15
-NB_CIMX_ROOT ?= $(CIMX_PREFIX)/rd890
-SB_CIMX_ROOT ?= $(CIMX_PREFIX)/sb700
diff --git a/src/mainboard/supermicro/h8scm/OemCustomize.c b/src/mainboard/supermicro/h8scm/OemCustomize.c
deleted file mode 100644
index 064d400f49..0000000000
--- a/src/mainboard/supermicro/h8scm/OemCustomize.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <PlatformMemoryConfiguration.h>
-
-/*----------------------------------------------------------------------------------------
- *                        CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-//reference BKDG Table87: works
-#define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM.
-#define SEED_A 0x54
-#define SEED_B 0x4D
-#define SEED_C 0x45
-#define SEED_D 0x40
-
-#define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM.
-
-/*
- *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *  use its default conservative settings.
- *  I am not sure whether DefaultPlatformMemoryConfiguration is necessary.
- *  If I comment out these code, H8SCM will still pass mem training.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
-	WRITE_LEVELING_SEED(
-			ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
-			F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
-			F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
-			F15_WL_SEED),
-
-	HW_RXEN_SEED(
-		ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
-		SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
-		SEED_A),
-	HW_RXEN_SEED(
-		ANY_SOCKET, CHANNEL_B, ALL_DIMMS,
-		SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B,
-		SEED_B),
-	HW_RXEN_SEED(
-		ANY_SOCKET, CHANNEL_C, ALL_DIMMS,
-		SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C,
-		SEED_C),
-	HW_RXEN_SEED(
-		ANY_SOCKET, CHANNEL_D, ALL_DIMMS,
-		SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
-		SEED_D),
-
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), //max 3
-	PSO_END
-};
-
-const struct OEM_HOOK OemCustomize = {
-};
diff --git a/src/mainboard/supermicro/h8scm/OptionsIds.h b/src/mainboard/supermicro/h8scm/OptionsIds.h
deleted file mode 100644
index 079d6b2b84..0000000000
--- a/src/mainboard/supermicro/h8scm/OptionsIds.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDS_DEBUG_PORT
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_CONTROL_ENABLED TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-//#define IDSOPT_PERF_ANALYSIS   TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-//#define CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL TRUE
-//#undef IDSOPT_DEBUG_ENABLED
-//#define IDSOPT_DEBUG_ENABLED  FALSE
-//#undef IDSOPT_HOST_SIMNOW
-//#define IDSOPT_HOST_SIMNOW    FALSE
-//#undef IDSOPT_HOST_HDT
-//#define IDSOPT_HOST_HDT       FALSE
-//#define IDS_DEBUG_PORT    0x80
-
-#endif
diff --git a/src/mainboard/supermicro/h8scm/acpi/cpstate.asl b/src/mainboard/supermicro/h8scm/acpi/cpstate.asl
deleted file mode 100644
index afba4ffa93..0000000000
--- a/src/mainboard/supermicro/h8scm/acpi/cpstate.asl
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* This file defines the processor and performance state capability
- * for each core in the system.  It is included into the DSDT for each
- * core.  It assumes that each core of the system has the same performance
- * characteristics.
-*/
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
-	{
-		Scope (\_PR) {
-		Processor(CPU0,0,0x808,0x06) {
-			#include "cpstate.asl"
-		}
-		Processor(CPU1,1,0x0,0x0) {
-			#include "cpstate.asl"
-		}
-		Processor(CPU2,2,0x0,0x0) {
-			#include "cpstate.asl"
-		}
-		Processor(CPU3,3,0x0,0x0) {
-			#include "cpstate.asl"
-		}
-	}
-*/
-	/* P-state support: The maximum number of P-states supported by the */
-	/* CPUs we'll use is 6. */
-	/* Get from AMI BIOS. */
-	Name(_PSS, Package(){
-		Package ()
-		{
-		    0x00000AF0,
-		    0x0000BF81,
-		    0x00000002,
-		    0x00000002,
-		    0x00000000,
-		    0x00000000
-		},
-
-		Package ()
-		{
-		    0x00000578,
-		    0x000076F2,
-		    0x00000002,
-		    0x00000002,
-		    0x00000001,
-		    0x00000001
-		}
-	})
-
-	Name(_PCT, Package(){
-		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
-		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
-	})
-
-	Method(_PPC, 0){
-		Return(0)
-	}
diff --git a/src/mainboard/supermicro/h8scm/acpi/ide.asl b/src/mainboard/supermicro/h8scm/acpi/ide.asl
deleted file mode 100644
index 59ea078593..0000000000
--- a/src/mainboard/supermicro/h8scm/acpi/ide.asl
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(IDEC) {
-			Name(_ADR, 0x00140001)
-			#include "ide.asl"
-		}
-	}
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
-	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
-	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
-	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
-	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
-	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
-	Field(ICRG, AnyAcc, NoLock, Preserve)
-{
-	PPTS, 8,	/* Primary PIO Slave Timing */
-	PPTM, 8,	/* Primary PIO Master Timing */
-	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
-	PMTM, 8,	/* Primary MWDMA Master Timing */
-	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
-	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
-	PPSM, 4,	/* Primary PIO slave Mode */
-	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
-	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
-	PDSM, 4,	/* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
-	Store(And(Arg0, 0x0F), Local0)	/* Recovery Width */
-	Increment(Local0)
-	Store(ShiftRight(Arg0, 4), Local1)	/* Command Width */
-	Increment(Local1)
-	Return(Multiply(30, Add(Local0, Local1)))
-}
-
-Device(PRID)
-{
-	Name (_ADR, Zero)
-	Method(_GTM, 0, Serialized)
-	{
-		NAME(OTBF, Buffer(20) { /* out buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
-		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
-		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
-		/* Just return if the channel is disabled */
-		If(And(PPCR, 0x01)) { /* primary PIO control */
-			Return(OTBF)
-		}
-
-		/* Always tell them independent timing available and IOChannelReady used on both drives */
-		Or(BFFG, 0x1A, BFFG)
-
-		Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming  to PIO spd0 */
-		Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing  to PIO spd1 */
-
-		If(And(PDCR, 0x01)) {	/* It's under UDMA mode */
-			Or(BFFG, 0x01, BFFG)
-			Store(DerefOf(Index(UDTT, PDMM)), DSD0)
-		}
-		Else {
-			Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing,  DmaSpd0 */
-		}
-
-		If(And(PDCR, 0x02)) {	/* It's under UDMA mode */
-			Or(BFFG, 0x04, BFFG)
-			Store(DerefOf(Index(UDTT, PDSM)), DSD1)
-		}
-		Else {
-			Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing,  DmaSpd0 */
-		}
-
-		Return(OTBF) /* out buffer */
-	}				/* End Method(_GTM) */
-
-	Method(_STM, 3, Serialized)
-	{
-		NAME(INBF, Buffer(20) { /* in buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
-		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
-		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
-		Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
-		Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
-		Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
-		Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
-
-		Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
-		Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
-
-		If(And(BFFG, 0x01)) {	/* Drive 0 is under UDMA mode */
-			Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
-			Divide(Local0, 7, PDMM,)
-			Or(PDCR, 0x01, PDCR)
-		}
-		Else {
-			If(LNotEqual(DSD0, 0xFFFFFFFF)) {
-				Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
-				Store(DerefOf(Index(MDRT, Local0)), PMTM)
-			}
-		}
-
-		If(And(BFFG, 0x04)) {	/* Drive 1 is under UDMA mode */
-			Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
-			Divide(Local0, 7, PDSM,)
-			Or(PDCR, 0x02, PDCR)
-		}
-		Else {
-			If(LNotEqual(DSD1, 0xFFFFFFFF)) {
-				Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
-				Store(DerefOf(Index(MDRT, Local0)), PMTS)
-			}
-		}
-		/* Return(INBF) */
-	}		/*End Method(_STM) */
-	Device(MST)
-	{
-		Name(_ADR, 0)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			Store(0xA0, CMDA)
-			Store(0xA0, CMDB)
-			Store(0xA0, CMDC)
-
-			Or(PPMM, 0x08, POMD)
-
-			If(And(PDCR, 0x01)) {
-				Or(PDMM, 0x40, DMMD)
-			}
-			Else {
-				Store(Match
-				      (MDTT, MLE, GTTM(PMTM),
-				       MTR, 0, 0), Local0)
-				If(LLess(Local0, 3)) {
-					Or(0x20, Local0, DMMD)
-				}
-			}
-			Return(CMBF)
-		}
-	}		/* End Device(MST) */
-
-	Device(SLAV)
-	{
-		Name(_ADR, 1)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			Store(0xB0, CMDA)
-			Store(0xB0, CMDB)
-			Store(0xB0, CMDC)
-
-			Or(PPSM, 0x08, POMD)
-
-			If(And(PDCR, 0x02)) {
-				Or(PDSM, 0x40, DMMD)
-			}
-			Else {
-				Store(Match
-				      (MDTT, MLE, GTTM(PMTS),
-				       MTR, 0, 0), Local0)
-				If(LLess(Local0, 3)) {
-					Or(0x20, Local0, DMMD)
-				}
-			}
-			Return(CMBF)
-		}
-	}			/* End Device(SLAV) */
-}
diff --git a/src/mainboard/supermicro/h8scm/acpi/routing.asl b/src/mainboard/supermicro/h8scm/acpi/routing.asl
deleted file mode 100644
index 3cae067af3..0000000000
--- a/src/mainboard/supermicro/h8scm/acpi/routing.asl
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
-		)
-	{
-		#include "routing.asl"
-	}
-*/
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - SR5650 HT */
-		Package() { 0xFFFF, Zero, INTA, Zero },
-
-		/* Bus 0, Dev 1 - CLKCONFIG */
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
-		Package() {0x0002FFFF, 0, INTE, 0 },
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package() {0x0003FFFF, 0, INTE, 0 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package() {0x0004FFFF, 0, INTE, 0 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package() {0x0005FFFF, 0, INTE, 0 },
-
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package() {0x0006FFFF, 0, INTF, 0 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package() {0x0007FFFF, 0, INTF, 0 },
-
-		/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
-
-		/* Bus 0, Dev 9 - PCIe Bridge */
-		Package() {0x0009FFFF, 0, INTF, 0 },
-
-		/* Bus 0, Dev a - PCIe Bridge */
-		Package() {0x000AFFFF, 0, INTG, 0 },
-
-		/* Bus 0, Dev b - PCIe Bridge */
-		Package() {0x000BFFFF, 0, INTG, 0 },
-
-		/* Bus 0, Dev c - PCIe Bridge */
-		Package() {0x000CFFFF, 0, INTG, 0 },
-
-		/* Bus 0, Dev d - PCIe Bridge for Intel 82576 Giga NIC*/
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller */
-		Package() {0x0011FFFF, 0, INTG, 0 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package() {0x0012FFFF, 0, INTA, 0 },
-		Package() {0x0012FFFF, 1, INTB, 0 },
-		Package() {0x0012FFFF, 2, INTC, 0 },
-		Package() {0x0012FFFF, 3, INTD, 0 },
-
-		Package() {0x0013FFFF, 0, INTC, 0 },
-		Package() {0x0013FFFF, 1, INTD, 0 },
-		Package() {0x0013FFFF, 2, INTA, 0 },
-		Package() {0x0013FFFF, 2, INTB, 0 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - SR5650 HT */
-		Package() { 0xFFFF, Zero, Zero, 0x37 },
-
-		/* Bus 0, Dev 1 - CLKCONFIG */
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot (GFX0) */
-		Package() {0x0002FFFF, 0, 0, 0x34 },
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package() {0x0003FFFF, 0, 0, 0x34 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package() {0x0004FFFF, 0, 0, 0x34 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package() {0x0005FFFF, 0, 0, 0x34 },
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package() {0x0006FFFF, 0, 0, 0x35 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge */
-		Package() {0x0007FFFF, 0, 0, 0x35 },
-
-		/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
-
-		/* Bus 0, Dev 9 - PCIe Bridge */
-		Package() {0x0009FFFF, 0, 0, 0x35 },
-
-		/* Bus 0, Dev A - PCIe Bridge */
-		Package() {0x000AFFFF, 0, 0, 0x36 },
-
-		/* Bus 0, Dev B - PCIe Bridge */
-		Package() {0x000BFFFF, 0, 0, 0x36 },
-
-		/* Bus 0, Dev C - PCIe Bridge */
-		Package() {0x000CFFFF, 0, 0, 0x36 },
-
-		/* Bus 0, Dev D - PCIe Bridge For Intel 82576 Giga NIC*/
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller */
-		Package() {0x0011FFFF, 0, 0, 0x16 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package( ){0x0012FFFF, 0, 0, 16 },
-		Package() {0x0012FFFF, 1, 0, 17 },
-		Package() {0x0012FFFF, 2, 0, 18 },
-		Package() {0x0012FFFF, 3, 0, 19 },
-
-		Package() {0x0013FFFF, 0, 0, 18 },
-		Package() {0x0013FFFF, 1, 0, 19 },
-		Package() {0x0013FFFF, 2, 0, 16 },
-		Package() {0x0013FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package() {0x0014FFFF, 0, 0, 16 },
-		Package() {0x0014FFFF, 1, 0, 17 },
-		Package() {0x0014FFFF, 2, 0, 18 },
-		Package() {0x0014FFFF, 3, 0, 19 },
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 4 */
-		Package() {0x0000FFFF, 0, INTC, 0 },
-		Package() {0x0000FFFF, 1, INTD, 0 },
-		Package() {0x0000FFFF, 2, INTA, 0 },
-		Package() {0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 0x18 },
-		Package(){0x0000FFFF, 1, 0, 0x19 },
-		Package(){0x0000FFFF, 2, 0, 0x1A },
-		Package(){0x0000FFFF, 3, 0, 0x1B },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 0x2C },
-		Package(){0x0000FFFF, 1, 0, 0x2D },
-		Package(){0x0000FFFF, 2, 0, 0x2E },
-		Package(){0x0000FFFF, 3, 0, 0x2F },
-	})
-
-	Name(PSb, Package(){
-		/* PCIe slot - Hooked to PCIe slot 11 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APSb, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 0x20 },
-		Package(){0x0000FFFF, 1, 0, 0x21 },
-		Package(){0x0000FFFF, 2, 0, 0x22 },
-		Package(){0x0000FFFF, 3, 0, 0x23 },
-	})
-
-	Name(PSc, Package(){
-		/* PCIe slot - Hooked to PCIe slot 12 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APSc, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 0x24 },
-		Package(){0x0000FFFF, 1, 0, 0x25 },
-		Package(){0x0000FFFF, 2, 0, 0x26 },
-		Package(){0x0000FFFF, 3, 0, 0x27 },
-	})
-
-	Name(PSd, Package(){
-		/* PCIe slot - Hooked to PCIe slot 13 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-
-	Name(APSd, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 0x28 },
-		Package(){0x0000FFFF, 1, 0, 0x29 },
-		Package(){0x0000FFFF, 2, 0, 0x2A },
-		Package(){0x0000FFFF, 3, 0, 0x2B },
-	})
-
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
-		Package(){0x0004FFFF, 0, 0, 0x14 },
-		Package(){0x0003FFFF, 0, 0, 0x15 },
-		Package(){0x0003FFFF, 1, 0, 0x16 },
-		Package(){0x0003FFFF, 2, 0, 0x17 },
-		Package(){0x0003FFFF, 3, 0, 0x14 },
-	})
-}
diff --git a/src/mainboard/supermicro/h8scm/acpi/sata.asl b/src/mainboard/supermicro/h8scm/acpi/sata.asl
deleted file mode 100644
index 9e0e535da6..0000000000
--- a/src/mainboard/supermicro/h8scm/acpi/sata.asl
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (LGreater(P0IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (LGreater(P1IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (LGreater(P2IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (LGreater(P3IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (LGreater(\_SB.P0IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P0PR)
-		}
-
-		if (\_SB.P1PR) {
-			if (LGreater(\_SB.P1IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P1PR)
-		}
-
-		if (\_SB.P2PR) {
-			if (LGreater(\_SB.P2IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P2PR)
-		}
-
-		if (\_SB.P3PR) {
-			if (LGreater(\_SB.P3IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P3PR)
-		}
-	}
-}
diff --git a/src/mainboard/supermicro/h8scm/acpi/usb.asl b/src/mainboard/supermicro/h8scm/acpi/usb.asl
deleted file mode 100644
index 0f8ca9c0ab..0000000000
--- a/src/mainboard/supermicro/h8scm/acpi/usb.asl
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
-		)
-	{
-		#include "usb.asl"
-	}
-*/
-Method(UCOC, 0) {
-	Sleep(20)
-	Store(0x13,CMTI)
-	Store(0,GPSL)
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if(LEqual(GPB0,PLC0)) {
-				Not(PLC0,PLC0)
-				Store(PLC0, \_SB.PT0D)
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (LEqual(GPB1,PLC1)) {
-				Not(PLC1,PLC1)
-				Store(PLC1, \_SB.PT1D)
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (LEqual(GPB2,PLC2)) {
-				Not(PLC2,PLC2)
-				Store(PLC2, \_SB.PT2D)
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (LEqual(GPB3,PLC3)) {
-				Not(PLC3,PLC3)
-				Store(PLC3, \_SB.PT3D)
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (LEqual(GPB4,PLC4)) {
-				Not(PLC4,PLC4)
-				Store(PLC4, \_SB.PT4D)
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (LLessEqual(UOM5,9)) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (LEqual(GPB5,PLC5)) {
-				Not(PLC5,PLC5)
-				Store(PLC5, \_SB.PT5D)
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (LEqual(GPB6,PLC6)) {
-				Not(PLC6,PLC6)
-				Store(PLC6, \_SB.PT6D)
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (LEqual(GPB7,PLC7)) {
-				Not(PLC7,PLC7)
-				Store(PLC7, \_SB.PT7D)
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (LEqual(G8IS,PLC8)) {
-				Not(PLC8,PLC8)
-				Store(PLC8, \_SB.PT8D)
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (LEqual(G9IS,0)) {
-			Store(1,\_SB.PT9D)
-			}
-		}
-	}
-}
diff --git a/src/mainboard/supermicro/h8scm/acpi_tables.c b/src/mainboard/supermicro/h8scm/acpi_tables.c
deleted file mode 100644
index 4221992601..0000000000
--- a/src/mainboard/supermicro/h8scm/acpi_tables.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <arch/ioapic.h>
-#include <arch/io.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	device_t dev;
-	u32 dword;
-	u32 gsi_base = 0;
-	u32 apicid_sp5100;
-	u32 apicid_sr5650;
-
-	/*
-	 * AGESA v5 Apply apic enumeration rules
-	 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
-	 * put the local-APICs at m..z
-	 * For systems with < 16 APICs, put the Local-APICs at 0..n and
-	 * put the IO-APICs at (n + 1)..z
-	 */
-	if (CONFIG_MAX_CPUS >= 16)
-		apicid_sp5100 = 0x0;
-	else
-		apicid_sp5100 = CONFIG_MAX_CPUS + 1;
-	apicid_sr5650 = apicid_sp5100 + 1;
-
-	/* create all subtables for processors */
-	current = acpi_create_madt_lapics(current);
-
-	/* Write sp5100 IOAPIC, only one */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-			apicid_sp5100,
-			IO_APIC_ADDR,
-			0
-			);
-
-	/* IOAPIC on rs5690 */
-	gsi_base += IO_APIC_INTERRUPTS;  /* SP5100 has 24 IOAPIC entries. */
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-	if (dev) {
-		pci_write_config32(dev, 0xF8, 0x1);
-		dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
-		current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				apicid_sr5650,
-				dword,
-				gsi_base
-				);
-	}
-
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current,
-			0, //BUS
-			0, //SOURCE
-			2, //gsirq
-			0  //flags
-			);
-
-	/* 0: mean bus 0--->ISA */
-	/* 0: PIC 0 */
-	/* 2: APIC 2 */
-	/* 5 mean: 0101 --> Edge-triggered, Active high */
-
-	/* create all subtables for processors */
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
-	/* 1: LINT1 connect to NMI */
-
-	return current;
-}
diff --git a/src/mainboard/supermicro/h8scm/board_info.txt b/src/mainboard/supermicro/h8scm/board_info.txt
deleted file mode 100644
index dca0971e6e..0000000000
--- a/src/mainboard/supermicro/h8scm/board_info.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Category: server
-Board URL: http://www.supermicro.com/aplus/motherboard/opteron4000/sr56x0/h8scm.cfm
-ROM package: SOIC-8
-ROM protocol: SPI
-ROM socketed: n
diff --git a/src/mainboard/supermicro/h8scm/buildOpts.c b/src/mainboard/supermicro/h8scm/buildOpts.c
deleted file mode 100644
index 313aee36a9..0000000000
--- a/src/mainboard/supermicro/h8scm/buildOpts.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdlib.h>
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-//#define OPTION_HW_DQS_REC_EN_TRAINING TRUE
-/* AGESA will check the OEM configuration during preprocessing stage,
- * coreboot enable -Wundef option, so we should make sure we have all contanstand defined
- */
-/* MEMORY_BUS_SPEED */
-#define DDR400_FREQUENCY		200	///< DDR 400
-#define DDR533_FREQUENCY		266	///< DDR 533
-#define DDR667_FREQUENCY		333	///< DDR 667
-#define DDR800_FREQUENCY		400	///< DDR 800
-#define DDR1066_FREQUENCY		533	///< DDR 1066
-#define DDR1333_FREQUENCY		667	///< DDR 1333
-#define DDR1600_FREQUENCY		800	///< DDR 1600
-#define DDR1866_FREQUENCY		933	///< DDR 1866
-#define UNSUPPORTED_DDR_FREQUENCY	934	///< Highest limit of DDR frequency
-
-/* QUANDRANK_TYPE */
-#define QUADRANK_REGISTERED		0	///< Quadrank registered DIMM
-#define QUADRANK_UNBUFFERED		1	///< Quadrank unbuffered DIMM
-
-/* USER_MEMORY_TIMING_MODE */
-#define TIMING_MODE_AUTO		0	///< Use best rate possible
-#define TIMING_MODE_LIMITED		1	///< Set user top limit
-#define TIMING_MODE_SPECIFIC		2	///< Set user specified speed
-
-/* POWER_DOWN_MODE */
-#define POWER_DOWN_BY_CHANNEL		0	///< Channel power down mode
-#define POWER_DOWN_BY_CHIP_SELECT	1	///< Chip select power down mode
-
-/* User makes option selections here
- * Comment out the items wanted to be included in the build.
- * Uncomment those items you with to REMOVE from the build.
- */
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
-//#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
-//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
-#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
-//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT      TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES             TRUE
-//#define BLDOPT_REMOVE_SRAT                     TRUE
-//#define BLDOPT_REMOVE_SLIT                     TRUE
-//#define BLDOPT_REMOVE_WHEA                     TRUE
-//#define BLDOPT_REMOVE_DMI                      TRUE
-
-/*f15 Rev A1 ucode patch CpuF15OrMicrocodePatch0600011F */
-#define BLDOPT_REMOVE_EARLY_SAMPLES		FALSE
-
-//#define BLDOPT_REMOVE_HT_ASSIST                TRUE
-//#define BLDOPT_REMOVE_MSG_BASED_C1E            TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
-
-/* Build configuration values here.
- */
-#define BLDCFG_VRM_CURRENT_LIMIT                 120000
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD           0
-#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT          0
-#define BLDCFG_PLAT_NUM_IO_APICS                 3
-#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
-#define BLDCFG_MEM_INIT_PSTATE                   0
-#define BLDCFG_AMD_PSTATE_CAP_VALUE              0
-
-#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_SERVER
-
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR800_FREQUENCY//1600
-#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
-#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
-#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_REGISTERED
-#define BLDCFG_MEMORY_RDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE              FALSE
-#define BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB          TRUE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    FALSE//TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE//TRUE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE//TRUE
-#define BLDCFG_MEMORY_POWER_DOWN                  FALSE
-#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHANNEL
-#define BLDCFG_ONLINE_SPARE                       FALSE
-#define BLDCFG_BANK_SWIZZLE                       TRUE
-#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR800_FREQUENCY //DDR800_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
-#define BLDCFG_USE_BURST_MODE                     FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON               TRUE
-#define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
-#define BLDCFG_ECC_REDIRECTION                    FALSE
-#define BLDCFG_SCRUB_IC_RATE                      0
-#define BLDCFG_ECC_SYNC_FLOOD                     TRUE
-#define BLDCFG_ECC_SYMBOL_SIZE                    4
-
-#define BLDCFG_PCI_MMIO_BASE                    CONFIG_MMCONF_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_SIZE                    CONFIG_MMCONF_BUS_NUMBER
-
-/**
- * Enable Message Based C1e CPU feature in multi-socket systems.
- * BLDCFG_PLATFORM_C1E_OPDATA element be defined with a valid IO port value,
- * else the feature cannot be enabled.
- */
-#define BLDCFG_PLATFORM_C1E_MODE                  C1eModeMsgBased
-#define BLDCFG_PLATFORM_C1E_OPDATA                0x80//TODO
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1        0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2        0
-
-#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000
-#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    0xD0000000
-#define BLDCFG_1GB_ALIGN                          FALSE
-//#define BLDCFG_PROCESSOR_SCOPE_NAME0              'C'
-//#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
-//
-
-// Select the platform control flow mode for performance tuning.
-#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
-
-/**
- * Enable the probe filtering performance tuning feature.
- * The probe filter provides filtering of broadcast probes to
- * improve link bandwidth and performance for multi- node systems.
- *
- * This feature may interact with other performance features.
- *  TRUE  -Enable the feature (default) if supported by all processors,
- *         based on revision and presence of L3 cache.
- *         The feature is not enabled if there are no coherent HT links.
- *  FALSE -Do not enable the feature regardless of the configuration.
- */
-//TODO enable it,
-//but AGESA set PFMode = 0; //PF Disable, HW never set PFInitDone
-//hang in F10HtAssistInit() do{...} while(PFInitDone != 1)
-#define BLDCFG_USE_HT_ASSIST	FALSE
-
-/**
- * The socket and link match values are platform specific
- */
-CONST MANUAL_BUID_SWAP_LIST ROMDATA h8scm_manual_swaplist[2] =
-{
-	{
-		/* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-
-		{ //BUID Swap List
-			{ //BUID Swaps
-				/* Each Non-coherent chain may have a list of device swaps,
-				 * Each item specify a device will be swap from its current id to a new one
-				 */
-				/* FromID 0x00 is the chain with the southbridge */
-				/* 'Move' device zero to device zero, All others are non applicable */
-				{0x00, 0x00}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-			},
-
-			{ //The ordered final BUIDs
-				/* Specify the final BUID to be zero, All others are non applicable */
-				0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-				0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-				0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-				0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-			}
-		}
-	},
-
-	/* The 2nd element in the array merely terminates the list */
-	{
-		HT_LIST_TERMINAL,
-	}
-};
-
-#define HYPERTRANSPORT_V31_SUPPORT 1
-
-#if HYPERTRANSPORT_V31_SUPPORT
-/**
- * The socket and link match values are platform specific
- *
- */
-CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8scm_cpu2cpu_limit_list[2] =
-{
-	{
-		/* On the reference platform, these settings apply to all coherent links */
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-
-		/* Set incoming and outgoing links to 16 bit widths, and 3.2GHz frequencies */
-		HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M,
-	},
-
-	/* The 2nd element in the array merely terminates the list */
-	{
-		HT_LIST_TERMINAL,
-	}
-};
-
-CONST IO_PCB_LIMITS ROMDATA h8scm_io_limit_list[2] =
-{
-	{
-		/* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-
-		/* Set upstream and downstream links to 16 bit widths, and limit frequencies to 3.2GHz */
-		HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, //Actually IO hub only support 2600M MAX
-	},
-
-	/* The 2nd element in the array merely terminates the list */
-	{
-		HT_LIST_TERMINAL,
-	}
-};
-#else /* HYPERTRANSPORT_V31_SUPPORT == 0 */
-CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8scm_cpu2cpu_limit_list[2] =
-{
-	{
-		/* On the reference platform, these settings apply to all coherent links */
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-
-		/* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
-		HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
-	},
-
-	/* The 2nd element in the array merely terminates the list */
-	{
-		HT_LIST_TERMINAL,
-	}
-};
-
-CONST IO_PCB_LIMITS ROMDATA h8scm_io_limit_list[2] =
-{
-	{
-		/* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-
-		/* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
-		HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
-	},
-
-	/* The 2nd element in the array merely terminates the list */
-	{
-		HT_LIST_TERMINAL
-	}
-};
-#endif /* HYPERTRANSPORT_V31_SUPPORT == 0 */
-
-/**
- * HyperTransport links will typically require an equalization at high frequencies.
- * This is called deemphasis.
- *
- * Deemphasis is specified as levels, for example, -3 db.
- * There are two levels for each link, its receiver deemphasis level and its DCV level,
- * which is based on the far side transmitter's deemphasis.
- * For each link, different levels may be required at each link frequency.
- *
- * Coherent connections between processors should have an entry for the port on each processor.
- * There should be one entry for the host root port of each non-coherent chain.
- *
- * AGESA initialization code does not set deemphasis on IO Devices.
- * A default is provided for internal links of MCM processors, and
- * those links will generally not need deemphasis structures.
- */
-CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA h8scm_deemphasis_list[] =
-{
-	/* Socket, Link, LowFreq, HighFreq, Receiver Deemphasis, Dcv Deemphasis */
-
-	/* Non-coherent link deemphasis. */
-	{0, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
-	{0, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
-	{0, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
-	{0, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
-	{0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
-	{0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
-
-	/* Coherent link deemphasis. */
-	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
-	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3},
-	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus6},
-	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus6},
-	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus8},
-	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2600M, HT_FREQUENCY_MAX, DeemphasisLevelMinus11pre8, DcvLevelMinus11},
-
-	/* End of the list */
-	{
-		HT_LIST_TERMINAL
-	}
-};
-
-CONST AP_MTRR_SETTINGS ROMDATA h8scm_ap_mtrr_list[] =
-{
-	{AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E},
-	{AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E},
-	{AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_C0000,  0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_C8000,  0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_D0000,  0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_D8000,  0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_E0000,  0x1818181818181818},
-	{AMD_AP_MTRR_FIX4k_E8000,  0x1818181818181818},
-	{AMD_AP_MTRR_FIX4k_F0000,  0x1818181818181818},
-	{AMD_AP_MTRR_FIX4k_F8000,  0x1818181818181818},
-	{CPU_LIST_TERMINAL}
-};
-
-#define BLDCFG_BUID_SWAP_LIST			&h8scm_manual_swaplist
-#define BLDCFG_HTFABRIC_LIMITS_LIST		&h8scm_cpu2cpu_limit_list
-#define BLDCFG_HTCHAIN_LIMITS_LIST		&h8scm_io_limit_list
-#define BLDCFG_PLATFORM_DEEMPHASIS_LIST		&h8scm_deemphasis_list
-#define BLDCFG_AP_MTRR_SETTINGS_LIST		&h8scm_ap_mtrr_list
-
-/*  Process the options...
- * This file include MUST occur AFTER the user option selection settings
- */
-
-#include "SanMarinoInstall.h"
diff --git a/src/mainboard/supermicro/h8scm/cmos.layout b/src/mainboard/supermicro/h8scm/cmos.layout
deleted file mode 100644
index 956aba3689..0000000000
--- a/src/mainboard/supermicro/h8scm/cmos.layout
+++ /dev/null
@@ -1,68 +0,0 @@
-#*****************************************************************************
-#
-#  This file is part of the coreboot project.
-#
-#  Copyright (C) 2011 Advanced Micro Devices, Inc.
-#
-#  This program is free software; you can redistribute it and/or modify
-#  it under the terms of the GNU General Public License as published by
-#  the Free Software Foundation; version 2 of the License.
-#
-#  This program is distributed in the hope that it will be useful,
-#  but WITHOUT ANY WARRANTY; without even the implied warranty of
-#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-#  GNU General Public License for more details.
-#*****************************************************************************
-
-entries
-
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#392          3       r       0        unused
-395          1       e       1        hw_scrubber
-396          1       e       1        interleave_chip_selects
-397          2       e       8        max_mem_clock
-399          1       e       2        multi_core
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        iommu
-456          1       e       1        ECC_memory
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
-
-
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-8     0     400Mhz
-8     1     333Mhz
-8     2     266Mhz
-8     3     200Mhz
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/supermicro/h8scm/devicetree.cb b/src/mainboard/supermicro/h8scm/devicetree.cb
deleted file mode 100644
index 3b22407a01..0000000000
--- a/src/mainboard/supermicro/h8scm/devicetree.cb
+++ /dev/null
@@ -1,217 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-chip northbridge/amd/agesa/family15/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family15
-			device lapic 0x10 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x15d9 0xab11 inherit #Supermicro
-		chip northbridge/amd/agesa/family15 # CPU side of HT root complex
-			device pci 18.0 on     # Put IO-HUB at link_num 0, Instead of HT Link topology
-				chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex
-					device pci 0.0 on  end # HT Root Complex 0x9600
-					device pci 0.1 on end # CLKCONFIG
-					device pci 2.0 on  end # GPP1 Port0  x16 SLOT4, 0x5A16
-					device pci 3.0 on end # GPP1 Port1
-					device pci 4.0 on end # GPP3a Port0  x4 SAS
-					device pci 5.0 off end # GPP3a Port1
-					device pci 6.0 off end # GPP3a Port2
-					device pci 7.0 off end # GPP3a Port3
-					device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time
-					device pci 9.0 on end # GPP3a Port4  x1 NC
-					device pci a.0 on end # GPP3a Port5  x1 NC
-					device pci b.0 off end # GPP2 Port0 (Not for sr5650)
-					device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670)
-					device pci d.0 off  end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
-					register "gpp1_configuration" = "1"   # Configuration 16:0 default
-					#register "gpp2_configuration" = "0"   # Configuration 8:8
-					register "gpp3a_configuration" = "2"   # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1
-					register "port_enable" = "0x61f"
-				end #northbridge/amd/cimx/rd890
-				chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus
-					device pci 11.0 on end # SATA
-					device pci 12.0 on end # USB1
-					device pci 12.1 on end # USB1
-					device pci 12.2 on end # USB1
-					device pci 13.0 on end # USB2
-					device pci 13.1 on end # USB2
-					device pci 13.2 on end # USB2
-					device pci 14.0 on end # SM
-					device pci 14.1 off end # IDE  0x439c
-					device pci 14.2 off end # HDA  0x4383, h8scm not have codec.
-					device pci 14.3 on # LPC  0x439d
-						chip superio/winbond/w83627dhg
-							device pnp 2e.0 off #  Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off #  Parallel Port
-								io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 on  #  Com1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.3 on  #  Com2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							## though UARTs are on the NUVOTON BMC, superio only used to support PS2 KB/MS##
-							device pnp 2e.5 on #  PS/2 keyboard & mouse
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 0x01 #keyboard
-								irq 0x72 = 0x0C #mouse
-							end
-							device pnp 2e.6 off #  SPI
-							end
-							device pnp 2e.307 off #  GPIO6
-							end
-							device pnp 2e.8 off #  WDTO#, PLED
-							end
-							device pnp 2e.009 off #  GPIO2
-							end
-							device pnp 2e.109 off #  GPIO3
-							end
-							device pnp 2e.209 off #  GPIO4
-							end
-							device pnp 2e.309 off #  GPIO5
-							end
-							device pnp 2e.a off #  ACPI
-							end
-							device pnp 2e.b off # HWM
-								io 0x60 = 0x290
-							end
-							device pnp 2e.c off # PECI, SST
-							end
-						end #superio/winbond/w83627dhg
-						chip drivers/i2c/w83795
-							register "fanin_ctl1" = "0xff"			# Enable monitoring of FANIN1 - FANIN8
-							register "fanin_ctl2" = "0x00"			# Connect FANIN11 - FANIN14 to alternate functions
-							register "temp_ctl1" = "0x2a"			# Enable monitoring of DTS, VSEN12, and VSEN13
-							register "temp_ctl2" = "0x01"			# Enable monitoring of TD1/TR1
-							register "temp_dtse" = "0x03"			# Enable DTS1 and DTS2
-							register "volt_ctl1" = "0xff"			# Enable monitoring of VSEN1 - VSEN8
-							register "volt_ctl2" = "0xf7"			# Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT
-							register "temp1_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp1)
-							register "temp2_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp2)
-							register "temp3_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp3)
-							register "temp4_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp4)
-							register "temp5_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp5)
-							register "temp6_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp6)
-							register "temp1_source_select" = "0x00"		# Use TD1/TR1 as data source for Temp1
-							register "temp2_source_select" = "0x00"		# Use TD2/TR2 as data source for Temp2
-							register "temp3_source_select" = "0x00"		# Use TD3/TR3 as data source for Temp3
-							register "temp4_source_select" = "0x00"		# Use TD4/TR4 as data source for Temp4
-							register "temp5_source_select" = "0x00"		# Use TR5 as data source for Temp5
-							register "temp6_source_select" = "0x00"		# Use TR6 as data source for Temp6
-							register "tr1_critical_temperature" = "85"	# Set TD1/TR1 critical temperature to 85°C
-							register "tr1_critical_hysteresis" = "80"	# Set TD1/TR1 critical hysteresis temperature to 80°C
-							register "tr1_warning_temperature" = "70"	# Set TD1/TR1 warning temperature to 70°C
-							register "tr1_warning_hysteresis" = "65"	# Set TD1/TR1 warning hysteresis temperature to 65°C
-							register "dts_critical_temperature" = "85"	# Set DTS (CPU) critical temperature to 85°C
-							register "dts_critical_hysteresis" = "80"	# Set DTS (CPU) critical hysteresis temperature to 80°C
-							register "dts_warning_temperature" = "70"	# Set DTS (CPU) warning temperature to 70°C
-							register "dts_warning_hysteresis" = "65"	# Set DTS (CPU) warning hysteresis temperature to 65°C
-							register "temp1_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
-							register "temp2_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
-							register "temp3_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
-							register "temp4_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
-							register "temp5_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
-							register "temp6_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
-							register "temp1_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
-							register "temp2_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
-							register "temp3_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
-							register "temp4_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
-							register "temp5_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
-							register "temp6_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
-							register "fan1_nonstop" = "7"			# Set Fan 1 minimum speed
-							register "fan2_nonstop" = "7"			# Set Fan 2 minimum speed
-							register "fan3_nonstop" = "7"			# Set Fan 3 minimum speed
-							register "fan4_nonstop" = "7"			# Set Fan 4 minimum speed
-							register "fan5_nonstop" = "7"			# Set Fan 5 minimum speed
-							register "fan6_nonstop" = "7"			# Set Fan 6 minimum speed
-							register "fan7_nonstop" = "7"			# Set Fan 7 minimum speed
-							register "fan8_nonstop" = "7"			# Set Fan 8 minimum speed
-							register "default_speed" = "100"		# All fans to full speed on power up
-							register "fan1_duty" = "100"			# Fan 1 to full speed
-							register "fan2_duty" = "100"			# Fan 2 to full speed
-							register "fan3_duty" = "100"			# Fan 3 to full speed
-							register "fan4_duty" = "100"			# Fan 4 to full speed
-							register "fan5_duty" = "100"			# Fan 5 to full speed
-							register "fan6_duty" = "100"			# Fan 6 to full speed
-							register "fan7_duty" = "100"			# Fan 7 to full speed
-							register "fan8_duty" = "100"			# Fan 8 to full speed
-							register "vcore1_high_limit_mv" = "1500"	# VCORE1 (Node 0) high limit to 1.5V
-							register "vcore1_low_limit_mv" = "900"		# VCORE1 (Node 0) low limit to 0.9V
-							register "vcore2_high_limit_mv" = "1500"	# VCORE2 (Node 1) high limit to 1.5V
-							register "vcore2_low_limit_mv" = "900"		# VCORE2 (Node 1) low limit to 0.9V
-							register "vsen3_high_limit_mv" = "1600"		# VSEN1 (Node 0 RAM voltage) high limit to 1.6V
-							register "vsen3_low_limit_mv" = "1100"		# VSEN1 (Node 0 RAM voltage) low limit to 1.1V
-							register "vsen4_high_limit_mv" = "1600"		# VSEN2 (Node 1 RAM voltage) high limit to 1.6V
-							register "vsen4_low_limit_mv" = "1100"		# VSEN2 (Node 1 RAM voltage) low limit to 1.1V
-							register "vsen5_high_limit_mv" = "1250"		# VSEN5 (Node 0 HT link voltage) high limit to 1.25V
-							register "vsen5_low_limit_mv" = "1150"		# VSEN5 (Node 0 HT link voltage) low limit to 1.15V
-							register "vsen6_high_limit_mv" = "1250"		# VSEN6 (Node 1 HT link voltage) high limit to 1.25V
-							register "vsen6_low_limit_mv" = "1150"		# VSEN6 (Node 1 HT link voltage) low limit to 1.15V
-							register "vsen7_high_limit_mv" = "1150"		# VSEN7 (Northbridge core voltage) high limit to 1.15V
-							register "vsen7_low_limit_mv" = "1050"		# VSEN7 (Northbridge core voltage) low limit to 1.05V
-							register "vsen8_high_limit_mv" = "1900"		# VSEN8 (+1.8V) high limit to 1.9V
-							register "vsen8_low_limit_mv" = "1700"		# VSEN8 (+1.8V) low limit to 1.7V
-							register "vsen9_high_limit_mv" = "1250"		# VSEN9 (+1.2V) high limit to 1.25V
-							register "vsen9_low_limit_mv" = "1150"		# VSEN9 (+1.2V) low limit to 1.15V
-							register "vsen10_high_limit_mv" = "1150"	# VSEN10 (+1.1V) high limit to 1.15V
-							register "vsen10_low_limit_mv" = "1050"		# VSEN10 (+1.1V) low limit to 1.05V
-							register "vsen11_high_limit_mv" = "1625"	# VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V
-							register "vsen11_low_limit_mv" = "1500"		# VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V
-							register "vsen12_high_limit_mv" = "1083"	# VSEN12 (+12V, scaling factor ~12) high limit to 13V
-							register "vsen12_low_limit_mv" = "917"		# VSEN12 (+12V, scaling factor ~12) low limit to 11V
-							register "vsen13_high_limit_mv" = "1625"	# VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V
-							register "vsen13_low_limit_mv" = "1500"		# VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V
-							register "vdd_high_limit_mv" = "3500"		# 3VDD high limit to 3.5V
-							register "vdd_low_limit_mv" = "3100"		# 3VDD low limit to 3.1V
-							register "vsb_high_limit_mv" = "3500"		# 3VSB high limit to 3.5V
-							register "vsb_low_limit_mv" = "3100"		# 3VSB low limit to 3.1V
-							register "vbat_high_limit_mv" = "3500"		# VBAT (+3V) high limit to 3.5V
-							register "vbat_low_limit_mv" = "2500"		# VBAT (+3V) low limit to 2.5V
-							register "smbus_aux" = "0"			# Device located on primary SMBUS
-							device pnp 5e on #hwm
-							end
-						end #drivers/i2c/w83795
-					end # LPC
-					device pci 14.4 on end # PCI 0x4384
-					device pci 14.5 on end # USB 3
-					register "boot_switch_sata_ide" = "0"   # 0: boot from SATA. 1: IDE
-				end # southbridge/amd/cimx/sb700
-			end # device pci 18.0
-
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end #f15
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xA4, 0xA6}, {0xA0, 0xA2}, {0x00, 0x00}, {0x00, 0x00}, }, // socket 0
-				{ {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 (unused)
-			}"
-		end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
-	end #domain
-end #northbridge/amd/agesa/family15/root_complex
diff --git a/src/mainboard/supermicro/h8scm/dsdt.asl b/src/mainboard/supermicro/h8scm/dsdt.asl
deleted file mode 100644
index b8e4c1859a..0000000000
--- a/src/mainboard/supermicro/h8scm/dsdt.asl
+++ /dev/null
@@ -1,1687 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* DefinitionBlock Statement */
-DefinitionBlock (
-	"DSDT.AML",	/* Output filename */
-	"DSDT",		/* Signature */
-	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
-	"AMD   ",	/* OEMID */
-	"COREBOOT",	/* TABLE ID */
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	/* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
-
-	/* Data to be patched by the BIOS during POST */
-	/* FIXME the patching is not done yet! */
-	/* Memory related values */
-	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
-	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
-	Name(PBLN, 0x0)	/* Length of BIOS area */
-
-	Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
-	Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
-
-	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
-	/* USB overcurrent mapping pins.   */
-	Name(UOM0, 0)
-	Name(UOM1, 2)
-	Name(UOM2, 0)
-	Name(UOM3, 7)
-	Name(UOM4, 2)
-	Name(UOM5, 2)
-	Name(UOM6, 6)
-	Name(UOM7, 2)
-	Name(UOM8, 6)
-	Name(UOM9, 6)
-
-	/* Some global data */
-	Name(OSVR, 3)		/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
-	Name(OSV, Ones)	/* Assume nothing */
-	Name(PMOD, One)	/* Assume APIC */
-
-	/*
-	 * Processor Object
-	 *
-	 */
-	Scope (\_PR) {		/* define processor scope */
-		Processor(
-			C000,		/* name space name */
-			0x00,		/* Unique number for this processor */
-			0x810,		/* PBLK system I/O address !hardcoded! */
-			0x06		/* PBLKLEN for boot processor */
-			) {
-			//#include "acpi/cpstate.asl"
-		}
-		Processor(C001, 0x01, 0x00000000, 0x00) {}
-		Processor(C002, 0x02, 0x00000000, 0x00) {}
-		Processor(C003, 0x03, 0x00000000, 0x00) {}
-		Processor(C004, 0x04, 0x00000000, 0x00) {}
-		Processor(C005, 0x05, 0x00000000, 0x00) {}
-		Processor(C006, 0x06, 0x00000000, 0x00) {}
-		Processor(C007, 0x07, 0x00000000, 0x00) {}
-		Processor(C008, 0x08, 0x00000000, 0x00) {}
-		Processor(C009, 0x09, 0x00000000, 0x00) {}
-		Processor(C00A, 0x0A, 0x00000000, 0x00) {}
-		Processor(C00B, 0x0B, 0x00000000, 0x00) {}
-		Processor(C00C, 0x0C, 0x00000000, 0x00) {}
-		Processor(C00D, 0x0D, 0x00000000, 0x00) {}
-		Processor(C00E, 0x0E, 0x00000000, 0x00) {}
-		Processor(C00F, 0x0F, 0x00000000, 0x00) {}
-		Processor(C010, 0x10, 0x00000000, 0x00) {}
-		Processor(C011, 0x11, 0x00000000, 0x00) {}
-		Processor(C012, 0x12, 0x00000000, 0x00) {}
-		Processor(C013, 0x13, 0x00000000, 0x00) {}
-		Processor(C014, 0x14, 0x00000000, 0x00) {}
-		Processor(C015, 0x15, 0x00000000, 0x00) {}
-		Processor(C016, 0x16, 0x00000000, 0x00) {}
-		Processor(C017, 0x17, 0x00000000, 0x00) {}
-		Processor(C018, 0x18, 0x00000000, 0x00) {}
-		Processor(C019, 0x19, 0x00000000, 0x00) {}
-		Processor(C01A, 0x1A, 0x00000000, 0x00) {}
-		Processor(C01B, 0x1B, 0x00000000, 0x00) {}
-		Processor(C01C, 0x1C, 0x00000000, 0x00) {}
-		Processor(C01D, 0x1D, 0x00000000, 0x00) {}
-		Processor(C01E, 0x1E, 0x00000000, 0x00) {}
-		Processor(C01F, 0x1F, 0x00000000, 0x00) {}
-		Processor(C020, 0x20, 0x00000000, 0x00) {}
-		Processor(C021, 0x21, 0x00000000, 0x00) {}
-		Processor(C022, 0x22, 0x00000000, 0x00) {}
-		Processor(C023, 0x23, 0x00000000, 0x00) {}
-		Processor(C024, 0x24, 0x00000000, 0x00) {}
-		Processor(C025, 0x25, 0x00000000, 0x00) {}
-		Processor(C026, 0x26, 0x00000000, 0x00) {}
-		Processor(C027, 0x27, 0x00000000, 0x00) {}
-		Processor(C028, 0x28, 0x00000000, 0x00) {}
-		Processor(C029, 0x29, 0x00000000, 0x00) {}
-		Processor(C02A, 0x2A, 0x00000000, 0x00) {}
-		Processor(C02B, 0x2B, 0x00000000, 0x00) {}
-		Processor(C02C, 0x2C, 0x00000000, 0x00) {}
-		Processor(C02D, 0x2D, 0x00000000, 0x00) {}
-		Processor(C02E, 0x2E, 0x00000000, 0x00) {}
-		Processor(C02F, 0x2F, 0x00000000, 0x00) {}
-		Alias (C000, CPU0)
-		Alias (C001, CPU1)
-		Alias (C002, CPU2)
-		Alias (C003, CPU3)
-		Alias (C004, CPU4)
-		Alias (C005, CPU5)
-		Alias (C006, CPU6)
-		Alias (C007, CPU7)
-		Alias (C008, CPU8)
-	} /* End _PR scope */
-
-	/* PIC IRQ mapping registers, C00h-C01h */
-	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
-		Field(PRQM, ByteAcc, NoLock, Preserve) {
-		PRQI, 0x00000008,
-		PRQD, 0x00000008,  /* Offset: 1h */
-	}
-	IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
-		PINA, 0x00000008,	/* Index 0 */
-		PINB, 0x00000008,	/* Index 1 */
-		PINC, 0x00000008,	/* Index 2 */
-		PIND, 0x00000008,	/* Index 3 */
-		AINT, 0x00000008,	/* Index 4 */
-		SINT, 0x00000008,	/* Index 5 */
-		    , 0x00000008,	/* Index 6 */
-		AAUD, 0x00000008,	/* Index 7 */
-		AMOD, 0x00000008,	/* Index 8 */
-		PINE, 0x00000008,	/* Index 9 */
-		PINF, 0x00000008,	/* Index A */
-		PING, 0x00000008,	/* Index B */
-		PINH, 0x00000008,	/* Index C */
-	}
-
-	/* PCI Error control register */
-	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
-		Field(PERC, ByteAcc, NoLock, Preserve) {
-		SENS, 0x00000001,
-		PENS, 0x00000001,
-		SENE, 0x00000001,
-		PENE, 0x00000001,
-	}
-
-	/* Client Management index/data registers */
-	OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
-		Field(CMT, ByteAcc, NoLock, Preserve) {
-		CMTI, 8,
-		/* Client Management Data register */
-		G64E, 1,
-		G64O, 1,
-		G32O, 2,
-		    , 2,
-		GPSL, 2,
-	}
-
-	/* GPM Port register */
-	OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
-		Field(GPT, ByteAcc, NoLock, Preserve) {
-		GPB0,1,
-		GPB1,1,
-		GPB2,1,
-		GPB3,1,
-		GPB4,1,
-		GPB5,1,
-		GPB6,1,
-		GPB7,1,
-	}
-
-	/* Flash ROM program enable register */
-	OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
-		Field(FRE, ByteAcc, NoLock, Preserve) {
-		    , 0x00000006,
-		FLRE, 0x00000001,
-	}
-
-	/* PM2 index/data registers */
-	OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
-		Field(PM2R, ByteAcc, NoLock, Preserve) {
-		PM2I, 0x00000008,
-		PM2D, 0x00000008,
-	}
-
-	/* Power Management I/O registers */
-	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
-		Field(PIOR, ByteAcc, NoLock, Preserve) {
-		PIOI, 0x00000008,
-		PIOD, 0x00000008,
-	}
-	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
-		Offset(0x00),	/* MiscControl */
-		, 1,
-		T1EE, 1,
-		T2EE, 1,
-		Offset(0x01),	/* MiscStatus */
-		, 1,
-		T1E, 1,
-		T2E, 1,
-		Offset(0x04),	/* SmiWakeUpEventEnable3 */
-		, 7,
-		SSEN, 1,
-		Offset(0x07),	/* SmiWakeUpEventStatus3 */
-		, 7,
-		CSSM, 1,
-		Offset(0x10),	/* AcpiEnable */
-		, 6,
-		PWDE, 1,
-		Offset(0x1C),	/* ProgramIoEnable */
-		, 3,
-		MKME, 1,
-		IO3E, 1,
-		IO2E, 1,
-		IO1E, 1,
-		IO0E, 1,
-		Offset(0x1D),	/* IOMonitorStatus */
-		, 3,
-		MKMS, 1,
-		IO3S, 1,
-		IO2S, 1,
-		IO1S, 1,
-		IO0S,1,
-		Offset(0x20),	/* AcpiPmEvtBlk */
-		APEB, 16,
-		Offset(0x36),	/* GEvtLevelConfig */
-		, 6,
-		ELC6, 1,
-		ELC7, 1,
-		Offset(0x37),	/* GPMLevelConfig0 */
-		, 3,
-		PLC0, 1,
-		PLC1, 1,
-		PLC2, 1,
-		PLC3, 1,
-		PLC8, 1,
-		Offset(0x38),	/* GPMLevelConfig1 */
-		, 1,
-		 PLC4, 1,
-		 PLC5, 1,
-		, 1,
-		 PLC6, 1,
-		 PLC7, 1,
-		Offset(0x3B),	/* PMEStatus1 */
-		GP0S, 1,
-		GM4S, 1,
-		GM5S, 1,
-		APS, 1,
-		GM6S, 1,
-		GM7S, 1,
-		GP2S, 1,
-		STSS, 1,
-		Offset(0x55),	/* SoftPciRst */
-		SPRE, 1,
-		, 1,
-		, 1,
-		PNAT, 1,
-		PWMK, 1,
-		PWNS, 1,
-
-		/* 	Offset(0x61), */	/*  Options_1 */
-		/* 		,7,  */
-		/* 		R617,1, */
-
-		Offset(0x65),	/* UsbPMControl */
-		, 4,
-		URRE, 1,
-		Offset(0x68),	/* MiscEnable68 */
-		, 3,
-		TMTE, 1,
-		, 1,
-		Offset(0x92),	/* GEVENTIN */
-		, 7,
-		E7IS, 1,
-		Offset(0x96),	/* GPM98IN */
-		G8IS, 1,
-		G9IS, 1,
-		Offset(0x9A),	/* EnhanceControl */
-		,7,
-		HPDE, 1,
-		Offset(0xA8),	/* PIO7654Enable */
-		IO4E, 1,
-		IO5E, 1,
-		IO6E, 1,
-		IO7E, 1,
-		Offset(0xA9),	/* PIO7654Status */
-		IO4S, 1,
-		IO5S, 1,
-		IO6S, 1,
-		IO7S, 1,
-	}
-
-	/* PM1 Event Block
-	* First word is PM1_Status, Second word is PM1_Enable
-	*/
-	OperationRegion(P1EB, SystemIO, APEB, 0x04)
-		Field(P1EB, ByteAcc, NoLock, Preserve) {
-		TMST, 1,
-		,    3,
-		BMST,    1,
-		GBST,   1,
-		Offset(0x01),
-		PBST, 1,
-		, 1,
-		RTST, 1,
-		, 3,
-		PWST, 1,
-		SPWS, 1,
-		Offset(0x02),
-		TMEN, 1,
-		, 4,
-		GBEN, 1,
-		Offset(0x03),
-		PBEN, 1,
-		, 1,
-		RTEN, 1,
-		, 3,
-		PWDA, 1,
-	}
-
-	OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
-		Field (GRAM, ByteAcc, Lock, Preserve)
-		{
-			Offset (0x10),
-			FLG0,   8
-		}
-
-	Scope(\_SB) {
-		/* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
-		OperationRegion(PCFG, SystemMemory, PCBA, PCLN)
-			Field(PCFG, ByteAcc, NoLock, Preserve) {
-			/* Byte offsets are computed using the following technique:
-			 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
-			 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
-			*/
-			Offset(0x00088024),	/* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
-			STB5, 32,
-			Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
-			PT0D, 1,
-			PT1D, 1,
-			PT2D, 1,
-			PT3D, 1,
-			PT4D, 1,
-			PT5D, 1,
-			PT6D, 1,
-			PT7D, 1,
-			PT8D, 1,
-			PT9D, 1,
-			Offset(0x000A0004),	/* Byte offset to SMBUS	register 4h - Bus 0, Device 20, Function 0 */
-			SBIE, 1,
-			SBME, 1,
-			Offset(0x000A0008),	/* Byte offset to SMBUS	register 8h - Bus 0, Device 20, Function 0 */
-			SBRI, 8,
-			Offset(0x000A0014),	/* Byte offset to SMBUS	register 14h - Bus 0, Device 20, Function 0 */
-			SBB1, 32,
-			Offset(0x000A0078),	/* Byte offset to SMBUS	register 78h - Bus 0, Device 20, Function 0 */
-			,14,
-			P92E, 1,		/* Port92 decode enable */
-		}
-
-		OperationRegion(SB5, SystemMemory, STB5, 0x1000)
-			Field(SB5, AnyAcc, NoLock, Preserve){
-			/* Port 0 */
-			Offset(0x120),		/* Port 0 Task file status */
-			P0ER, 1,
-			, 2,
-			P0DQ, 1,
-			, 3,
-			P0BY, 1,
-			Offset(0x128),		/* Port 0 Serial ATA status */
-			P0DD, 4,
-			, 4,
-			P0IS, 4,
-			Offset(0x12C),		/* Port 0 Serial ATA control */
-			P0DI, 4,
-			Offset(0x130),		/* Port 0 Serial ATA error */
-			, 16,
-			P0PR, 1,
-
-			/* Port 1 */
-			offset(0x1A0),		/* Port 1 Task file status */
-			P1ER, 1,
-			, 2,
-			P1DQ, 1,
-			, 3,
-			P1BY, 1,
-			Offset(0x1A8),		/* Port 1 Serial ATA status */
-			P1DD, 4,
-			, 4,
-			P1IS, 4,
-			Offset(0x1AC),		/* Port 1 Serial ATA control */
-			P1DI, 4,
-			Offset(0x1B0),		/* Port 1 Serial ATA error */
-			, 16,
-			P1PR, 1,
-
-			/* Port 2 */
-			Offset(0x220),		/* Port 2 Task file status */
-			P2ER, 1,
-			, 2,
-			P2DQ, 1,
-			, 3,
-			P2BY, 1,
-			Offset(0x228),		/* Port 2 Serial ATA status */
-			P2DD, 4,
-			, 4,
-			P2IS, 4,
-			Offset(0x22C),		/* Port 2 Serial ATA control */
-			P2DI, 4,
-			Offset(0x230),		/* Port 2 Serial ATA error */
-			, 16,
-			P2PR, 1,
-
-			/* Port 3 */
-			Offset(0x2A0),		/* Port 3 Task file status */
-			P3ER, 1,
-			, 2,
-			P3DQ, 1,
-			, 3,
-			P3BY, 1,
-			Offset(0x2A8),		/* Port 3 Serial ATA status */
-			P3DD, 4,
-			, 4,
-			P3IS, 4,
-			Offset(0x2AC),		/* Port 3 Serial ATA control */
-			P3DI, 4,
-			Offset(0x2B0),		/* Port 3 Serial ATA error */
-			, 16,
-			P3PR, 1,
-		}
-	}
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-		Method(OSFL, 0){
-			if(LNotEqual(OSVR, Ones)) {Return(OSVR)}	/* OS version was already detected */
-			if(CondRefOf(\_OSI))
-			{
-				Store(1, OSVR)			/* Assume some form of XP */
-				if (\_OSI("Windows 2006"))      /* Vista */
-				{
-					Store(2, OSVR)
-				}
-			} else {
-				If(WCMP(\_OS,"Linux")) {
-					Store(3, OSVR)		/* Linux */
-				} Else {
-					Store(4, OSVR)		/* Gotta be WinCE */
-				}
-			}
-			Return(OSVR)
-		}
-
-		Method(_PIC, 0x01, NotSerialized)
-		{
-			If (Arg0)
-			{
-				\_SB.CIRQ()
-			}
-			Store(Arg0, PMOD)
-		}
-		Method(CIRQ, 0x00, NotSerialized){
-			Store(0, PINA)
-			Store(0, PINB)
-			Store(0, PINC)
-			Store(0, PIND)
-			Store(0, PINE)
-			Store(0, PINF)
-			Store(0, PING)
-			Store(0, PINH)
-		}
-
-		Name(IRQB, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Shared){15}
-		})
-
-		Name(IRQP, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
-		})
-
-		Name(PITF, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Exclusive){9}
-		})
-
-		Device(INTA) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 1)
-
-			Method(_STA, 0) {
-				if (PINA) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTA._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_DIS\n") */
-				Store(0, PINA)
-			} /* End Method(_SB.INTA._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTA._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINA, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTA._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINA)
-			} /* End Method(_SB.INTA._SRS) */
-		} /* End Device(INTA) */
-
-		Device(INTB) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 2)
-
-			Method(_STA, 0) {
-				if (PINB) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTB._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_DIS\n") */
-				Store(0, PINB)
-			} /* End Method(_SB.INTB._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTB._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINB, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTB._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINB)
-			} /* End Method(_SB.INTB._SRS) */
-		} /* End Device(INTB)  */
-
-		Device(INTC) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 3)
-
-			Method(_STA, 0) {
-				if (PINC) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTC._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_DIS\n") */
-				Store(0, PINC)
-			} /* End Method(_SB.INTC._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTC._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINC, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTC._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINC)
-			} /* End Method(_SB.INTC._SRS) */
-		} /* End Device(INTC)  */
-
-		Device(INTD) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 4)
-
-			Method(_STA, 0) {
-				if (PIND) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTD._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_DIS\n") */
-				Store(0, PIND)
-			} /* End Method(_SB.INTD._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTD._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PIND, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTD._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PIND)
-			} /* End Method(_SB.INTD._SRS) */
-		} /* End Device(INTD)  */
-
-		Device(INTE) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 5)
-
-			Method(_STA, 0) {
-				if (PINE) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTE._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_DIS\n") */
-				Store(0, PINE)
-			} /* End Method(_SB.INTE._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTE._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINE, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTE._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINE)
-			} /* End Method(_SB.INTE._SRS) */
-		} /* End Device(INTE)  */
-
-		Device(INTF) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 6)
-
-			Method(_STA, 0) {
-				if (PINF) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTF._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_DIS\n") */
-				Store(0, PINF)
-			} /* End Method(_SB.INTF._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_PRS\n") */
-				Return(PITF)
-			} /* Method(_SB.INTF._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINF, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTF._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINF)
-			} /*  End Method(_SB.INTF._SRS) */
-		} /* End Device(INTF)  */
-
-		Device(INTG) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 7)
-
-			Method(_STA, 0) {
-				if (PING) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTG._STA)  */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_DIS\n") */
-				Store(0, PING)
-			} /* End Method(_SB.INTG._DIS)  */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTG._CRS)  */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PING, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTG._CRS)  */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PING)
-			} /* End Method(_SB.INTG._SRS)  */
-		} /* End Device(INTG)  */
-
-		Device(INTH) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 8)
-
-			Method(_STA, 0) {
-				if (PINH) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTH._STA)  */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_DIS\n") */
-				Store(0, PINH)
-			} /* End Method(_SB.INTH._DIS)  */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTH._CRS)  */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINH, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTH._CRS)  */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINH)
-			} /* End Method(_SB.INTH._SRS)  */
-		} /* End Device(INTH)   */
-
-	}   /* End Scope(_SB)  */
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Wake status package */
-	Name(WKST,Package(){Zero, Zero})
-
-	/*
-	* \_PTS - Prepare to Sleep method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-	*
-	* Exit:
-	*		-none-
-	*
-	* The _PTS control method is executed at the beginning of the sleep process
-	* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-	* control method may be executed a relatively long time before entering the
-	* sleep state and the OS may abort the operation without notification to
-	* the ACPI driver.  This method cannot modify the configuration or power
-	* state of any device in the system.
-	*/
-	Method(\_PTS, 1) {
-		/* DBGO("\\_PTS\n") */
-		/* DBGO("From S0 to S") */
-		/* DBGO(Arg0) */
-		/* DBGO("\n") */
-
-		/* Don't allow PCIRST# to reset USB */
-		if (LEqual(Arg0,3)){
-			Store(0,URRE)
-		}
-
-		/* Clear sleep SMI status flag and enable sleep SMI trap. */
-		/*Store(One, CSSM)
-		Store(One, SSEN)*/
-
-		/* On older chips, clear PciExpWakeDisEn */
-		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
-		*    	Store(0,\_SB.PWDE)
-		*}
-		*/
-
-		/* Clear wake status structure. */
-		Store(0, Index(WKST,0))
-		Store(0, Index(WKST,1))
-		\_SB.PCI0.SIOS (Arg0)
-	} /* End Method(\_PTS) */
-
-	/*
-	*  The following method results in a "not a valid reserved NameSeg"
-	*  warning so I have commented it out for the duration.  It isn't
-	*  used, so it could be removed.
-	*
-	*
-	*  	\_GTS OEM Going To Sleep method
-	*
-	*  	Entry:
-	*  		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*  	Exit:
-	*  		-none-
-	*
-	*  Method(\_GTS, 1) {
-	*  DBGO("\\_GTS\n")
-	*  DBGO("From S0 to S")
-	*  DBGO(Arg0)
-	*  DBGO("\n")
-	*  }
-	*/
-
-	/*
-	*	\_BFS OEM Back From Sleep method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*	Exit:
-	*		-none-
-	*/
-	Method(\_BFS, 1) {
-		/* DBGO("\\_BFS\n") */
-		/* DBGO("From S") */
-		/* DBGO(Arg0) */
-		/* DBGO(" to S0\n") */
-	}
-
-	/*
-	*  \_WAK System Wake method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*	Exit:
-	*		Return package of 2 DWords
-	*		Dword 1 - Status
-	*			0x00000000	wake succeeded
-	*			0x00000001	Wake was signaled but failed due to lack of power
-	*			0x00000002	Wake was signaled but failed due to thermal condition
-	*		Dword 2 - Power Supply state
-	*			if non-zero the effective S-state the power supply entered
-	*/
-	Method(\_WAK, 1) {
-		/* DBGO("\\_WAK\n") */
-		/* DBGO("From S") */
-		/* DBGO(Arg0) */
-		/* DBGO(" to S0\n") */
-
-		/* Re-enable HPET */
-		Store(1,HPDE)
-
-		/* Restore PCIRST# so it resets USB */
-		if (LEqual(Arg0,3)){
-			Store(1,URRE)
-		}
-
-		/* Arbitrarily clear PciExpWakeStatus */
-		Store(PWST, Local1)
-		Store(Local1, PWST)
-
-		/* if(DeRefOf(Index(WKST,0))) {
-		*	Store(0, Index(WKST,1))
-		* } else {
-		*	Store(Arg0, Index(WKST,1))
-		* }
-		*/
-		\_SB.PCI0.SIOW (Arg0)
-		Return(WKST)
-	} /* End Method(\_WAK) */
-
-	Scope(\_GPE) {	/* Start Scope GPE */
-		/*  General event 0  */
-		Method(_L00) {
-		      //DBGO("\\_GPE\\_L00\n")
-		}
-
-		/*  General event 1  */
-		Method(_L01) {
-		      //DBGO("\\_GPE\\_L01\n")
-		}
-
-		/*  General event 2  */
-		Method(_L02) {
-		      //DBGO("\\_GPE\\_L02\n")
-		}
-
-		/*  General event 3  */
-		Method(_L03) {
-			//DBGO("\\_GPE\\_L00\n")
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  General event 4  */
-		Method(_L04) {
-		      //DBGO("\\_GPE\\_L04\n")
-		}
-
-		/*  General event 5  */
-		Method(_L05) {
-		      //DBGO("\\_GPE\\_L05\n")
-		}
-
-		/* _L06 General event 6 - Used for GPM6, moved to USB.asl */
-		/* _L07 General event 7 - Used for GPM7, moved to USB.asl */
-
-		/*  Legacy PM event  */
-		Method(_L08) {
-			//DBGO("\\_GPE\\_L08\n")
-		}
-
-		/*  Temp warning (TWarn) event  */
-		Method(_L09) {
-			//DBGO("\\_GPE\\_L09\n")
-			Notify (\_TZ.TZ00, 0x80)
-		}
-
-		/*  Reserved  */
-		Method(_L0A) {
-		      //DBGO("\\_GPE\\_L0A\n")
-		}
-
-		/*  USB controller PME#  */
-		Method(_L0B) {
-			//DBGO("\\_GPE\\_L0B\n")
-			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  AC97 controller PME#  */
-		Method(_L0C) {
-		      //DBGO("\\_GPE\\_L0C\n")
-		}
-
-		/*  OtherTherm PME#  */
-		Method(_L0D) {
-		      //DBGO("\\_GPE\\_L0D\n")
-		}
-
-		/* _L0E GPM9 SCI event - Moved to USB.asl */
-
-		/*  PCIe HotPlug event  */
-		Method(_L0F) {
-			//DBGO("\\_GPE\\_L0F\n")
-		}
-
-		/*  ExtEvent0 SCI event  */
-		Method(_L10) {
-			//DBGO("\\_GPE\\_L10\n")
-		}
-
-
-		/*  ExtEvent1 SCI event  */
-		Method(_L11) {
-			//DBGO("\\_GPE\\_L11\n")
-		}
-
-		/*  PCIe PME# event  */
-		Method(_L12) {
-		      //DBGO("\\_GPE\\_L12\n")
-		}
-
-		/* _L13 GPM0 SCI event - Moved to USB.asl */
-		/* _L14 GPM1 SCI event - Moved to USB.asl */
-		/* _L15 GPM2 SCI event - Moved to USB.asl */
-		/* _L16 GPM3 SCI event - Moved to USB.asl */
-		/* _L17 GPM8 SCI event - Moved to USB.asl */
-
-		/*  GPIO0 or GEvent8 event  */
-		Method(_L18) {
-			//DBGO("\\_GPE\\_L18\n")
-			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBRb, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBRc, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBRd, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/* _L19 GPM4 SCI event - Moved to USB.asl */
-		/* _L1A GPM5 SCI event - Moved to USB.asl */
-
-		/*  Azalia SCI event  */
-		Method(_L1B) {
-			//DBGO("\\_GPE\\_L1B\n")
-			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  GPM6 SCI event - Reassigned to _L06 */
-		Method(_L1C) {
-		      //DBGO("\\_GPE\\_L1C\n")
-		}
-
-		/*  GPM7 SCI event - Reassigned to _L07 */
-		Method(_L1D) {
-		      //DBGO("\\_GPE\\_L1D\n")
-		}
-
-		/*  GPIO2 or GPIO66 SCI event  */
-		Method(_L1E) {
-			//DBGO("\\_GPE\\_L1E\n")
-		}
-
-		/* _L1F SATA SCI event - Moved to sata.asl */
-
-	} 	/* End Scope GPE */
-
-	#include "acpi/usb.asl"
-
-	/* System Bus */
-	Scope(\_SB) { /* Start \_SB scope */
-		#include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
-
-		/*  _SB.PCI0 */
-		/* Note: Only need HID on Primary Bus */
-		Device(PCI0) {
-			External (TOM1) //assigned when update_ssdt()
-			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
-
-			Name(_HID, EISAID("PNP0A03"))
-			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
-			Method(_BBN, 0) { /* Bus number = 0 */
-				Return(0)
-			}
-			Method(_STA, 0) {
-				/* DBGO("\\_SB\\PCI0\\_STA\n") */
-				Return(0x0B)     /* Status is visible */
-			}
-
-			Method(_PRT,0) {
-				If(PMOD){ Return(APR0) }	/* APIC mode */
-				Return (PR0)			/* PIC Mode */
-			} /* end _PRT */
-
-			/* Describe the Northbridge devices */
-			Device(AMRT) {
-				Name(_ADR, 0x00000000)
-			} /* end AMRT */
-
-			/* The external GFX bridge */
-			Device(PBR2) {
-				Name(_ADR, 0x00020000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APS2) }	/* APIC mode */
-					Return (PS2)			/* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR2 */
-
-			/* Dev3 is also an external GFX bridge */
-
-			Device(PBR4) {
-				Name(_ADR, 0x00040000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APS4) }	/* APIC mode */
-					Return (PS4)			/* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR4 */
-
-			Device(PBRb) {
-				Name(_ADR, 0x000b0000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APSb) }	/* APIC mode */
-					Return (PSb)			/* PIC Mode */
-				} /* end _PRT */
-			} /* end PBRb */
-
-			Device(PBRc) {
-				Name(_ADR, 0x000c0000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APSc) }	/* APIC mode */
-					Return (PSc)			/* PIC Mode */
-				} /* end _PRT */
-			} /* end PBRc */
-
-			Device(PBRd) {
-				Name(_ADR, 0x000d0000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APSd) }	/* APIC mode */
-					Return (PSd)			/*  PIC Mode */
-				} /* end _PRT */
-			} /* end PBRd */
-
-			/* PCI slot 1, 2, 3 */
-			Device(PIBR) {
-				Name(_ADR, 0x00140004)
-				Name(_PRW, Package() {0x18, 4})
-
-				Method(_PRT, 0) {
-					Return (PCIB)
-				}
-			}
-
-			/* Describe the Southbridge devices */
-			Device(STCR) {
-				Name(_ADR, 0x00110000)
-				#include "acpi/sata.asl"
-			} /* end STCR */
-
-			Device(UOH1) {
-				Name(_ADR, 0x00130000)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH1 */
-
-			Device(UOH2) {
-				Name(_ADR, 0x00130001)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH2 */
-
-			Device(UOH3) {
-				Name(_ADR, 0x00130002)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH3 */
-
-			Device(UOH4) {
-				Name(_ADR, 0x00130003)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH4 */
-
-			Device(UOH5) {
-				Name(_ADR, 0x00130004)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH5 */
-
-			Device(UEH1) {
-				Name(_ADR, 0x00130005)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UEH1 */
-
-			Device(SBUS) {
-				Name(_ADR, 0x00140000)
-			} /* end SBUS */
-
-			/* Primary (and only) IDE channel */
-			Device(IDEC) {
-				Name(_ADR, 0x00140001)
-				#include "acpi/ide.asl"
-			} /* end IDEC */
-
-			Device(AZHD) {
-				Name(_ADR, 0x00140002)
-				OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
-					Field(AZPD, AnyAcc, NoLock, Preserve) {
-					offset (0x42),
-					NSDI, 1,
-					NSDO, 1,
-					NSEN, 1,
-					offset (0x44),
-					IPCR, 4,
-					offset (0x54),
-					PWST, 2,
-					, 6,
-					PMEB, 1,
-					, 6,
-					PMST, 1,
-					offset (0x62),
-					MMCR, 1,
-					offset (0x64),
-					MMLA, 32,
-					offset (0x68),
-					MMHA, 32,
-					offset (0x6C),
-					MMDT, 16,
-				}
-
-				Method(_INI) {
-					If(LEqual(OSVR,3)){   /* If we are running Linux */
-						Store(zero, NSEN)
-						Store(one, NSDO)
-						Store(one, NSDI)
-					}
-				}
-			} /* end AZHD */
-
-			Device(LIBR) {
-				Name(_ADR, 0x00140003)
-				/* Method(_INI) {
-				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
-				} */ /* End Method(_SB.SBRDG._INI) */
-
-				/* Real Time Clock Device */
-				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
-					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){8}
-						IO(Decode16,0x0070, 0x0070, 0, 2)
-						/* IO(Decode16,0x0070, 0x0070, 0, 4) */
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
-				Device(TMR) {	/* Timer */
-					Name(_HID,EISAID("PNP0100"))	/* System Timer */
-					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){0}
-						IO(Decode16, 0x0040, 0x0040, 0, 4)
-						/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
-				Device(SPKR) {	/* Speaker */
-					Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
-					Name(_CRS, ResourceTemplate() {
-						IO(Decode16, 0x0061, 0x0061, 0, 1)
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
-				Device(PIC) {
-					Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
-					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){2}
-						IO(Decode16,0x0020, 0x0020, 0, 2)
-						IO(Decode16,0x00A0, 0x00A0, 0, 2)
-						/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
-						/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
-				Device(MAD) { /* 8257 DMA */
-					Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
-					Name(_CRS, ResourceTemplate() {
-						DMA(Compatibility,BusMaster,Transfer8){4}
-						IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
-						IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
-						IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
-						IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
-						IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
-						IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
-					}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
-				} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
-				Device(COPR) {
-					Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
-					Name(_CRS, ResourceTemplate() {
-						IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
-						IRQNoFlags(){13}
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
-				Device (PS2M) {
-					Name (_HID, EisaId ("PNP0F13"))
-					Name (_CRS, ResourceTemplate () {
-						IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
-						IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
-						IRQNoFlags () {12}
-					})
-					Method (_STA, 0, NotSerialized) {
-						And (FLG0, 0x04, Local0)
-						If (LEqual (Local0, 0x04)) {
-							Return (0x0F)
-						} Else {
-							Return (0x00)
-						}
-					}
-				}
-
-				Device (PS2K) {
-					Name (_HID, EisaId ("PNP0303"))
-					Method (_STA, 0, NotSerialized) {
-						And (FLG0, 0x04, Local0)
-						If (LEqual (Local0, 0x04)) {
-							Return (0x0F)
-						} Else {
-							Return (0x00)
-						}
-					}
-					Name (_CRS, ResourceTemplate () {
-						IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
-						IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
-						IRQNoFlags () {1}
-					})
-				}
-
-#if 0 //acpi_create_hpet
-				Device(HPET) {
-					Name(_HID,EISAID("PNP0103"))
-					Name(CRS, ResourceTemplate() {
-		    				IRQNoFlags () {0}
-		    				IRQNoFlags () {2}
-		   			 	IRQNoFlags () {8}
-						Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, MNT)	/* 1kb reserved space */
-					})
-					Method(_STA, 0, NotSerialized) {
-						Return(0x0F) /* sata is visible */
-					}
-					Method(_CRS, 0, NotSerialized) {
-						CreateDwordField(CRS, ^MNT._BAS, HPT)
-						Store(HPBA, HPT)
-						Return(CRS)
-					}
-				} /* End Device(_SB.PCI0.LIBR.HPET) */
-#endif
-			} /* end LIBR */
-
-			Device(HPBR) {
-				Name(_ADR, 0x00140004)
-			} /* end HostPciBr */
-
-			Device(ACAD) {
-				Name(_ADR, 0x00140005)
-			} /* end Ac97audio */
-
-			Device(ACMD) {
-				Name(_ADR, 0x00140006)
-			} /* end Ac97modem */
-
-			/* ITE8718 Support */
-			OperationRegion (IOID, SystemIO, 0x2E, 0x02)	/* sometimes it is 0x4E */
-				Field (IOID, ByteAcc, NoLock, Preserve)
-				{
-					SIOI,   8,    SIOD,   8		/* 0x2E and 0x2F */
-				}
-
-			IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
-			{
-					Offset (0x07),
-				LDN,	8,	/* Logical Device Number */
-					Offset (0x20),
-				CID1,	8,	/* Chip ID Byte 1, 0x87 */
-				CID2,	8,	/* Chip ID Byte 2, 0x12 */
-					Offset (0x30),
-				ACTR,	8,	/* Function activate */
-					Offset (0xF0),
-				APC0,	8,	/* APC/PME Event Enable Register */
-				APC1,	8,	/* APC/PME Status Register */
-				APC2,	8,	/* APC/PME Control Register 1 */
-				APC3,	8,	/* Environment Controller Special Configuration Register */
-				APC4,	8	/* APC/PME Control Register 2 */
-			}
-
-			/* Enter the 8718 MB PnP Mode */
-			Method (EPNP)
-			{
-				Store(0x87, SIOI)
-				Store(0x01, SIOI)
-				Store(0x55, SIOI)
-				Store(0x55, SIOI) /* 8718 magic number */
-			}
-			/* Exit the 8718 MB PnP Mode */
-			Method (XPNP)
-			{
-				Store (0x02, SIOI)
-				Store (0x02, SIOD)
-			}
-			/*
-			 * Keyboard PME is routed to SB700 Gevent3. We can wake
-			 * up the system by pressing the key.
-			 */
-			Method (SIOS, 1)
-			{
-				/* We only enable KBD PME for S5. */
-				If (LLess (Arg0, 0x05))
-				{
-					EPNP()
-					/* DBGO("8718F\n") */
-
-					Store (0x4, LDN)
-					Store (One, ACTR)  /* Enable EC */
-					/*
-					Store (0x4, LDN)
-					Store (0x04, APC4)
-					*/  /* falling edge. which mode? Not sure. */
-
-					Store (0x4, LDN)
-					Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
-					Store (0x4, LDN)
-					Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
-
-					XPNP()
-				}
-			}
-			Method (SIOW, 1)
-			{
-				EPNP()
-				Store (0x4, LDN)
-				Store (Zero, APC0) /* disable keyboard PME */
-				Store (0x4, LDN)
-				Store (0xFF, APC1) /* clear keyboard PME status */
-				XPNP()
-			}
-
-			Name (CRS, ResourceTemplate ()
-			{
-				WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
-					0x0000,             // Granularity
-					0x0000,             // Range Minimum
-					0x00FF,             // Range Maximum
-					0x0000,             // Translation Offset
-					0x0100,             // Length
-					,,)
-				IO (Decode16,
-					0x0CF8,             // Range Minimum
-					0x0CF8,             // Range Maximum
-					0x01,               // Alignment
-					0x08,               // Length
-					)
-
-				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,             // Granularity
-					0x0000,             // Range Minimum
-					0x03AF,             // Range Maximum
-					0x0000,             // Translation Offset
-					0x03B0,             // Length
-					,, , TypeStatic)
-				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,             // Granularity
-					0x03E0,             // Range Minimum
-					0x0CF7,             // Range Maximum
-					0x0000,             // Translation Offset
-					0x0918,             // Length
-					,, , TypeStatic)
-
-				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,             // Granularity
-					0x03B0,             // Range Minimum
-					0x03BB,             // Range Maximum
-					0x0000,             // Translation Offset
-					0x000C,             // Length
-					,, , TypeStatic)
-				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,             // Granularity
-					0x03C0,             // Range Minimum
-					0x03DF,             // Range Maximum
-					0x0000,             // Translation Offset
-					0x0020,             // Length
-					,, , TypeStatic)
-				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,             // Granularity
-					0x0D00,             // Range Minimum
-					0xFFFF,             // Range Maximum
-					0x0000,             // Translation Offset
-					0xF300,             // Length
-					,, , TypeStatic)
-				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	// VGA memory space
-
-				Memory32Fixed (ReadOnly,
-						0xE0000000,         // Address Base
-						0x10000000,         // Address Length, (1MB each Bus, 256 Buses by default)
-						MMIO)
-			})
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1)
-				CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1)
-
-				/*
-				 * Declare memory between TOM1 and 4GB as available
-				 * for PCI MMIO.
-				 * Use ShiftLeft to avoid 64bit constant (for XP).
-				 * This will work even if the OS does 32bit arithmetic, as
-				 * 32bit (0x00000000 - TOM1) will wrap and give the same
-				 * result as 64bit (0x100000000 - TOM1).
-				 */
-				Store(TOM1, BAS1)
-				ShiftLeft(0x10000000, 4, Local0)
-				Subtract(Local0, TOM1, Local0)
-				Store(Local0, LEN1)
-				//DBGO(TOM1)
-
-				Return (CRS)
-			}
-
-			/*
-			 *
-			 *               FIRST METHOD CALLED UPON BOOT
-			 *
-			 *  1. If debugging, print current OS and ACPI interpreter.
-			 *  2. Get PCI Interrupt routing from ACPI VSM, this
-			 *     value is based on user choice in BIOS setup.
-			 */
-			Method(_INI, 0) {
-				/* DBGO("\\_SB\\_INI\n") */
-				/* DBGO("   DSDT.ASL code from ") */
-				/* DBGO(__DATE__) */
-				/* DBGO(" ") */
-				/* DBGO(__TIME__) */
-				/* DBGO("\n   Sleep states supported: ") */
-				/* DBGO("\n") */
-				/* DBGO("   \\_OS=") */
-				/* DBGO(\_OS) */
-				/* DBGO("\n   \\_REV=") */
-				/* DBGO(\_REV) */
-				/* DBGO("\n") */
-
-				/* Determine the OS we're running on */
-				OSFL()
-				/* On older chips, clear PciExpWakeDisEn */
-				/*if (LLessEqual(\SBRI, 0x13)) {
-				 *    	Store(0,\PWDE)
-				 *}
-				 */
-			} /* End Method(_SB._INI) */
-		} /* End Device(PCI0)  */
-
-		Device(PWRB) {	/* Start Power button device */
-			Name(_HID, EISAID("PNP0C0C"))
-			Name(_UID, 0xAA)
-			Name(_PRW, Package () {3, 0x04})	/* wake from S1-S4 */
-			Name(_STA, 0x0B) /* sata is invisible */
-		}
-	} /* End \_SB scope */
-
-	Scope(\_SI) {
-		Method(_SST, 1) {
-			/* DBGO("\\_SI\\_SST\n") */
-			/* DBGO("   New Indicator state: ") */
-			/* DBGO(Arg0) */
-			/* DBGO("\n") */
-		}
-	} /* End Scope SI */
-
-	#include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
-
-	/* THERMAL */
-	Scope(\_TZ) {
-		Name (KELV, 2732)
-		Name (THOT, 800)
-		Name (TCRT, 850)
-
-		ThermalZone(TZ00) {
-			Method(_AC0,0) {	/* Active Cooling 0 (0=highest fan speed) */
-				/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
-				Return(Add(0, 2730))
-			}
-			Method(_AL0,0) {	/* Returns package of cooling device to turn on */
-				/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
-				Return(Package() {\_TZ.TZ00.FAN0})
-			}
-			Device (FAN0) {
-				Name(_HID, EISAID("PNP0C0B"))
-				Name(_PR0, Package() {PFN0})
-			}
-
-			PowerResource(PFN0,0,0) {
-				Method(_STA) {
-					Store(0xF,Local0)
-					Return(Local0)
-				}
-				Method(_ON) {
-					/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
-				}
-				Method(_OFF) {
-					/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
-				}
-			}
-
-			Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
-				/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
-				Return (Add (THOT, KELV))
-			}
-			Method(_CRT,0) {	/* return critical temp in tenths degree Kelvin */
-				/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
-				Return (Add (TCRT, KELV))
-			}
-			Method(_TMP,0) {	/* return current temp of this zone */
-				Store (SMBR (0x07, 0x4C,, 0x00), Local0)
-				If (LGreater (Local0, 0x10)) {
-					Store (Local0, Local1)
-				}
-				Else {
-					Add (Local0, THOT, Local0)
-					Return (Add (400, KELV))
-				}
-
-				Store (SMBR (0x07, 0x4C, 0x01), Local0)
-				/* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
-				/* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
-				If (LGreater (Local0, 0x10)) {
-					If (LGreater (Local0, Local1)) {
-						Store (Local0, Local1)
-					}
-
-					Multiply (Local1, 10, Local1)
-					Return (Add (Local1, KELV))
-				}
-				Else {
-					Add (Local0, THOT, Local0)
-					Return (Add (400 , KELV))
-				}
-			} /* end of _TMP */
-		} /* end of TZ00 */
-	}
-}
-/* End of ASL file */
diff --git a/src/mainboard/supermicro/h8scm/fadt.c b/src/mainboard/supermicro/h8scm/fadt.c
deleted file mode 100644
index fda488f7fe..0000000000
--- a/src/mainboard/supermicro/h8scm/fadt.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- */
-
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include "Platform.h" /*sb700 platform header*/
-
-#ifndef ACPI_BLK_BASE
-  #define ACPI_BLK_BASE	PM1_EVT_BLK_ADDRESS
-#endif
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
-	acpi_header_t *header = &(fadt->header);
-
-	printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
-	/* Prepare the header */
-	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
-	memcpy(header->signature, "FACP", 4);
-	header->length = 244;
-	header->revision = 3;
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, "AMD     ", 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-	header->asl_compiler_revision = 0;
-
-	if ((uintptr_t)facs > 0xffffffff)
-		printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n");
-	else
-		fadt->firmware_ctrl = (uintptr_t)facs;
-
-	if ((uintptr_t)dsdt > 0xffffffff)
-		printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n");
-	else
-		fadt->dsdt = (uintptr_t)dsdt;
-
-	/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
-	fadt->preferred_pm_profile = 0x03;
-	fadt->sci_int = 9;
-	/* disable system management mode by setting to 0: */
-	fadt->smi_cmd = 0;
-	fadt->acpi_enable = 0xf0;
-	fadt->acpi_disable = 0xf1;
-	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = 0xe2;
-
-	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
-	outl(0x1, PM1_CNT_BLK_ADDRESS);           /* set SCI_EN */
-	fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
-	fadt->pm1b_evt_blk = 0x0000;
-	fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
-	fadt->pm1b_cnt_blk = 0x0000;
-	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
-	fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
-	fadt->gpe0_blk = GPE0_BLK_ADDRESS;
-	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
-
-	fadt->pm1_evt_len = 4;
-	fadt->pm1_cnt_len = 2;
-	fadt->pm2_cnt_len = 1;
-	fadt->pm_tmr_len = 4;
-	fadt->gpe0_blk_len = 8;
-	fadt->gpe1_blk_len = 0;
-	fadt->gpe1_base = 0;
-
-	fadt->cst_cnt = 0xe3;
-	fadt->p_lvl2_lat = 101;
-	fadt->p_lvl3_lat = 1001;
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
-	fadt->duty_offset = 1;
-	fadt->duty_width = 3;
-	fadt->day_alrm = 0;	/* 0x7d these have to be */
-	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
-	fadt->century = 0;	/* 0x7f to make rtc alrm work */
-	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
-	fadt->flags = 0x0001c1a5;/* 0x25; */
-
-	fadt->res2 = 0;
-
-	fadt->reset_reg.space_id = 1;
-	fadt->reset_reg.bit_width = 8;
-	fadt->reset_reg.bit_offset = 0;
-	fadt->reset_reg.resv = 0;
-	fadt->reset_reg.addrl = 0xcf9;
-	fadt->reset_reg.addrh = 0x0;
-
-	fadt->reset_value = 6;
-	fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff;
-	fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32;
-	fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff;
-	fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32;
-
-	fadt->x_pm1a_evt_blk.space_id = 1;
-	fadt->x_pm1a_evt_blk.bit_width = 32;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.resv = 0;
-	fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
-	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_evt_blk.space_id = 1;
-	fadt->x_pm1b_evt_blk.bit_width = 4;
-	fadt->x_pm1b_evt_blk.bit_offset = 0;
-	fadt->x_pm1b_evt_blk.resv = 0;
-	fadt->x_pm1b_evt_blk.addrl = 0x0;
-	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-
-	fadt->x_pm1a_cnt_blk.space_id = 1;
-	fadt->x_pm1a_cnt_blk.bit_width = 16;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.resv = 0;
-	fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
-	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_cnt_blk.space_id = 1;
-	fadt->x_pm1b_cnt_blk.bit_width = 2;
-	fadt->x_pm1b_cnt_blk.bit_offset = 0;
-	fadt->x_pm1b_cnt_blk.resv = 0;
-	fadt->x_pm1b_cnt_blk.addrl = 0x0;
-	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-
-	fadt->x_pm2_cnt_blk.space_id = 1;
-	fadt->x_pm2_cnt_blk.bit_width = 0;
-	fadt->x_pm2_cnt_blk.bit_offset = 0;
-	fadt->x_pm2_cnt_blk.resv = 0;
-	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
-	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-
-	fadt->x_pm_tmr_blk.space_id = 1;
-	fadt->x_pm_tmr_blk.bit_width = 32;
-	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.resv = 0;
-	fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
-	fadt->x_pm_tmr_blk.addrh = 0x0;
-
-
-	fadt->x_gpe0_blk.space_id = 1;
-	fadt->x_gpe0_blk.bit_width = 32;
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.resv = 0;
-	fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
-	fadt->x_gpe0_blk.addrh = 0x0;
-
-
-	fadt->x_gpe1_blk.space_id = 1;
-	fadt->x_gpe1_blk.bit_width = 0;
-	fadt->x_gpe1_blk.bit_offset = 0;
-	fadt->x_gpe1_blk.resv = 0;
-	fadt->x_gpe1_blk.addrl = 0;
-	fadt->x_gpe1_blk.addrh = 0x0;
-
-	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-}
diff --git a/src/mainboard/supermicro/h8scm/irq_tables.c b/src/mainboard/supermicro/h8scm/irq_tables.c
deleted file mode 100644
index 0897945e81..0000000000
--- a/src/mainboard/supermicro/h8scm/irq_tables.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr += 15;
-	addr &= ~15;
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/supermicro/h8scm/mainboard.c b/src/mainboard/supermicro/h8scm/mainboard.c
deleted file mode 100644
index 378acc9b98..0000000000
--- a/src/mainboard/supermicro/h8scm/mainboard.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <device/pci_def.h>
-#include <NbPlatform.h>
-#include "chip.h"
-
-void set_pcie_dereset(void *nbconfig);
-void set_pcie_reset(void *nbconfig);
-
-/**
- *
- */
-void set_pcie_reset(void *nbconfig)
-{
-}
-
-/**
- * Mainboard specific RD890 CIMx callback
- * Release Resets to PCIe Links
- * For Both SR56X0 chips, PCIE_RESET_GPIO1 to reset pcie
- */
-void set_pcie_dereset(void *nbconfig)
-{
-	//u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
-	u32 i;
-	u32 val;
-	u32 nb_addr;
-
-	val = 0x00000007UL;
-	AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig;
-	for (i = 0; i < MAX_NB_COUNT; i ++) {
-		nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX;
-		LibNbPciIndexRMW(nb_addr,
-				NB_HTIU_REGA8,
-				AccessS3SaveWidth32,
-				~val,
-				val,
-				 &(pConfig->Northbridges[i]));
-	}
-}
-
-
-/*************************************************
- * enable the dedicated function in h8scm board.
- *************************************************/
-static void mainboard_enable(device_t dev)
-{
-	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-}
-
-struct chip_operations mainboard_ops = {
-		.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c
deleted file mode 100644
index 417f677955..0000000000
--- a/src/mainboard/supermicro/h8scm/mptable.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-	u32 apicid_sp5100;
-	u32 apicid_sr5650;
-	device_t dev;
-	u32 *dword;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/*
-	 * AGESA v5 Apply apic enumeration rules
-	 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
-	 * put the local-APICs at m..z
-	 * For systems with < 16 APICs, put the Local-APICs at 0..n and
-	 * put the IO-APICs at (n + 1)..z
-	 */
-	if (CONFIG_MAX_CPUS >= 16)
-		apicid_sp5100 = 0x0;
-	else
-		apicid_sp5100 = CONFIG_MAX_CPUS + 1;
-	apicid_sr5650 = apicid_sp5100 + 1;
-
-	dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	if (dev) {
-		/* Set SP5100 IOAPIC ID */
-		dword = (u32 *)(uintptr_t)(pci_read_config32(dev, 0x74) & 0xfffffff0);
-		smp_write_ioapic(mc, apicid_sp5100, 0x20, dword);
-
-#ifdef UNUSED_CODE
-		u8 byte;
-		/* Initialize interrupt mapping */
-		/* aza */
-		byte = pci_read_config8(dev, 0x63);
-		byte &= 0xf8;
-		byte |= 0; /* 0: INTA, ...., 7: INTH */
-		pci_write_config8(dev, 0x63, byte);
-		/* SATA */
-		dword = (u32 *)pci_read_config32(dev, 0xAC);
-		dword = dword & ~(7 << 26);
-		dword = dword | (6 << 26); /* 0: INTA, ...., 7: INTH */
-		/* dword |= 1 << 22; PIC and APIC co exists */
-		pci_write_config32(dev, 0xAC, dword);
-#endif
-
-		/*
-		 * 00:12.0: PROG SATA : INT F
-		 * 00:13.0: INTA USB_0
-		 * 00:13.1: INTB USB_1
-		 * 00:13.2: INTC USB_2
-		 * 00:13.3: INTD USB_3
-		 * 00:13.4: INTC USB_4
-		 * 00:13.5: INTD USB2
-		 * 00:14.1: INTA IDE
-		 * 00:14.2: Prog HDA : INT E
-		 * 00:14.5: INTB ACI
-		 * 00:14.6: INTB MCI
-		 */
-
-		/* Set RS5650 IOAPIC ID */
-		dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-		if (dev) {
-			pci_write_config32(dev, 0xF8, 0x1);
-			dword = (u32 *)(uintptr_t)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
-			smp_write_ioapic(mc, apicid_sr5650, 0x20, dword);
-		}
-
-	}
-
-	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
-	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0);
-
-	/* PCI interrupts are level triggered, and are
-	 * associated with a specific bus/device/function tuple.
-	 */
-#define PCI_INT(bus, dev, int_sign, pin) \
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sp5100, (pin))
-
-	/* SMBUS */
-	//PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0
-
-	/* HD Audio */
-	PCI_INT(0x0, 0x14, 0x2, 0x10);
-
-	/* USB */
-	/* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */
-	/* EHCI hard-wired to 02h, corresponding to using INTB# */
-	/* USB1 */
-	PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */
-	PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */
-	PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */
-
-	/* USB2 */
-	PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */
-	PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */
-	PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */
-
-	/* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */
-	PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */
-
-	/* SATA */
-	PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
-
-	/* PCI slots */
-	dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-	if (dev && dev->enabled) {
-		u8 bus_pci = dev->link_list->secondary;
-		/* PCI_SLOT 0. */
-		PCI_INT(bus_pci, 0x5, 0x0, 0x14);
-		PCI_INT(bus_pci, 0x5, 0x1, 0x15);
-		PCI_INT(bus_pci, 0x5, 0x2, 0x16);
-		PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
-		/* PCI_SLOT 1. */
-		PCI_INT(bus_pci, 0x6, 0x0, 0x15);
-		PCI_INT(bus_pci, 0x6, 0x1, 0x16);
-		PCI_INT(bus_pci, 0x6, 0x2, 0x17);
-		PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
-		/* PCI_SLOT 2. */
-		PCI_INT(bus_pci, 0x7, 0x0, 0x16);
-		PCI_INT(bus_pci, 0x7, 0x1, 0x17);
-		PCI_INT(bus_pci, 0x7, 0x2, 0x14);
-		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
-	}
-
-	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
-	IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/supermicro/h8scm/platform_cfg.h b/src/mainboard/supermicro/h8scm/platform_cfg.h
deleted file mode 100644
index f5a5c73882..0000000000
--- a/src/mainboard/supermicro/h8scm/platform_cfg.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-
-/* northbridge customize options */
-/**
- * Max number of northbridges in the system
- */
-#define MAX_NB_COUNT		1 //TODO: only 1 NB tested
-
-/**
- *  Enable check for PCIe endpoint to be ready for PCI enumeration.
- *
- */
-//#define EPREADY_WORKAROUND_DISABLED
-
-/**
- *  Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table.
- *
- */
-#define IOMMU_SUPPORT_DISABLE //TODO: enable it
-
-/**
- *  Disable server PCIe hotplug support.
- */
-
-//#define HOTPLUG_SUPPORT_DISABLED
-
-/**
- *  Disable support for device number remapping for PCIe portsserver PCIe hotplug support.
- */
-
-//#define DEVICE_REMAP_DISABLE
-
-#endif //_PLATFORM_CFG_H_
diff --git a/src/mainboard/supermicro/h8scm/rd890_cfg.c b/src/mainboard/supermicro/h8scm/rd890_cfg.c
deleted file mode 100644
index 9bbb02a50c..0000000000
--- a/src/mainboard/supermicro/h8scm/rd890_cfg.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "NbPlatform.h"
-#include "rd890_cfg.h"
-#include "northbridge/amd/cimx/rd890/chip.h"
-#include "nbInitializer.h"
-#include <string.h>
-#include <arch/ioapic.h>
-
-#ifndef __PRE_RAM__
-#include <device/device.h>
-extern void set_pcie_reset(void *config);
-extern void set_pcie_dereset(void *config);
-
-/**
- * Platform dependent configuration at ramstage
- */
-static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr)
-{
-	u16 i;
-	PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig;
-	//AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr);
-	struct northbridge_amd_cimx_rd890_config *rd890_info = NULL;
-	DEFAULT_PLATFORM_CONFIG(platform_config);
-
-	/* update the platform depentent configuration by devicetree */
-	rd890_info  = nb_dev->chip_info;
-	platform_config.PortEnableMap = rd890_info->port_enable;
-	if (rd890_info->gpp1_configuration == 0) {
-		platform_config.Gpp1Config = GFX_CONFIG_AAAA;
-	} else if (rd890_info->gpp1_configuration == 1) {
-		platform_config.Gpp1Config = GFX_CONFIG_AABB;
-	}
-	if (rd890_info->gpp2_configuration == 0) {
-		platform_config.Gpp2Config = GFX_CONFIG_AAAA;
-	} else if (rd890_info->gpp2_configuration == 1) {
-		platform_config.Gpp2Config = GFX_CONFIG_AABB;
-	}
-	platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration;
-
-	if (platform_config.Gpp1Config != 0) {
-		pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config;
-	}
-	if (platform_config.Gpp2Config != 0) {
-		pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config;
-	}
-	if (platform_config.Gpp3aConfig != 0) {
-		pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig;
-	}
-
-	pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20);
-	for (i = 0; i <= MAX_CORE_ID; i++) {
-		NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF;
-		NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF;
-	}
-	for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
-		NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2;
-	}
-
-	for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
-		if ((platform_config.PortEnableMap & (1 << i)) != 0) {
-			pPcieConfig->PortConfiguration[i].PortPresent = ON;
-			if ((platform_config.PortGen1Map & (1 << i)) != 0) {
-				pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1;
-			}
-			if ((platform_config.PortHotplugMap & (1 << i)) != 0) {
-				u16 j;
-				pPcieConfig->PortConfiguration[i].PortHotplug = ON; /* Enable Hotplug */
-				/* Set Hotplug descriptor info */
-				for (j = 0; j < 8; j++) {
-					u32 PortDescriptor;
-					PortDescriptor = platform_config.PortHotplugDescriptors[j];
-					if ((PortDescriptor & 0xF) == j) {
-						pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap  = (PortDescriptor >> 4)  & 3;
-						pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6)  & 1;
-						break;
-					}
-				}
-			}
-		}
-	}
-}
-#endif // __PRE_RAM__
-
-/**
- * @brief Entry point of Northbridge CIMx callout/CallBack
- *
- * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr);
- *
- * @param[in] func     Northbridge CIMx CallBackId
- * @param[in] data     Northbridge Input Data.
- * @param[in] *config  Northbridge configuration structure pointer.
- *
- */
-static u32 rd890_callout_entry(u32 func, uintptr_t data, void *config)
-{
-	u32 ret = 0;
-#ifndef __PRE_RAM__
-	device_t nb_dev = (device_t)data;
-#endif
-	AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config;
-
-	switch (func) {
-		case PHCB_AmdPortTrainingCompleted:
-			break;
-
-		case PHCB_AmdPortResetDeassert:
-#ifndef __PRE_RAM__
-			set_pcie_dereset(config);
-#endif
-			break;
-
-		case PHCB_AmdPortResetAssert:
-#ifndef __PRE_RAM__
-			set_pcie_reset(config);
-#endif
-			break;
-
-		case PHCB_AmdPortResetSupported:
-			break;
-		case PHCB_AmdGeneratePciReset:
-			break;
-		case PHCB_AmdGetExclusionTable:
-			break;
-		case PHCB_AmdAllocateBuffer:
-			break;
-		case PHCB_AmdUpdateApicInterruptMapping:
-			break;
-		case PHCB_AmdFreeBuffer:
-			break;
-		case PHCB_AmdLocateBuffer:
-			break;
-		case PHCB_AmdReportEvent:
-			break;
-		case PHCB_AmdPcieAsmpInfo:
-			break;
-
-		case CB_AmdSetNbPorConfig:
-			break;
-		case CB_AmdSetHtConfig:
-			/*TODO: different HT path and deempasis for each NB */
-			nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES;
-
-			break;
-		case CB_AmdSetPcieEarlyConfig:
-#ifndef __PRE_RAM__
-			nb_platform_config(nb_dev, nbConfigPtr);
-#endif
-			break;
-
-		case CB_AmdSetEarlyPostConfig:
-			break;
-
-		case CB_AmdSetMidPostConfig:
-			nbConfigPtr->pNbConfig->IoApicBaseAddress = IO_APIC_ADDR;
-#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu
-			/* SBIOS must alloc 16K memory for IOMMU MMIO */
-			UINT32  MmcfgBarAddress; //using default IOmmuBaseAddress
-			LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C,
-					AccessWidth32,
-					&MmcfgBarAddress,
-					nbConfigPtr);
-			MmcfgBarAddress &= ~0xf;
-			if (MmcfgBarAddress != 0) {
-				nbConfigPtr->IommuBaseAddress = MmcfgBarAddress;
-			}
-			nbConfigPtr->IommuBaseAddress = 0; //disable iommu
-#endif
-			break;
-
-		case CB_AmdSetLatePostConfig:
-			break;
-
-		case CB_AmdSetRecoveryConfig:
-			break;
-	}
-
-	return ret;
-}
-
-
-/**
- * @brief North Bridge CIMx configuration
- *
- * should be called before exeucte CIMx function.
- * this function will be called in romstage and ramstage.
- */
-void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig)
-{
-	u16 i = 0;
-	PCI_ADDR PciAddress;
-	u32 val, sbNode, sbLink;
-
-	if (!pConfig) {
-		return;
-	}
-
-	memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK));
-	for (i = 0; i < MAX_NB_COUNT; i++) {
-		pConfig->Northbridges[i].pNbConfig	= &nbConfig[i];
-		pConfig->Northbridges[i].pHtConfig	= &htConfig[i];
-		pConfig->Northbridges[i].pPcieConfig	= &pcieConfig[i];
-		pConfig->Northbridges[i].ConfigPtr	= &pConfig;
-	}
-
-	/* Initialize all NB structures */
-	AmdInitializer(pConfig);
-
-	pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
-	pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
-	pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;
-
-	/*
-	 * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform.
-	 * Always 0:0:0 on single NB platform.
-	 */
-	pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
-
-	/* Set HT path to NB by SbNode and SbLink */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
-	LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
-	sbNode = (val >> 8) & 0x07;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
-	LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
-	sbLink = (val >> 8) & 0x07; //assum ganged
-	pConfig->Northbridges[0].NbHtPath.NodeID = sbNode;
-	pConfig->Northbridges[0].NbHtPath.LinkID = sbLink;
-	//TODO: other NBs
-
-#ifndef __PRE_RAM__
-	/* If temporrary MMIO enable set up CPU MMIO */
-	for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) {
-		UINT32  MmioBase;
-		UINT32  LinkId;
-		UINT32  SubLinkId;
-		MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress;
-		if (MmioBase != 0) {
-			LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf;
-			SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0;
-			/* Set Limit */
-			LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84),
-					AccessWidth32,
-					0x0,
-					((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6),
-					&(pConfig->Northbridges[i]));
-			/* Set Base */
-			LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80),
-					AccessWidth32,
-					0x0,
-					(MmioBase << 12) | 0x3,
-					&(pConfig->Northbridges[i]));
-		}
-	}
-#endif
-}
diff --git a/src/mainboard/supermicro/h8scm/rd890_cfg.h b/src/mainboard/supermicro/h8scm/rd890_cfg.h
deleted file mode 100644
index 0227c3f54d..0000000000
--- a/src/mainboard/supermicro/h8scm/rd890_cfg.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef  _RD890_CFG_H_
-#define _RD890_CFG_H_
-
-#include "NbPlatform.h"
-
-/* platform dependent configuration default value */
-
-/**
- * Path from CPU to NB
- * [0..7]   - Node  (0..8)
- * [8..11]  - Link  (0..3)
- * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
- */
-#ifndef DEFAULT_HT_PATH
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
-#define DEFAULT_HT_PATH		{0x0, 0x1}
-#else /* FAMILY10 */
-#define DEFAULT_HT_PATH		{0x0, 0x3}
-#endif
-#endif
-
-/**
- * Bitmap of enabled ports on NB #0/1/2/3
- * Bit[0] - Reserved
- * Bit[1] - Reserved
- * Bit[2] - Enable PCIe port 2
- * Bit[3] - Enable PCIe port 3
- * Bit[4] - Enable PCIe port 4
- * Bit[5] - Enable PCIe port 5
- * Bit[6] - Enable PCIe port 2
- * Bit[7] - Enable PCIe port 7
- * Bit[8] - Reserved
- * Bit[9] - Enable PCIe port 9
- * Bit[10]- Enable PCIe port 10
- * Bit[11]- Enable PCIe port 11
- * Bit[12]- Enable PCIe port 12
- * Bit[13]- Enable PCIe port 13
- * Example:
- *  port_enable = 0x14
- *  Port 2 and 4 enabled for training/initialization
- */
-#ifndef DEFAULT_PORT_ENABLE_MAP
-#define DEFAULT_PORT_ENABLE_MAP		0x0014
-#endif
-
-/**
- * Bitmap of ports that have slot or onboard device connected.
- * Example force PCIe Gen1 supporton port 2 and 4  (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4)
- * define DEFAULT_PORT_FORCE_GEN1        0x604
- */
-#ifndef DEFAULT_PORT_FORCE_GEN1
-#define DEFAULT_PORT_FORCE_GEN1		0x0
-#endif
-
-/**
- * Bitmap of ports that have server hotplug support
- */
-#ifndef DEFAULT_HOTPLUG_SUPPORT
-#define DEFAULT_HOTPLUG_SUPPORT		0x0
-#endif
-
-#ifndef DEFAULT_HOTPLUG_DESCRIPTOR
-#define DEFAULT_HOTPLUG_DESCRIPTOR		{0, 0, 0, 0, 0, 0, 0, 0}
-#endif
-
-#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS
-#define DEFAULT_TEMPMMIO_BASE_ADDRESS		0xD0000000
-#endif
-
-/**
- * Default GPP1 core configuraton on NB #0/1/2/3.
- *  2  x8 slot, GFX_CONFIG_AABB
- *  1 x16 slot, GFX_CONFIG_AAAA
- */
-#ifndef DEFAULT_GPP1_CONFIG
-#define DEFAULT_GPP1_CONFIG		GFX_CONFIG_AABB
-#endif
-
-/**
- * Default GPP2 core configuraton on NB #0/1/2/3.
- *  2  x8 slot, GFX_CONFIG_AABB
- *  1 x16 slot, GFX_CONFIG_AAAA
- */
-#ifndef DEFAULT_GPP2_CONFIG
-#define DEFAULT_GPP2_CONFIG		GFX_CONFIG_AABB
-#endif
-
-/**
- * Default GPP3a core configuraton on NB #0/1/2/3.
- * 4:2:0:0:0:0   - GPP_CONFIG_GPP420000, 0x1
- * 4:1:1:0:0:0   - GPP_CONFIG_GPP411000, 0x2
- * 2:2:2:0:0:0   - GPP_CONFIG_GPP222000, 0x3
- * 2:2:1:1:0:0   - GPP_CONFIG_GPP221100, 0x4
- * 2:1:1:1:1:0   - GPP_CONFIG_GPP211110, 0x5
- * 1:1:1:1:1:1   - GPP_CONFIG_GPP111111, 0x6
- */
-#ifndef DEFAULT_GPP3A_CONFIG
-#define DEFAULT_GPP3A_CONFIG		GPP_CONFIG_GPP111111
-#endif
-
-
-/**
- * Default HT Transmitter de-emphasis setting
- */
-#ifndef DEFAULT_HT_DEEMPASIES
-#define DEFAULT_HT_DEEMPASIES		0x3
-#endif
-
-/**
- * Default APIC nterrupt base for IOAPIC
- */
-#ifndef DEFAULT_APIC_INTERRUPT_BASE
-#define DEFAULT_APIC_INTERRUPT_BASE	24
-#endif
-
-
-#define DEFAULT_PLATFORM_CONFIG(name) \
-	NB_PLATFORM_CONFIG name = { \
-		DEFAULT_PORT_ENABLE_MAP, \
-		DEFAULT_PORT_FORCE_GEN1, \
-		DEFAULT_HOTPLUG_SUPPORT, \
-		DEFAULT_HOTPLUG_DESCRIPTOR, \
-		DEFAULT_TEMPMMIO_BASE_ADDRESS, \
-		DEFAULT_GPP1_CONFIG, \
-		DEFAULT_GPP2_CONFIG, \
-		DEFAULT_GPP3A_CONFIG, \
-		DEFAULT_HT_DEEMPASIES, \
-		/*DEFAULT_HT_PATH,*/ \
-		DEFAULT_APIC_INTERRUPT_BASE, \
-	}
-
-/**
- * Platform configuration
- */
-typedef struct {
-	UINT16  PortEnableMap;            ///< Bitmap of enabled ports
-	UINT16  PortGen1Map;              ///< Bitmap of ports to disable Gen2
-	UINT16  PortHotplugMap;           ///< Bitmap of ports support hotplug
-	UINT8   PortHotplugDescriptors[8];///< Ports Hotplug descriptors
-	UINT32  TemporaryMmio;            ///< Temporary MMIO
-	UINT32  Gpp1Config;               ///< Default PCIe GFX core configuration
-	UINT32  Gpp2Config;               ///< Default PCIe GPP2 core configuration
-	UINT32  Gpp3aConfig;              ///< Default PCIe GPP3a core configuration
-	UINT8   NbTransmitterDeemphasis;  ///< HT transmitter de-emphasis level
-	//	HT_PATH NbHtPath;                 ///< HT path to NB
-	UINT8   GlobalApicInterruptBase;  ///< Global APIC interrupt base that is used in MADT table for IO APIC.
-} NB_PLATFORM_CONFIG;
-
-/**
- * Bridge CIMx configuration
- */
-void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig);
-
-#endif //_RD890_CFG_H_
diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c
deleted file mode 100644
index bee430ac4e..0000000000
--- a/src/mainboard/supermicro/h8scm/romstage.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <lib.h>
-#include <reset.h>
-#include <stdint.h>
-#include <arch/io.h>
-#include <arch/cpu.h>
-#include <console/console.h>
-#include <arch/stages.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <northbridge/amd/agesa/family15/reset_test.h>
-#include <nb_cimx.h>
-#include <sb_cimx.h>
-#include <superio/nuvoton/wpcm450/wpcm450.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627dhg/w83627dhg.h>
-
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
-#define DUMMY_DEV PNP_DEV(0x2e, 0)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	u32 val;
-
-	/* Must come first to enable PCI MMCONF. */
-	amd_initmmio();
-
-	post_code(0x31);
-
-	/* Halt if there was a built in self test failure */
-	post_code(0x33);
-	report_bist_failure(bist);
-
-	sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
-	wpcm450_enable_dev(WPCM450_SP1, 0x164E, CONFIG_TTYS0_BASE);
-	sb7xx_51xx_disable_wideio(0);
-	post_code(0x34);
-
-	post_code(0x35);
-	console_init();
-
-	val = cpuid_eax(1);
-	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
-	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
-	post_code(0x37);
-	agesawrapper_amdinitreset();
-
-	if (!cpu_init_detectedx && boot_cpu()) {
-		post_code(0x38);
-		/*
-		 * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
-		 * Disable all Pcie Bridges to work around It.
-		 */
-		sr56x0_rd890_disable_pcie_bridge();
-		post_code(0x39);
-		nb_Poweron_Init();
-		post_code(0x3A);
-		sb_Poweron_Init();
-	}
-	post_code(0x3B);
-	agesawrapper_amdinitearly();
-
-	post_code(0x3C);
-	nb_Ht_Init();
-
-	post_code(0x3D);
-	/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
-	if (!warm_reset_detect(0)) {
-		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
-		distinguish_cpu_resets(0);
-		soft_reset();
-		die("After soft_reset - shouldn't see this message!!!\n");
-	}
-
-	post_code(0x40);
-	agesawrapper_amdinitpost();
-
-	post_code(0x41);
-	agesawrapper_amdinitenv();
-	post_code(0x42);
-
-	post_code(0x50);
-	printk(BIOS_DEBUG, "Disabling cache as RAM ");
-	disable_cache_as_ram();
-	printk(BIOS_DEBUG, "done\n");
-
-	post_code(0x51);
-	copy_and_run();
-
-	/* We will not return,  Should never see this message and post code. */
-	printk(BIOS_DEBUG, "should not be here -\n");
-	post_code(0x54);
-}
diff --git a/src/mainboard/supermicro/h8scm/sb700_cfg.c b/src/mainboard/supermicro/h8scm/sb700_cfg.c
deleted file mode 100644
index 2d8437c5ef..0000000000
--- a/src/mainboard/supermicro/h8scm/sb700_cfg.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#include <string.h>
-#include <console/console.h>    /* printk */
-#include "Platform.h"
-#include "sb700_cfg.h"
-
-
-/**
- * @brief South Bridge CIMx configuration
- *
- * should be called before exeucte CIMx function.
- * this function will be called in romstage and ramstage.
- */
-void sb700_cimx_config(AMDSBCFG *sb_config)
-{
-	if (!sb_config) {
-		printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - No sb_config.\n");
-		return;
-	}
-	printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - Start.\n");
-	memset(sb_config, 0, sizeof(AMDSBCFG));
-
-	/* SB_POWERON_INIT */
-	sb_config->StdHeader.Func = SB_POWERON_INIT;
-
-	/* header */
-	sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS;
-
-	/* static Build Parameters */
-	sb_config->BuildParameters.BiosSize = BIOS_SIZE;
-	sb_config->BuildParameters.LegacyFree = LEGACY_FREE;
-	sb_config->BuildParameters.EcKbd = 0;
-	sb_config->BuildParameters.EcChannel0 = 0;
-	sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS;
-	sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS;
-	sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS;
-	sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS;
-	sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS;
-
-	sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS;
-	sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS;
-	sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS;
-	sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS;
-	sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS;
-	sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT;
-	sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS;
-
-	sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID;
-	sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID;
-	sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID;
-	sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID;
-	sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID;
-	sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID;
-	sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID;
-	sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID;
-	sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID;
-	sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID;
-	sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID;
-	sb_config->BuildParameters.SmbusSsid = SMBUS_SSID;
-	sb_config->BuildParameters.IdeSsid = IDE_SSID;
-	sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID;
-	sb_config->BuildParameters.LpcSsid = LPC_SSID;
-
-	sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS;
-
-	/* General */
-	sb_config->Spi33Mhz = 1;
-	sb_config->SpreadSpectrum = 0;
-	sb_config->PciClk5 = 1;
-	sb_config->PciClks = 0x1F;
-	sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood
-	sb_config->TimerClockSource = 2;  // Auto
-	sb_config->S3Resume = 0;
-	sb_config->RebootRequired = 0;
-
-	/* HPET */
-	sb_config->HpetTimer = HPET_TIMER;
-
-	/* USB */
-	sb_config->UsbIntClock = 0;     // Use external clock
-	sb_config->Usb1Ohci0 = 1; //0:disable  1:enable Bus 0 Dev 18 Func0
-	sb_config->Usb1Ohci1 = 1; //0:disable  1:enable Bus 0 Dev 18 Func1
-	sb_config->Usb1Ehci  = 1; //0:disable  1:enable Bus 0 Dev 18 Func2
-	sb_config->Usb2Ohci0 = 1; //0:disable  1:enable Bus 0 Dev 19 Func0
-	sb_config->Usb2Ohci1 = 1; //0:disable  1:enable Bus 0 Dev 19 Func1
-	sb_config->Usb2Ehci  = 1; //0:disable  1:enable Bus 0 Dev 19 Func2
-	sb_config->Usb3Ohci  = 1; //0:disable  1:enable Bus 0 Dev 20 Func5
-	sb_config->UsbOhciLegacyEmulation = 1; //0:Enable  1:Disable
-
-	sb_config->AcpiS1Supported = 1;
-
-	/* SATA */
-	sb_config->SataController = 1;
-	sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci
-	sb_config->SataSmbus = 0;
-	sb_config->SataAggrLinkPmCap = 1;
-	sb_config->SataPortMultCap = 1;
-	sb_config->SataClkAutoOff = 1;
-	sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
-	//TODO: set to secondary not take effect.
-	sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled
-	sb_config->SataEspPort = 0;
-	sb_config->SataClkAutoOffAhciMode = 1;
-	sb_config->SataHpcpButNonESP = 0;
-	sb_config->SataHideUnusedPort = 0;
-
-	/* Azalia HDA */
-	sb_config->AzaliaController = AZALIA_CONTROLLER;
-	sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG;
-	sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN_0;
-	sb_config->AzaliaSdin1 = AZALIA_SDIN_PIN_1;
-	sb_config->AzaliaSdin2 = AZALIA_SDIN_PIN_2;
-	sb_config->AzaliaSdin3 = AZALIA_SDIN_PIN_3;
-	sb_config->pAzaliaOemCodecTablePtr = NULL;
-
-#ifndef __PRE_RAM__
-	/* ramstage cimx config here */
-	if (!sb_config->StdHeader.pCallBack) {
-		sb_config->StdHeader.pCallBack = sb700_callout_entry;
-	}
-
-	//sb_config->
-#endif //!__PRE_RAM__
-	printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - End.\n");
-}
diff --git a/src/mainboard/supermicro/h8scm/sb700_cfg.h b/src/mainboard/supermicro/h8scm/sb700_cfg.h
deleted file mode 100644
index 62b618f70a..0000000000
--- a/src/mainboard/supermicro/h8scm/sb700_cfg.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#ifndef _SB700_CFG_H_
-#define _SB700_CFG_H_
-
-#include <stdint.h>
-
-
-/**
- * @def BIOS_SIZE_1M
- * @def BIOS_SIZE_2M
- * @def BIOS_SIZE_4M
- * @def BIOS_SIZE_8M
- */
-#define BIOS_SIZE_1M                    0
-#define BIOS_SIZE_2M                    1
-#define BIOS_SIZE_4M                    3
-#define BIOS_SIZE_8M                    7
-
-/* In SB700, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024)
-#define BIOS_SIZE BIOS_SIZE_1M
-#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048)
-#define BIOS_SIZE BIOS_SIZE_2M
-#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096)
-#define BIOS_SIZE BIOS_SIZE_4M
-#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192)
-#define BIOS_SIZE BIOS_SIZE_8M
-#endif
-#endif
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- *  0 - Disable Spread Spectrum function
- *  1 - Enable  Spread Spectrum function
- */
-#define SPREAD_SPECTRUM                 0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- *  0 - Disable hpet
- *  1 - Enable  hpet
- */
-#define HPET_TIMER                      1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- *   0 - Disable
- *   1 - Enable
- *  Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
- *  Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
- *  Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
- *  Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
- *  Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
- *  Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
- *  Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
- */
-#define USB_CINFIG              0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- *   0 - disable
- *   1 - enable
- *  PCI SLOT 0 define at BIT0
- *  PCI SLOT 1 define at BIT1
- *  PCI SLOT 2 define at BIT2
- *  PCI SLOT 3 define at BIT3
- *  PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL                  0x1F
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#ifndef SATA_CONTROLLER
-#define SATA_CONTROLLER               1
-#endif
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#ifndef SATA_MODE
-#define SATA_MODE                     NATIVE_IDE_MODE
-#endif
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE                 0
-#define IDE_NATIVE_MODE                 1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#ifndef SATA_IDE_MODE
-#define SATA_IDE_MODE                 IDE_LEGACY_MODE
-#endif
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- *  PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK          0x00
-#define INTERNAL_CLOCK          0x01
-
-#define SATA_CLOCK_SOURCE       EXTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED     1
-
-
-/**
- * @def   AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def   AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def   AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO                     0
-#define AZALIA_DISABLE                  1
-#define AZALIA_ENABLE                   2
-
-/**
- * @brief INCHIP HDA controller
- */
-#ifndef AZALIA_CONTROLLER
-#define AZALIA_CONTROLLER             AZALIA_AUTO
-#endif
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- *  0 - disable
- *  1 - enable
- */
-#ifndef AZALIA_PIN_CONFIG
-#define AZALIA_PIN_CONFIG             1
-#endif
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- *  SDIN0 is define at BIT0 & BIT1
- *   00 - GPIO PIN
- *   01 - Reserved
- *   10 - As a Azalia SDIN pin
- *  SDIN1 is define at BIT2 & BIT3
- *  SDIN2 is define at BIT4 & BIT5
- *  SDIN3 is define at BIT6 & BIT7
- */
-#ifndef AZALIA_SDIN_PIN
-//#define AZALIA_SDIN_PIN             0xAA
-#define AZALIA_SDIN_PIN
-#define AZALIA_SDIN_PIN_0             0x2
-#define AZALIA_SDIN_PIN_1             0x2
-#define AZALIA_SDIN_PIN_2             0x2
-#define AZALIA_SDIN_PIN_3             0x0
-#endif
-
-/**
- * @def GPP_CONTROLLER
- */
-#ifndef GPP_CONTROLLER
-#define GPP_CONTROLLER                1
-#endif
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- *  GPP_CFGMODE_X4000
- *  GPP_CFGMODE_X2200
- *  GPP_CFGMODE_X2110
- *  GPP_CFGMODE_X1111
- */
-#ifndef GPP_CFGMODE
-#define GPP_CFGMODE                   GPP_CFGMODE_X1111
-#endif
-
-
-/**
- * @brief South Bridge CIMx configuration
- *
- */
-void sb700_cimx_config(AMDSBCFG *sb_cfg);
-
-/**
- * @brief Entry point of Southbridge CIMx callout
- *
- * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
- *
- * @param[in] func    Southbridge CIMx Function ID.
- * @param[in] data    Southbridge Input Data.
- * @param[in] config  Southbridge configuration structure pointer.
- *
- */
-u32 sb700_callout_entry(u32 func, u32 data, void* config);
-
-#endif //_SB700_CFG_H_
diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c
deleted file mode 100644
index ff9ea4575b..0000000000
--- a/src/mainboard/tyan/s8226/BiosCallOuts.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "AGESA.h"
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <arch/io.h>
-#include <stdlib.h>
-
-#ifdef __PRE_RAM__
-/* These defines are used to select the appropriate socket for the SPD read
- * because this is a multi-socket design.
- */
-#define PCI_REG_GPIO_48_47_46_37_CNTRL   (0xA6)
-#define PCI_REG_GPIO_52_to_49_CNTRL      (0x50)
-#define GPIO_OUT_BIT_GPIO48              (BIT3)
-#define GPIO_OUT_BIT_GPIO49              (BIT0)
-#define GPIO_OUT_ENABLE_BIT_GPIO48       (BIT7)
-#define GPIO_OUT_ENABLE_BIT_GPIO49       (BIT4)
-
-static UINT8 select_socket(UINT8 socket_id)
-{
-	pci_devfn_t sm_dev       = PCI_DEV(0, 0x14, 0); //SMBUS
-	UINT8    value        = 0;
-	UINT8    gpio52_to_49 = 0;
-
-	/* Configure GPIO49,48 to select the desired socket
-	 * GPIO49,48 control the IDTQS3253 S1,S0
-	 *  S1 S0 true table
-	 *   0  0   channel 0
-	 *   0  1   channel 1
-	 *   1  0   channel 2   -  Socket 0
-	 *   1  1   channel 3   -  Socket 1
-	 * Note: Above is abstracted from Schematic. But actually it seems to be other way.
-	 *   1  0   channel 2   -  Socket 1
-	 *   1  1   channel 3   -  Socket 0
-	 * Note: The DIMMs need to be plugged in from the farthest slot for each channel.
-	 */
-	gpio52_to_49 = pci_read_config8(sm_dev, PCI_REG_GPIO_52_to_49_CNTRL);
-	value  = gpio52_to_49 | GPIO_OUT_BIT_GPIO49; // Output of GPIO49 is always forced to "1"
-	value &= ~(GPIO_OUT_ENABLE_BIT_GPIO49); // 0=Output Enabled, 1=Tristate
-	pci_write_config8(sm_dev, PCI_REG_GPIO_52_to_49_CNTRL, value);
-
-	value  = pci_read_config8(sm_dev, PCI_REG_GPIO_48_47_46_37_CNTRL);
-	value &= ~(GPIO_OUT_BIT_GPIO48);
-	value |= (~(socket_id & 1)) << 3;  // Output of GPIO48 is inverse of SocketId
-	value &= ~(GPIO_OUT_ENABLE_BIT_GPIO48); // 0=Output Enabled, 1=Tristate
-	pci_write_config8(sm_dev, PCI_REG_GPIO_48_47_46_37_CNTRL, value);
-
-	return gpio52_to_49;
-}
-
-static void restore_socket(UINT8 original_value)
-{
-	pci_devfn_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
-	pci_write_config8(sm_dev, PCI_REG_GPIO_52_to_49_CNTRL, original_value);
-
-	// TODO: Restore previous GPIO48 configurations?
-	//pci_write_config8(sm_dev, PCI_REG_GPIO_48_47_46_37_CNTRL, gpio48_47_46_37_save);
-}
-#endif
-
-static AGESA_STATUS board_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			board_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_GET_IDS_INIT_DATA,		agesa_EmptyIdsInitData },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-static AGESA_STATUS board_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS Status;
-#ifdef __PRE_RAM__
-	UINT8 original_value = 0;
-
-	if (ConfigPtr == NULL)
-		return AGESA_ERROR;
-
-	original_value = select_socket(((AGESA_READ_SPD_PARAMS *)ConfigPtr)->SocketId);
-
-	Status = agesa_ReadSpd (Func, Data, ConfigPtr);
-
-	restore_socket(original_value);
-#else
-	Status = AGESA_UNSUPPORTED;
-#endif
-
-	return Status;
-}
diff --git a/src/mainboard/tyan/s8226/Kconfig b/src/mainboard/tyan/s8226/Kconfig
deleted file mode 100644
index 71ee5b80a0..0000000000
--- a/src/mainboard/tyan/s8226/Kconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-if BOARD_TYAN_S8226
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select AGESA_LEGACY
-	select CPU_AMD_AGESA_FAMILY15
-	select CPU_AMD_SOCKET_C32
-	select NORTHBRIDGE_AMD_AGESA_FAMILY15
-	select NORTHBRIDGE_AMD_CIMX_RD890
-	select SOUTHBRIDGE_AMD_CIMX_SB700
-	select SUPERIO_WINBOND_W83627DHG
-	select SUPERIO_NUVOTON_WPCM450
-	select DRIVERS_I2C_W83795
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_4096
-
-config MAINBOARD_DIR
-	string
-	default tyan/s8226
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "S8226"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 64
-
-config HW_MEM_HOLE_SIZE_AUTO_INC
-	bool
-	default n
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config VGA_BIOS
-	bool
-	default n
-
-config VGA_BIOS_ID
-	string
-	depends on VGA_BIOS
-	default "1a03,2000"
-
-endif # BOARD_TYAN_S8226
diff --git a/src/mainboard/tyan/s8226/Kconfig.name b/src/mainboard/tyan/s8226/Kconfig.name
deleted file mode 100644
index 881e56fafb..0000000000
--- a/src/mainboard/tyan/s8226/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_TYAN_S8226
-	bool "S8226"
diff --git a/src/mainboard/tyan/s8226/Makefile.inc b/src/mainboard/tyan/s8226/Makefile.inc
deleted file mode 100644
index 0868bc22d0..0000000000
--- a/src/mainboard/tyan/s8226/Makefile.inc
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-romstage-y += rd890_cfg.c
-romstage-y += sb700_cfg.c
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += rd890_cfg.c
-ramstage-y += sb700_cfg.c
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
-
-AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa
-CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx
-AGESA_ROOT ?= $(AGESA_PREFIX)/f15
-NB_CIMX_ROOT ?= $(CIMX_PREFIX)/rd890
-SB_CIMX_ROOT ?= $(CIMX_PREFIX)/sb700
diff --git a/src/mainboard/tyan/s8226/OemCustomize.c b/src/mainboard/tyan/s8226/OemCustomize.c
deleted file mode 100644
index f38ff06faf..0000000000
--- a/src/mainboard/tyan/s8226/OemCustomize.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <PlatformMemoryConfiguration.h>
-
-/*----------------------------------------------------------------------------------------
- *                        CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-//reference BKDG Table87: works
-#define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM.
-#define SEED_A 0x54
-#define SEED_B 0x4D
-#define SEED_C 0x45
-#define SEED_D 0x40
-
-#define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM.
-//4B 41 51
-
-/*
- *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *  use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
-
-	WRITE_LEVELING_SEED(
-			ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
-			F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
-			F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
-			F15_WL_SEED),
-
-	HW_RXEN_SEED(
-		ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
-		SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
-		SEED_A),
-	HW_RXEN_SEED(
-		ANY_SOCKET, CHANNEL_B, ALL_DIMMS,
-		SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B,
-		SEED_B),
-	HW_RXEN_SEED(
-		ANY_SOCKET, CHANNEL_C, ALL_DIMMS,
-		SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C,
-		SEED_C),
-	HW_RXEN_SEED(
-		ANY_SOCKET, CHANNEL_D, ALL_DIMMS,
-		SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
-		SEED_D),
-
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 3), //max 3
-	PSO_END
-};
-
-const struct OEM_HOOK OemCustomize = {
-};
diff --git a/src/mainboard/tyan/s8226/OptionsIds.h b/src/mainboard/tyan/s8226/OptionsIds.h
deleted file mode 100644
index 079d6b2b84..0000000000
--- a/src/mainboard/tyan/s8226/OptionsIds.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDS_DEBUG_PORT
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_CONTROL_ENABLED TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-//#define IDSOPT_PERF_ANALYSIS   TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-//#define CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL TRUE
-//#undef IDSOPT_DEBUG_ENABLED
-//#define IDSOPT_DEBUG_ENABLED  FALSE
-//#undef IDSOPT_HOST_SIMNOW
-//#define IDSOPT_HOST_SIMNOW    FALSE
-//#undef IDSOPT_HOST_HDT
-//#define IDSOPT_HOST_HDT       FALSE
-//#define IDS_DEBUG_PORT    0x80
-
-#endif
diff --git a/src/mainboard/tyan/s8226/acpi/routing.asl b/src/mainboard/tyan/s8226/acpi/routing.asl
deleted file mode 100644
index f66b1670fd..0000000000
--- a/src/mainboard/tyan/s8226/acpi/routing.asl
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
-		)
-	{
-		#include "routing.asl"
-	}
-*/
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - SR5650 HT */
-		Package() { 0xFFFF, Zero, INTA, Zero },
-
-		/* Bus 0, Dev 1 - CLKCONFIG */
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
-		Package() {0x0002FFFF, 0, INTE, 0 },
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package() {0x0004FFFF, 0, INTE, 0 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-
-		/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
-
-		/* Bus 0, Dev 9 - PCIe Bridge */
-
-		/* Bus 0, Dev a - PCIe Bridge */
-
-		/* Bus 0, Dev b - PCIe Bridge */
-		Package() {0x000BFFFF, 0, INTG, 0 },
-
-		/* Bus 0, Dev c - PCIe Bridge */
-		Package() {0x000CFFFF, 0, INTG, 0 },
-
-		/* Bus 0, Dev d - PCIe Bridge for Intel 82576 Giga NIC*/
-		Package() {0x000DFFFF, 0, INTG, 0 },
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller */
-		Package() {0x0011FFFF, 0, INTG, 0 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package() {0x0012FFFF, 0, INTA, 0 },
-		Package() {0x0012FFFF, 1, INTB, 0 },
-		Package() {0x0012FFFF, 2, INTC, 0 },
-		Package() {0x0012FFFF, 3, INTD, 0 },
-
-		Package() {0x0013FFFF, 0, INTC, 0 },
-		Package() {0x0013FFFF, 1, INTD, 0 },
-		Package() {0x0013FFFF, 2, INTA, 0 },
-		Package() {0x0013FFFF, 2, INTB, 0 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - SR5650 HT */
-		Package() { 0xFFFF, Zero, Zero, 16 },
-
-		/* Bus 0, Dev 1 - CLKCONFIG */
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot (GFX0) */
-		Package() {0x0002FFFF, 0, 0, 0x34 },
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package() {0x0004FFFF, 0, 0, 0x34 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-
-		/* Bus 0, Dev 7 - PCIe Bridge */
-
-		/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
-
-		/* Bus 0, Dev 9 - PCIe Bridge */
-
-		/* Bus 0, Dev A - PCIe Bridge */
-
-		/* Bus 0, Dev B - PCIe Bridge */
-		Package() {0x000BFFFF, 0, 0, 0x36 },
-
-		/* Bus 0, Dev C - PCIe Bridge */
-		Package() {0x000CFFFF, 0, 0, 0x36 },
-
-		/* Bus 0, Dev D - PCIe Bridge For Intel 82576 Giga NIC*/
-		Package() {0x000DFFFF, 0, 0, 0x36 },
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller */
-		Package() {0x0011FFFF, 0, 0, 0x16 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package( ){0x0012FFFF, 0, 0, 16 },
-		Package() {0x0012FFFF, 1, 0, 17 },
-		Package() {0x0012FFFF, 2, 0, 18 },
-		Package() {0x0012FFFF, 3, 0, 19 },
-
-		Package() {0x0013FFFF, 0, 0, 18 },
-		Package() {0x0013FFFF, 1, 0, 19 },
-		Package() {0x0013FFFF, 2, 0, 16 },
-		Package() {0x0013FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package() {0x0014FFFF, 0, 0, 16 },
-		Package() {0x0014FFFF, 1, 0, 17 },
-		Package() {0x0014FFFF, 2, 0, 18 },
-		Package() {0x0014FFFF, 3, 0, 19 },
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 4 */
-		Package() {0x0000FFFF, 0, INTC, 0 },
-		Package() {0x0000FFFF, 1, INTD, 0 },
-		Package() {0x0000FFFF, 2, INTA, 0 },
-		Package() {0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 0x18 },
-		Package(){0x0000FFFF, 1, 0, 0x19 },
-		Package(){0x0000FFFF, 2, 0, 0x1A },
-		Package(){0x0000FFFF, 3, 0, 0x1B },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 0x2C },
-		Package(){0x0000FFFF, 1, 0, 0x2D },
-		Package(){0x0000FFFF, 2, 0, 0x2E },
-		Package(){0x0000FFFF, 3, 0, 0x2F },
-	})
-
-	Name(PSb, Package(){
-		/* PCIe slot - Hooked to PCIe slot 11 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APSb, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 0x20 },
-		Package(){0x0000FFFF, 1, 0, 0x21 },
-		Package(){0x0000FFFF, 2, 0, 0x22 },
-		Package(){0x0000FFFF, 3, 0, 0x23 },
-	})
-
-	Name(PSc, Package(){
-		/* PCIe slot - Hooked to PCIe slot 12 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APSc, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 0x24 },
-		Package(){0x0000FFFF, 1, 0, 0x25 },
-		Package(){0x0000FFFF, 2, 0, 0x26 },
-		Package(){0x0000FFFF, 3, 0, 0x27 },
-	})
-
-	Name(PSd, Package(){
-		/* PCIe slot - Hooked to PCIe slot 13 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APSd, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 0x28 },
-		Package(){0x0000FFFF, 1, 0, 0x29 },
-		Package(){0x0000FFFF, 2, 0, 0x2A },
-		Package(){0x0000FFFF, 3, 0, 0x2B },
-	})
-}
diff --git a/src/mainboard/tyan/s8226/acpi/sata.asl b/src/mainboard/tyan/s8226/acpi/sata.asl
deleted file mode 100644
index 9e0e535da6..0000000000
--- a/src/mainboard/tyan/s8226/acpi/sata.asl
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (LGreater(P0IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (LGreater(P1IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (LGreater(P2IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (LGreater(P3IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (LGreater(\_SB.P0IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P0PR)
-		}
-
-		if (\_SB.P1PR) {
-			if (LGreater(\_SB.P1IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P1PR)
-		}
-
-		if (\_SB.P2PR) {
-			if (LGreater(\_SB.P2IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P2PR)
-		}
-
-		if (\_SB.P3PR) {
-			if (LGreater(\_SB.P3IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P3PR)
-		}
-	}
-}
diff --git a/src/mainboard/tyan/s8226/acpi/usb.asl b/src/mainboard/tyan/s8226/acpi/usb.asl
deleted file mode 100644
index 0f8ca9c0ab..0000000000
--- a/src/mainboard/tyan/s8226/acpi/usb.asl
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
-		)
-	{
-		#include "usb.asl"
-	}
-*/
-Method(UCOC, 0) {
-	Sleep(20)
-	Store(0x13,CMTI)
-	Store(0,GPSL)
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if(LEqual(GPB0,PLC0)) {
-				Not(PLC0,PLC0)
-				Store(PLC0, \_SB.PT0D)
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (LEqual(GPB1,PLC1)) {
-				Not(PLC1,PLC1)
-				Store(PLC1, \_SB.PT1D)
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (LEqual(GPB2,PLC2)) {
-				Not(PLC2,PLC2)
-				Store(PLC2, \_SB.PT2D)
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (LEqual(GPB3,PLC3)) {
-				Not(PLC3,PLC3)
-				Store(PLC3, \_SB.PT3D)
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (LEqual(GPB4,PLC4)) {
-				Not(PLC4,PLC4)
-				Store(PLC4, \_SB.PT4D)
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (LLessEqual(UOM5,9)) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (LEqual(GPB5,PLC5)) {
-				Not(PLC5,PLC5)
-				Store(PLC5, \_SB.PT5D)
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (LEqual(GPB6,PLC6)) {
-				Not(PLC6,PLC6)
-				Store(PLC6, \_SB.PT6D)
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (LEqual(GPB7,PLC7)) {
-				Not(PLC7,PLC7)
-				Store(PLC7, \_SB.PT7D)
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (LEqual(G8IS,PLC8)) {
-				Not(PLC8,PLC8)
-				Store(PLC8, \_SB.PT8D)
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (LEqual(G9IS,0)) {
-			Store(1,\_SB.PT9D)
-			}
-		}
-	}
-}
diff --git a/src/mainboard/tyan/s8226/acpi_tables.c b/src/mainboard/tyan/s8226/acpi_tables.c
deleted file mode 100644
index 4221992601..0000000000
--- a/src/mainboard/tyan/s8226/acpi_tables.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <arch/ioapic.h>
-#include <arch/io.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	device_t dev;
-	u32 dword;
-	u32 gsi_base = 0;
-	u32 apicid_sp5100;
-	u32 apicid_sr5650;
-
-	/*
-	 * AGESA v5 Apply apic enumeration rules
-	 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
-	 * put the local-APICs at m..z
-	 * For systems with < 16 APICs, put the Local-APICs at 0..n and
-	 * put the IO-APICs at (n + 1)..z
-	 */
-	if (CONFIG_MAX_CPUS >= 16)
-		apicid_sp5100 = 0x0;
-	else
-		apicid_sp5100 = CONFIG_MAX_CPUS + 1;
-	apicid_sr5650 = apicid_sp5100 + 1;
-
-	/* create all subtables for processors */
-	current = acpi_create_madt_lapics(current);
-
-	/* Write sp5100 IOAPIC, only one */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-			apicid_sp5100,
-			IO_APIC_ADDR,
-			0
-			);
-
-	/* IOAPIC on rs5690 */
-	gsi_base += IO_APIC_INTERRUPTS;  /* SP5100 has 24 IOAPIC entries. */
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-	if (dev) {
-		pci_write_config32(dev, 0xF8, 0x1);
-		dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
-		current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				apicid_sr5650,
-				dword,
-				gsi_base
-				);
-	}
-
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current,
-			0, //BUS
-			0, //SOURCE
-			2, //gsirq
-			0  //flags
-			);
-
-	/* 0: mean bus 0--->ISA */
-	/* 0: PIC 0 */
-	/* 2: APIC 2 */
-	/* 5 mean: 0101 --> Edge-triggered, Active high */
-
-	/* create all subtables for processors */
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
-	/* 1: LINT1 connect to NMI */
-
-	return current;
-}
diff --git a/src/mainboard/tyan/s8226/board_info.txt b/src/mainboard/tyan/s8226/board_info.txt
deleted file mode 100644
index f858a4fca3..0000000000
--- a/src/mainboard/tyan/s8226/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: server
-Release year: 2010
diff --git a/src/mainboard/tyan/s8226/buildOpts.c b/src/mainboard/tyan/s8226/buildOpts.c
deleted file mode 100644
index 7a3afa9262..0000000000
--- a/src/mainboard/tyan/s8226/buildOpts.c
+++ /dev/null
@@ -1,426 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdlib.h>
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-
-/* AGESA will check the OEM configuration during preprocessing stage,
- * coreboot enable -Wundef option, so we should make sure we have all contanstand defined
- */
-/* MEMORY_BUS_SPEED */
-#define DDR400_FREQUENCY		200	///< DDR 400
-#define DDR533_FREQUENCY		266	///< DDR 533
-#define DDR667_FREQUENCY		333	///< DDR 667
-#define DDR800_FREQUENCY		400	///< DDR 800
-#define DDR1066_FREQUENCY		533	///< DDR 1066
-#define DDR1333_FREQUENCY		667	///< DDR 1333
-#define DDR1600_FREQUENCY		800	///< DDR 1600
-#define DDR1866_FREQUENCY		933	///< DDR 1866
-#define UNSUPPORTED_DDR_FREQUENCY	934	///< Highest limit of DDR frequency
-
-/* QUANDRANK_TYPE*/
-#define QUADRANK_REGISTERED		0	///< Quadrank registered DIMM
-#define QUADRANK_UNBUFFERED		1	///< Quadrank unbuffered DIMM
-
-/* USER_MEMORY_TIMING_MODE */
-#define TIMING_MODE_AUTO		0	///< Use best rate possible
-#define TIMING_MODE_LIMITED		1	///< Set user top limit
-#define TIMING_MODE_SPECIFIC		2	///< Set user specified speed
-
-/* POWER_DOWN_MODE */
-#define POWER_DOWN_BY_CHANNEL		0	///< Channel power down mode
-#define POWER_DOWN_BY_CHIP_SELECT	1	///< Chip select power down mode
-
-/* User makes option selections here
- * Comment out the items wanted to be included in the build.
- * Uncomment those items you with to REMOVE from the build.
- */
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
-//#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
-//#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
-//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
-#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
-//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT      TRUE
-////#define BLDOPT_REMOVE_ACPI_PSTATES             TRUE
-////#define BLDOPT_REMOVE_SRAT                     TRUE
-////#define BLDOPT_REMOVE_SLIT                     TRUE
-//#define BLDOPT_REMOVE_WHEA                     TRUE
-//#define BLDOPT_REMOVE_DMI                      TRUE
-
-/*f15 Rev A1 ucode patch CpuF15OrMicrocodePatch0600011F */
-#define BLDOPT_REMOVE_EARLY_SAMPLES		FALSE
-
-//#define BLDOPT_REMOVE_HT_ASSIST                TRUE
-//#define BLDOPT_REMOVE_MSG_BASED_C1E            TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
-
-/* Build configuration values here.
- */
-#define BLDCFG_VRM_CURRENT_LIMIT                 120000
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD           0
-#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT          0
-#define BLDCFG_PLAT_NUM_IO_APICS                 3
-#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
-#define BLDCFG_MEM_INIT_PSTATE                   0
-#define BLDCFG_AMD_PSTATE_CAP_VALUE              0
-
-#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_SERVER
-
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1333_FREQUENCY//1600
-#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
-#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
-#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_REGISTERED
-#define BLDCFG_MEMORY_RDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE              FALSE
-#define BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB          TRUE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    FALSE//TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE//TRUE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        FALSE//TRUE
-#define BLDCFG_MEMORY_POWER_DOWN                  FALSE
-#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHANNEL
-#define BLDCFG_ONLINE_SPARE                       FALSE
-#define BLDCFG_BANK_SWIZZLE                       TRUE
-#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1333_FREQUENCY //DDR800_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
-#define BLDCFG_USE_BURST_MODE                     FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
-#define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
-#define BLDCFG_ECC_REDIRECTION                    FALSE
-#define BLDCFG_SCRUB_IC_RATE                      0
-#define BLDCFG_ECC_SYNC_FLOOD                     TRUE
-#define BLDCFG_ECC_SYMBOL_SIZE                    4
-
-#define BLDCFG_PCI_MMIO_BASE                    CONFIG_MMCONF_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_SIZE                    CONFIG_MMCONF_BUS_NUMBER
-
-/**
- * Enable Message Based C1e CPU feature in multi-socket systems.
- * BLDCFG_PLATFORM_C1E_OPDATA element be defined with a valid IO port value,
- * else the feature cannot be enabled.
- */
-#define BLDCFG_PLATFORM_C1E_MODE                  C1eModeMsgBased
-#define BLDCFG_PLATFORM_C1E_OPDATA                0x80//TODO
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1        0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2        0
-
-#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000
-#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    0xD0000000
-#define BLDCFG_1GB_ALIGN                          FALSE
-//#define BLDCFG_PROCESSOR_SCOPE_NAME0              'C'
-//#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
-//
-
-// Select the platform control flow mode for performance tuning.
-#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
-
-/**
- * Enable the probe filtering performance tuning feature.
- * The probe filter provides filtering of broadcast probes to
- * improve link bandwidth and performance for multi- node systems.
- *
- * This feature may interact with other performance features.
- *  TRUE  -Enable the feature (default) if supported by all processors,
- *         based on revision and presence of L3 cache.
- *         The feature is not enabled if there are no coherent HT links.
- *  FALSE -Do not enable the feature regardless of the configuration.
- */
-//TODO enable it,
-//but AGESA set PFMode = 0; //PF Disable, HW never set PFInitDone
-//hang in F10HtAssistInit() do{...} while(PFInitDone != 1)
-#define BLDCFG_USE_HT_ASSIST	FALSE
-
-/**
- * The socket and link match values are platform specific
- */
-CONST MANUAL_BUID_SWAP_LIST ROMDATA s8226_manual_swaplist[2] =
-{
-	{
-		/* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-
-		{ //BUID Swap List
-			{ //BUID Swaps
-				/* Each Non-coherent chain may have a list of device swaps,
-				 * Each item specify a device will be swap from its current id to a new one
-				 */
-				/* FromID 0x00 is the chain with the southbridge */
-				/* 'Move' device zero to device zero, All others are non applicable */
-				{0x00, 0x00}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-				{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
-			},
-
-			{ //The ordered final BUIDs
-				/* Specify the final BUID to be zero, All others are non applicable */
-				0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-				0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-				0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-				0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-			}
-		}
-	},
-
-	/* The 2nd element in the array merely terminates the list */
-	{
-		HT_LIST_TERMINAL,
-	}
-};
-
-#define HYPERTRANSPORT_V31_SUPPORT 1
-
-#if HYPERTRANSPORT_V31_SUPPORT
-/**
- * The socket and link match values are platform specific
- *
- */
-CONST CPU_TO_CPU_PCB_LIMITS ROMDATA s8226_cpu2cpu_limit_list[2] =
-{
-	{
-		/* On the reference platform, these settings apply to all coherent links */
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-
-		/* Set incoming and outgoing links to 16 bit widths, and 3.2GHz frequencies */
-		HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M,
-	},
-
-	/* The 2nd element in the array merely terminates the list */
-	{
-		HT_LIST_TERMINAL,
-	}
-};
-
-CONST IO_PCB_LIMITS ROMDATA s8226_io_limit_list[2] =
-{
-	{
-		/* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-
-		/* Set upstream and downstream links to 16 bit widths, and limit frequencies to 3.2GHz */
-		HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, //Actually IO hub only support 2600M MAX
-	},
-
-	/* The 2nd element in the array merely terminates the list */
-	{
-		HT_LIST_TERMINAL,
-	}
-};
-#else /* HYPERTRANSPORT_V31_SUPPORT == 0 */
-CONST CPU_TO_CPU_PCB_LIMITS ROMDATA s8226_cpu2cpu_limit_list[2] =
-{
-	{
-		/* On the reference platform, these settings apply to all coherent links */
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-
-		/* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
-		HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
-	},
-
-	/* The 2nd element in the array merely terminates the list */
-	{
-		HT_LIST_TERMINAL,
-	}
-};
-
-CONST IO_PCB_LIMITS ROMDATA s8226_io_limit_list[2] =
-{
-	{
-		/* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
-		HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
-
-		/* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
-		HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
-	},
-
-	/* The 2nd element in the array merely terminates the list */
-	{
-		HT_LIST_TERMINAL
-	}
-};
-#endif /* HYPERTRANSPORT_V31_SUPPORT == 0 */
-
-/**
- * HyperTransport links will typically require an equalization at high frequencies.
- * This is called deemphasis.
- *
- * Deemphasis is specified as levels, for example, -3 db.
- * There are two levels for each link, its receiver deemphasis level and its DCV level,
- * which is based on the far side transmitter's deemphasis.
- * For each link, different levels may be required at each link frequency.
- *
- * Coherent connections between processors should have an entry for the port on each processor.
- * There should be one entry for the host root port of each non-coherent chain.
- *
- * AGESA initialization code does not set deemphasis on IO Devices.
- * A default is provided for internal links of MCM processors, and
- * those links will generally not need deemphasis structures.
- */
-CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA s8226_deemphasis_list[] =
-{
-	/* Socket, Link, LowFreq, HighFreq, Receiver Deemphasis, Dcv Deemphasis */
-
-	/* Non-coherent link deemphasis. */
-	{0, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
-	{0, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
-	{0, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
-	{0, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
-	{0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
-	{0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
-
-	{1, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
-	{1, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
-	{1, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
-	{1, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
-	{1, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
-	{1, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
-
-	{2, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
-	{2, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
-	{2, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
-	{2, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
-	{2, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
-	{2, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
-
-	{3, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
-	{3, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
-	{3, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
-	{3, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
-	{3, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
-	{3, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
-
-	/* Coherent link deemphasis. */
-	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
-	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3},
-	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus6},
-	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus6},
-	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus8},
-	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2600M, HT_FREQUENCY_MAX, DeemphasisLevelMinus11pre8, DcvLevelMinus11},
-
-	/* End of the list */
-	{
-		HT_LIST_TERMINAL
-	}
-};
-
-/**
- * For systems using socket infrastructure that permits strapping the SBI
- * address for each socket, this should be used to provide a socket ID value.
- * This is referred to as the hardware method for socket naming, and is the
- * preferred solution.
- */
-/*
- * I do NOT know howto config socket id in simnow,
- * so use this software way to make HT works in simnow,
- * real hardware do not need this Socket Map.
- *
- * A physical socket map for a 4 G34 Sockets MCM processors topology,
- * reference the mainboard schemantic in detail.
- *
- */
-CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA s8226_socket_map[] =
-{
-#define HT_SOCKET0	0
-#define HT_SOCKET1	1
-#define HT_SOCKET2	2
-#define HT_SOCKET3	3
-
-/**
- * 0-3 are sublink 0, 4-7 are sublink 1
- */
-#define HT_LINK0A	0
-#define HT_LINK1A	1
-#define HT_LINK2A	2
-#define HT_LINK3A	3
-#define HT_LINK0B	4
-#define HT_LINK1B	5
-#define HT_LINK2B	6
-#define HT_LINK3B	7
-
-	/* Source Socket, Link, Target Socket */
-/*	{HT_SOCKET0, HT_LINK0A, HT_SOCKET1},
-	{HT_SOCKET0, HT_LINK0B, HT_SOCKET3},
-	{HT_SOCKET0, HT_LINK1A, HT_SOCKET1},
-	{HT_SOCKET0, HT_LINK1B, HT_SOCKET3},
-	{HT_SOCKET0, HT_LINK3A, HT_SOCKET2},
-	{HT_SOCKET0, HT_LINK3B, HT_SOCKET2},
-
-	{HT_SOCKET1, HT_LINK0A, HT_SOCKET2},
-	{HT_SOCKET1, HT_LINK0B, HT_SOCKET3},
-	{HT_SOCKET1, HT_LINK1A, HT_SOCKET0},
-	{HT_SOCKET1, HT_LINK1B, HT_SOCKET2},
-	{HT_SOCKET1, HT_LINK3A, HT_SOCKET0},
-	{HT_SOCKET1, HT_LINK3B, HT_SOCKET3},
-
-	{HT_SOCKET2, HT_LINK0A, HT_SOCKET3},
-	{HT_SOCKET2, HT_LINK0B, HT_SOCKET0},
-	{HT_SOCKET2, HT_LINK1A, HT_SOCKET3},
-	{HT_SOCKET2, HT_LINK1B, HT_SOCKET1},
-	{HT_SOCKET2, HT_LINK3A, HT_SOCKET1},
-	{HT_SOCKET2, HT_LINK3B, HT_SOCKET0},
-
-	{HT_SOCKET3, HT_LINK0A, HT_SOCKET2},
-	{HT_SOCKET3, HT_LINK0B, HT_SOCKET1},
-	{HT_SOCKET3, HT_LINK1A, HT_SOCKET1},
-	{HT_SOCKET3, HT_LINK1B, HT_SOCKET0},
-	{HT_SOCKET3, HT_LINK3A, HT_SOCKET0},
-	{HT_SOCKET3, HT_LINK3B, HT_SOCKET2}, */
-};
-
-CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] =
-{
-	{AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E},
-	{AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E},
-	{AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_C0000,  0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_C8000,  0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_D0000,  0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_D8000,  0x0000000000000000},
-	{AMD_AP_MTRR_FIX4k_E0000,  0x1818181818181818},
-	{AMD_AP_MTRR_FIX4k_E8000,  0x1818181818181818},
-	{AMD_AP_MTRR_FIX4k_F0000,  0x1818181818181818},
-	{AMD_AP_MTRR_FIX4k_F8000,  0x1818181818181818},
-	{CPU_LIST_TERMINAL}
-};
-
-#define BLDCFG_BUID_SWAP_LIST			&s8226_manual_swaplist
-#define BLDCFG_HTFABRIC_LIMITS_LIST		&s8226_cpu2cpu_limit_list
-#define BLDCFG_HTCHAIN_LIMITS_LIST		&s8226_io_limit_list
-#define BLDCFG_PLATFORM_DEEMPHASIS_LIST		&s8226_deemphasis_list
-#define BLDCFG_AP_MTRR_SETTINGS_LIST		&s8226_ap_mtrr_list
-//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP	&s8226_socket_map
-
-
-/*  Process the options...
- * This file include MUST occur AFTER the user option selection settings
- */
-
-#include "SanMarinoInstall.h"
diff --git a/src/mainboard/tyan/s8226/cmos.layout b/src/mainboard/tyan/s8226/cmos.layout
deleted file mode 100644
index 956aba3689..0000000000
--- a/src/mainboard/tyan/s8226/cmos.layout
+++ /dev/null
@@ -1,68 +0,0 @@
-#*****************************************************************************
-#
-#  This file is part of the coreboot project.
-#
-#  Copyright (C) 2011 Advanced Micro Devices, Inc.
-#
-#  This program is free software; you can redistribute it and/or modify
-#  it under the terms of the GNU General Public License as published by
-#  the Free Software Foundation; version 2 of the License.
-#
-#  This program is distributed in the hope that it will be useful,
-#  but WITHOUT ANY WARRANTY; without even the implied warranty of
-#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-#  GNU General Public License for more details.
-#*****************************************************************************
-
-entries
-
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#392          3       r       0        unused
-395          1       e       1        hw_scrubber
-396          1       e       1        interleave_chip_selects
-397          2       e       8        max_mem_clock
-399          1       e       2        multi_core
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        iommu
-456          1       e       1        ECC_memory
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
-
-
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-8     0     400Mhz
-8     1     333Mhz
-8     2     266Mhz
-8     3     200Mhz
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/tyan/s8226/devicetree.cb b/src/mainboard/tyan/s8226/devicetree.cb
deleted file mode 100644
index ddcf769ff5..0000000000
--- a/src/mainboard/tyan/s8226/devicetree.cb
+++ /dev/null
@@ -1,217 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-chip northbridge/amd/agesa/family15/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family15
-			device lapic 0x10 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x15d9 0xab11 inherit #Tyan
-		chip northbridge/amd/agesa/family15 # CPU side of HT root complex
-			device pci 18.0 on     # Put IO-HUB at link_num 0, Instead of HT Link topology
-				chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex
-					device pci 0.0 on  end # HT Root Complex 0x9600
-					device pci 0.1 off end # CLKCONFIG
-					device pci 2.0 on  end # GPP1 Port0  x16 SLOT4, 0x5A16
-					device pci 3.0 off end # GPP1 Port1
-					device pci 4.0 on end # GPP3a Port0  x4 SAS
-					device pci 5.0 on end # GPP3a Port1
-					device pci 6.0 on end # GPP3a Port2
-					device pci 7.0 on end # GPP3a Port3
-					device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time
-					device pci 9.0 on end # GPP3a Port4  x1 NC
-					device pci a.0 on end # GPP3a Port5  x1 NC
-					device pci b.0 on end # GPP2 Port0 (Not for sr5650)
-					device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670)
-					device pci d.0 on  end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
-					register "gpp1_configuration" = "0"   # Configuration 16:0 default
-					register "gpp2_configuration" = "0"   # Configuration 8:8
-					register "gpp3a_configuration" = "2"   # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1
-					register "port_enable" = "0x3ef6"
-				end #northbridge/amd/cimx/rd890
-				chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus
-					device pci 11.0 on end # SATA
-					device pci 12.0 on end # USB1
-					device pci 12.1 on end # USB1
-					device pci 12.2 on end # USB1
-					device pci 13.0 on end # USB2
-					device pci 13.1 on end # USB2
-					device pci 13.2 on end # USB2
-					device pci 14.0 on end # SM
-					device pci 14.1 off end # IDE  0x439c
-					device pci 14.2 off end # HDA  0x4383, s8226 not have codec.
-					device pci 14.3 on # LPC  0x439d
-						chip superio/winbond/w83627dhg
-							device pnp 2e.0 off #  Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off #  Parallel Port
-								io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 on  #  Com1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.3 on  #  Com2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							## though UARTs are on the NUVOTON BMC, superio only used to support PS2 KB/MS##
-							device pnp 2e.5 on #  PS/2 keyboard & mouse
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 0x01 #keyboard
-								irq 0x72 = 0x0C #mouse
-							end
-							device pnp 2e.6 off #  SPI
-							end
-							device pnp 2e.307 off #  GPIO6
-							end
-							device pnp 2e.8 off #  WDTO#, PLED
-							end
-							device pnp 2e.009 off #  GPIO2
-							end
-							device pnp 2e.109 off #  GPIO3
-							end
-							device pnp 2e.209 off #  GPIO4
-							end
-							device pnp 2e.309 off #  GPIO5
-							end
-							device pnp 2e.a off #  ACPI
-							end
-							device pnp 2e.b off # HWM
-								io 0x60 = 0x290
-							end
-							device pnp 2e.c off # PECI, SST
-							end
-						end #superio/winbond/w83627dhg
-						chip drivers/i2c/w83795
-							register "fanin_ctl1" = "0xff"			# Enable monitoring of FANIN1 - FANIN8
-							register "fanin_ctl2" = "0x00"			# Connect FANIN11 - FANIN14 to alternate functions
-							register "temp_ctl1" = "0x2a"			# Enable monitoring of DTS, VSEN12, and VSEN13
-							register "temp_ctl2" = "0x01"			# Enable monitoring of TD1/TR1
-							register "temp_dtse" = "0x03"			# Enable DTS1 and DTS2
-							register "volt_ctl1" = "0xff"			# Enable monitoring of VSEN1 - VSEN8
-							register "volt_ctl2" = "0xf7"			# Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT
-							register "temp1_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp1)
-							register "temp2_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp2)
-							register "temp3_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp3)
-							register "temp4_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp4)
-							register "temp5_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp5)
-							register "temp6_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp6)
-							register "temp1_source_select" = "0x00"		# Use TD1/TR1 as data source for Temp1
-							register "temp2_source_select" = "0x00"		# Use TD2/TR2 as data source for Temp2
-							register "temp3_source_select" = "0x00"		# Use TD3/TR3 as data source for Temp3
-							register "temp4_source_select" = "0x00"		# Use TD4/TR4 as data source for Temp4
-							register "temp5_source_select" = "0x00"		# Use TR5 as data source for Temp5
-							register "temp6_source_select" = "0x00"		# Use TR6 as data source for Temp6
-							register "tr1_critical_temperature" = "85"	# Set TD1/TR1 critical temperature to 85°C
-							register "tr1_critical_hysteresis" = "80"	# Set TD1/TR1 critical hysteresis temperature to 80°C
-							register "tr1_warning_temperature" = "70"	# Set TD1/TR1 warning temperature to 70°C
-							register "tr1_warning_hysteresis" = "65"	# Set TD1/TR1 warning hysteresis temperature to 65°C
-							register "dts_critical_temperature" = "85"	# Set DTS (CPU) critical temperature to 85°C
-							register "dts_critical_hysteresis" = "80"	# Set DTS (CPU) critical hysteresis temperature to 80°C
-							register "dts_warning_temperature" = "70"	# Set DTS (CPU) warning temperature to 70°C
-							register "dts_warning_hysteresis" = "65"	# Set DTS (CPU) warning hysteresis temperature to 65°C
-							register "temp1_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
-							register "temp2_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
-							register "temp3_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
-							register "temp4_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
-							register "temp5_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
-							register "temp6_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
-							register "temp1_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
-							register "temp2_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
-							register "temp3_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
-							register "temp4_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
-							register "temp5_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
-							register "temp6_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
-							register "fan1_nonstop" = "7"			# Set Fan 1 minimum speed
-							register "fan2_nonstop" = "7"			# Set Fan 2 minimum speed
-							register "fan3_nonstop" = "7"			# Set Fan 3 minimum speed
-							register "fan4_nonstop" = "7"			# Set Fan 4 minimum speed
-							register "fan5_nonstop" = "7"			# Set Fan 5 minimum speed
-							register "fan6_nonstop" = "7"			# Set Fan 6 minimum speed
-							register "fan7_nonstop" = "7"			# Set Fan 7 minimum speed
-							register "fan8_nonstop" = "7"			# Set Fan 8 minimum speed
-							register "default_speed" = "100"		# All fans to full speed on power up
-							register "fan1_duty" = "100"			# Fan 1 to full speed
-							register "fan2_duty" = "100"			# Fan 2 to full speed
-							register "fan3_duty" = "100"			# Fan 3 to full speed
-							register "fan4_duty" = "100"			# Fan 4 to full speed
-							register "fan5_duty" = "100"			# Fan 5 to full speed
-							register "fan6_duty" = "100"			# Fan 6 to full speed
-							register "fan7_duty" = "100"			# Fan 7 to full speed
-							register "fan8_duty" = "100"			# Fan 8 to full speed
-							register "vcore1_high_limit_mv" = "1500"	# VCORE1 (Node 0) high limit to 1.5V
-							register "vcore1_low_limit_mv" = "900"		# VCORE1 (Node 0) low limit to 0.9V
-							register "vcore2_high_limit_mv" = "1500"	# VCORE2 (Node 1) high limit to 1.5V
-							register "vcore2_low_limit_mv" = "900"		# VCORE2 (Node 1) low limit to 0.9V
-							register "vsen3_high_limit_mv" = "1600"		# VSEN1 (Node 0 RAM voltage) high limit to 1.6V
-							register "vsen3_low_limit_mv" = "1100"		# VSEN1 (Node 0 RAM voltage) low limit to 1.1V
-							register "vsen4_high_limit_mv" = "1600"		# VSEN2 (Node 1 RAM voltage) high limit to 1.6V
-							register "vsen4_low_limit_mv" = "1100"		# VSEN2 (Node 1 RAM voltage) low limit to 1.1V
-							register "vsen5_high_limit_mv" = "1250"		# VSEN5 (Node 0 HT link voltage) high limit to 1.25V
-							register "vsen5_low_limit_mv" = "1150"		# VSEN5 (Node 0 HT link voltage) low limit to 1.15V
-							register "vsen6_high_limit_mv" = "1250"		# VSEN6 (Node 1 HT link voltage) high limit to 1.25V
-							register "vsen6_low_limit_mv" = "1150"		# VSEN6 (Node 1 HT link voltage) low limit to 1.15V
-							register "vsen7_high_limit_mv" = "1150"		# VSEN7 (Northbridge core voltage) high limit to 1.15V
-							register "vsen7_low_limit_mv" = "1050"		# VSEN7 (Northbridge core voltage) low limit to 1.05V
-							register "vsen8_high_limit_mv" = "1900"		# VSEN8 (+1.8V) high limit to 1.9V
-							register "vsen8_low_limit_mv" = "1700"		# VSEN8 (+1.8V) low limit to 1.7V
-							register "vsen9_high_limit_mv" = "1250"		# VSEN9 (+1.2V) high limit to 1.25V
-							register "vsen9_low_limit_mv" = "1150"		# VSEN9 (+1.2V) low limit to 1.15V
-							register "vsen10_high_limit_mv" = "1150"	# VSEN10 (+1.1V) high limit to 1.15V
-							register "vsen10_low_limit_mv" = "1050"		# VSEN10 (+1.1V) low limit to 1.05V
-							register "vsen11_high_limit_mv" = "1625"	# VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V
-							register "vsen11_low_limit_mv" = "1500"		# VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V
-							register "vsen12_high_limit_mv" = "1083"	# VSEN12 (+12V, scaling factor ~12) high limit to 13V
-							register "vsen12_low_limit_mv" = "917"		# VSEN12 (+12V, scaling factor ~12) low limit to 11V
-							register "vsen13_high_limit_mv" = "1625"	# VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V
-							register "vsen13_low_limit_mv" = "1500"		# VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V
-							register "vdd_high_limit_mv" = "3500"		# 3VDD high limit to 3.5V
-							register "vdd_low_limit_mv" = "3100"		# 3VDD low limit to 3.1V
-							register "vsb_high_limit_mv" = "3500"		# 3VSB high limit to 3.5V
-							register "vsb_low_limit_mv" = "3100"		# 3VSB low limit to 3.1V
-							register "vbat_high_limit_mv" = "3500"		# VBAT (+3V) high limit to 3.5V
-							register "vbat_low_limit_mv" = "2500"		# VBAT (+3V) low limit to 2.5V
-							register "smbus_aux" = "0"			# Device located on primary SMBUS
-							device pnp 5e on #hwm
-							end
-						end #drivers/i2c/w83795
-					end # LPC
-					device pci 14.4 on end # PCI 0x4384
-					device pci 14.5 on end # USB 3
-					register "boot_switch_sata_ide" = "0"   # 0: boot from SATA. 1: IDE
-				end # southbridge/amd/cimx/sb700
-			end # device pci 18.0
-
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end #f15
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 0
-				{ {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 1
-			}"
-		end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
-	end #domain
-end #northbridge/amd/agesa/family15/root_complex
diff --git a/src/mainboard/tyan/s8226/dsdt.asl b/src/mainboard/tyan/s8226/dsdt.asl
deleted file mode 100644
index 9e34a5a8c5..0000000000
--- a/src/mainboard/tyan/s8226/dsdt.asl
+++ /dev/null
@@ -1,1671 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* DefinitionBlock Statement */
-DefinitionBlock (
-	"DSDT.AML",	/* Output filename */
-	"DSDT",		/* Signature */
-	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
-	"AMD   ",	/* OEMID */
-	"COREBOOT",	/* TABLE ID */
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	/* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
-
-	/* Data to be patched by the BIOS during POST */
-	/* FIXME the patching is not done yet! */
-	/* Memory related values */
-	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
-	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
-	Name(PBLN, 0x0)	/* Length of BIOS area */
-
-	Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
-	Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
-
-	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
-	/* USB overcurrent mapping pins.   */
-	Name(UOM0, 0)
-	Name(UOM1, 2)
-	Name(UOM2, 0)
-	Name(UOM3, 7)
-	Name(UOM4, 2)
-	Name(UOM5, 2)
-	Name(UOM6, 6)
-	Name(UOM7, 2)
-	Name(UOM8, 6)
-	Name(UOM9, 6)
-
-	/* Some global data */
-	Name(OSVR, 3)		/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
-	Name(OSV, Ones)	/* Assume nothing */
-	Name(PMOD, One)	/* Assume APIC */
-
-	/*
-	 * Processor Object
-	 *
-	 */
-	Scope (\_PR) {		/* define processor scope */
-		Processor(
-			C000,		/* name space name */
-			0x00,		/* Unique number for this processor */
-			0x810,		/* PBLK system I/O address !hardcoded! */
-			0x06		/* PBLKLEN for boot processor */
-			) {
-			//#include "acpi/cpstate.asl"
-		}
-		Processor(C001, 0x01, 0x00000000, 0x00) {}
-		Processor(C002, 0x02, 0x00000000, 0x00) {}
-		Processor(C003, 0x03, 0x00000000, 0x00) {}
-		Processor(C004, 0x04, 0x00000000, 0x00) {}
-		Processor(C005, 0x05, 0x00000000, 0x00) {}
-		Processor(C006, 0x06, 0x00000000, 0x00) {}
-		Processor(C007, 0x07, 0x00000000, 0x00) {}
-		Processor(C008, 0x08, 0x00000000, 0x00) {}
-		Processor(C009, 0x09, 0x00000000, 0x00) {}
-		Processor(C00A, 0x0A, 0x00000000, 0x00) {}
-		Processor(C00B, 0x0B, 0x00000000, 0x00) {}
-		Processor(C00C, 0x0C, 0x00000000, 0x00) {}
-		Processor(C00D, 0x0D, 0x00000000, 0x00) {}
-		Processor(C00E, 0x0E, 0x00000000, 0x00) {}
-		Processor(C00F, 0x0F, 0x00000000, 0x00) {}
-		Processor(C010, 0x10, 0x00000000, 0x00) {}
-		Processor(C011, 0x11, 0x00000000, 0x00) {}
-		Processor(C012, 0x12, 0x00000000, 0x00) {}
-		Processor(C013, 0x13, 0x00000000, 0x00) {}
-		Processor(C014, 0x14, 0x00000000, 0x00) {}
-		Processor(C015, 0x15, 0x00000000, 0x00) {}
-		Processor(C016, 0x16, 0x00000000, 0x00) {}
-		Processor(C017, 0x17, 0x00000000, 0x00) {}
-		Processor(C018, 0x18, 0x00000000, 0x00) {}
-		Processor(C019, 0x19, 0x00000000, 0x00) {}
-		Processor(C01A, 0x1A, 0x00000000, 0x00) {}
-		Processor(C01B, 0x1B, 0x00000000, 0x00) {}
-		Processor(C01C, 0x1C, 0x00000000, 0x00) {}
-		Processor(C01D, 0x1D, 0x00000000, 0x00) {}
-		Processor(C01E, 0x1E, 0x00000000, 0x00) {}
-		Processor(C01F, 0x1F, 0x00000000, 0x00) {}
-		Processor(C020, 0x20, 0x00000000, 0x00) {}
-		Processor(C021, 0x21, 0x00000000, 0x00) {}
-		Processor(C022, 0x22, 0x00000000, 0x00) {}
-		Processor(C023, 0x23, 0x00000000, 0x00) {}
-		Processor(C024, 0x24, 0x00000000, 0x00) {}
-		Processor(C025, 0x25, 0x00000000, 0x00) {}
-		Processor(C026, 0x26, 0x00000000, 0x00) {}
-		Processor(C027, 0x27, 0x00000000, 0x00) {}
-		Processor(C028, 0x28, 0x00000000, 0x00) {}
-		Processor(C029, 0x29, 0x00000000, 0x00) {}
-		Processor(C02A, 0x2A, 0x00000000, 0x00) {}
-		Processor(C02B, 0x2B, 0x00000000, 0x00) {}
-		Processor(C02C, 0x2C, 0x00000000, 0x00) {}
-		Processor(C02D, 0x2D, 0x00000000, 0x00) {}
-		Processor(C02E, 0x2E, 0x00000000, 0x00) {}
-		Processor(C02F, 0x2F, 0x00000000, 0x00) {}
-		Alias (C000, CPU0)
-		Alias (C001, CPU1)
-		Alias (C002, CPU2)
-		Alias (C003, CPU3)
-		Alias (C004, CPU4)
-		Alias (C005, CPU5)
-		Alias (C006, CPU6)
-		Alias (C007, CPU7)
-		Alias (C008, CPU8)
-	} /* End _PR scope */
-
-	/* PIC IRQ mapping registers, C00h-C01h */
-	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
-		Field(PRQM, ByteAcc, NoLock, Preserve) {
-		PRQI, 0x00000008,
-		PRQD, 0x00000008,  /* Offset: 1h */
-	}
-	IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
-		PINA, 0x00000008,	/* Index 0 */
-		PINB, 0x00000008,	/* Index 1 */
-		PINC, 0x00000008,	/* Index 2 */
-		PIND, 0x00000008,	/* Index 3 */
-		AINT, 0x00000008,	/* Index 4 */
-		SINT, 0x00000008,	/* Index 5 */
-		    , 0x00000008,	/* Index 6 */
-		AAUD, 0x00000008,	/* Index 7 */
-		AMOD, 0x00000008,	/* Index 8 */
-		PINE, 0x00000008,	/* Index 9 */
-		PINF, 0x00000008,	/* Index A */
-		PING, 0x00000008,	/* Index B */
-		PINH, 0x00000008,	/* Index C */
-	}
-
-	/* PCI Error control register */
-	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
-		Field(PERC, ByteAcc, NoLock, Preserve) {
-		SENS, 0x00000001,
-		PENS, 0x00000001,
-		SENE, 0x00000001,
-		PENE, 0x00000001,
-	}
-
-	/* Client Management index/data registers */
-	OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
-		Field(CMT, ByteAcc, NoLock, Preserve) {
-		CMTI, 8,
-		/* Client Management Data register */
-		G64E, 1,
-		G64O, 1,
-		G32O, 2,
-		    , 2,
-		GPSL, 2,
-	}
-
-	/* GPM Port register */
-	OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
-		Field(GPT, ByteAcc, NoLock, Preserve) {
-		GPB0,1,
-		GPB1,1,
-		GPB2,1,
-		GPB3,1,
-		GPB4,1,
-		GPB5,1,
-		GPB6,1,
-		GPB7,1,
-	}
-
-	/* Flash ROM program enable register */
-	OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
-		Field(FRE, ByteAcc, NoLock, Preserve) {
-		    , 0x00000006,
-		FLRE, 0x00000001,
-	}
-
-	/* PM2 index/data registers */
-	OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
-		Field(PM2R, ByteAcc, NoLock, Preserve) {
-		PM2I, 0x00000008,
-		PM2D, 0x00000008,
-	}
-
-	/* Power Management I/O registers */
-	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
-		Field(PIOR, ByteAcc, NoLock, Preserve) {
-		PIOI, 0x00000008,
-		PIOD, 0x00000008,
-	}
-	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
-		Offset(0x00),	/* MiscControl */
-		, 1,
-		T1EE, 1,
-		T2EE, 1,
-		Offset(0x01),	/* MiscStatus */
-		, 1,
-		T1E, 1,
-		T2E, 1,
-		Offset(0x04),	/* SmiWakeUpEventEnable3 */
-		, 7,
-		SSEN, 1,
-		Offset(0x07),	/* SmiWakeUpEventStatus3 */
-		, 7,
-		CSSM, 1,
-		Offset(0x10),	/* AcpiEnable */
-		, 6,
-		PWDE, 1,
-		Offset(0x1C),	/* ProgramIoEnable */
-		, 3,
-		MKME, 1,
-		IO3E, 1,
-		IO2E, 1,
-		IO1E, 1,
-		IO0E, 1,
-		Offset(0x1D),	/* IOMonitorStatus */
-		, 3,
-		MKMS, 1,
-		IO3S, 1,
-		IO2S, 1,
-		IO1S, 1,
-		IO0S,1,
-		Offset(0x20),	/* AcpiPmEvtBlk */
-		APEB, 16,
-		Offset(0x36),	/* GEvtLevelConfig */
-		, 6,
-		ELC6, 1,
-		ELC7, 1,
-		Offset(0x37),	/* GPMLevelConfig0 */
-		, 3,
-		PLC0, 1,
-		PLC1, 1,
-		PLC2, 1,
-		PLC3, 1,
-		PLC8, 1,
-		Offset(0x38),	/* GPMLevelConfig1 */
-		, 1,
-		 PLC4, 1,
-		 PLC5, 1,
-		, 1,
-		 PLC6, 1,
-		 PLC7, 1,
-		Offset(0x3B),	/* PMEStatus1 */
-		GP0S, 1,
-		GM4S, 1,
-		GM5S, 1,
-		APS, 1,
-		GM6S, 1,
-		GM7S, 1,
-		GP2S, 1,
-		STSS, 1,
-		Offset(0x55),	/* SoftPciRst */
-		SPRE, 1,
-		, 1,
-		, 1,
-		PNAT, 1,
-		PWMK, 1,
-		PWNS, 1,
-
-		/* 	Offset(0x61), */	/*  Options_1 */
-		/* 		,7,  */
-		/* 		R617,1, */
-
-		Offset(0x65),	/* UsbPMControl */
-		, 4,
-		URRE, 1,
-		Offset(0x68),	/* MiscEnable68 */
-		, 3,
-		TMTE, 1,
-		, 1,
-		Offset(0x92),	/* GEVENTIN */
-		, 7,
-		E7IS, 1,
-		Offset(0x96),	/* GPM98IN */
-		G8IS, 1,
-		G9IS, 1,
-		Offset(0x9A),	/* EnhanceControl */
-		,7,
-		HPDE, 1,
-		Offset(0xA8),	/* PIO7654Enable */
-		IO4E, 1,
-		IO5E, 1,
-		IO6E, 1,
-		IO7E, 1,
-		Offset(0xA9),	/* PIO7654Status */
-		IO4S, 1,
-		IO5S, 1,
-		IO6S, 1,
-		IO7S, 1,
-	}
-
-	/* PM1 Event Block
-	* First word is PM1_Status, Second word is PM1_Enable
-	*/
-	OperationRegion(P1EB, SystemIO, APEB, 0x04)
-		Field(P1EB, ByteAcc, NoLock, Preserve) {
-		TMST, 1,
-		,    3,
-		BMST,    1,
-		GBST,   1,
-		Offset(0x01),
-		PBST, 1,
-		, 1,
-		RTST, 1,
-		, 3,
-		PWST, 1,
-		SPWS, 1,
-		Offset(0x02),
-		TMEN, 1,
-		, 4,
-		GBEN, 1,
-		Offset(0x03),
-		PBEN, 1,
-		, 1,
-		RTEN, 1,
-		, 3,
-		PWDA, 1,
-	}
-
-	OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
-		Field (GRAM, ByteAcc, Lock, Preserve)
-		{
-			Offset (0x10),
-			FLG0,   8
-		}
-
-	Scope(\_SB) {
-		/* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
-		OperationRegion(PCFG, SystemMemory, PCBA, PCLN)
-			Field(PCFG, ByteAcc, NoLock, Preserve) {
-			/* Byte offsets are computed using the following technique:
-			 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
-			 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
-			*/
-			Offset(0x00088024),	/* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
-			STB5, 32,
-			Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
-			PT0D, 1,
-			PT1D, 1,
-			PT2D, 1,
-			PT3D, 1,
-			PT4D, 1,
-			PT5D, 1,
-			PT6D, 1,
-			PT7D, 1,
-			PT8D, 1,
-			PT9D, 1,
-			Offset(0x000A0004),	/* Byte offset to SMBUS	register 4h - Bus 0, Device 20, Function 0 */
-			SBIE, 1,
-			SBME, 1,
-			Offset(0x000A0008),	/* Byte offset to SMBUS	register 8h - Bus 0, Device 20, Function 0 */
-			SBRI, 8,
-			Offset(0x000A0014),	/* Byte offset to SMBUS	register 14h - Bus 0, Device 20, Function 0 */
-			SBB1, 32,
-			Offset(0x000A0078),	/* Byte offset to SMBUS	register 78h - Bus 0, Device 20, Function 0 */
-			,14,
-			P92E, 1,		/* Port92 decode enable */
-		}
-
-		OperationRegion(SB5, SystemMemory, STB5, 0x1000)
-			Field(SB5, AnyAcc, NoLock, Preserve){
-			/* Port 0 */
-			Offset(0x120),		/* Port 0 Task file status */
-			P0ER, 1,
-			, 2,
-			P0DQ, 1,
-			, 3,
-			P0BY, 1,
-			Offset(0x128),		/* Port 0 Serial ATA status */
-			P0DD, 4,
-			, 4,
-			P0IS, 4,
-			Offset(0x12C),		/* Port 0 Serial ATA control */
-			P0DI, 4,
-			Offset(0x130),		/* Port 0 Serial ATA error */
-			, 16,
-			P0PR, 1,
-
-			/* Port 1 */
-			offset(0x1A0),		/* Port 1 Task file status */
-			P1ER, 1,
-			, 2,
-			P1DQ, 1,
-			, 3,
-			P1BY, 1,
-			Offset(0x1A8),		/* Port 1 Serial ATA status */
-			P1DD, 4,
-			, 4,
-			P1IS, 4,
-			Offset(0x1AC),		/* Port 1 Serial ATA control */
-			P1DI, 4,
-			Offset(0x1B0),		/* Port 1 Serial ATA error */
-			, 16,
-			P1PR, 1,
-
-			/* Port 2 */
-			Offset(0x220),		/* Port 2 Task file status */
-			P2ER, 1,
-			, 2,
-			P2DQ, 1,
-			, 3,
-			P2BY, 1,
-			Offset(0x228),		/* Port 2 Serial ATA status */
-			P2DD, 4,
-			, 4,
-			P2IS, 4,
-			Offset(0x22C),		/* Port 2 Serial ATA control */
-			P2DI, 4,
-			Offset(0x230),		/* Port 2 Serial ATA error */
-			, 16,
-			P2PR, 1,
-
-			/* Port 3 */
-			Offset(0x2A0),		/* Port 3 Task file status */
-			P3ER, 1,
-			, 2,
-			P3DQ, 1,
-			, 3,
-			P3BY, 1,
-			Offset(0x2A8),		/* Port 3 Serial ATA status */
-			P3DD, 4,
-			, 4,
-			P3IS, 4,
-			Offset(0x2AC),		/* Port 3 Serial ATA control */
-			P3DI, 4,
-			Offset(0x2B0),		/* Port 3 Serial ATA error */
-			, 16,
-			P3PR, 1,
-		}
-	}
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-		Method(OSFL, 0){
-			if(LNotEqual(OSVR, Ones)) {Return(OSVR)}	/* OS version was already detected */
-			if(CondRefOf(\_OSI))
-			{
-				Store(1, OSVR)			/* Assume some form of XP */
-				if (\_OSI("Windows 2006"))      /* Vista */
-				{
-					Store(2, OSVR)
-				}
-			} else {
-				If(WCMP(\_OS,"Linux")) {
-					Store(3, OSVR)		/* Linux */
-				} Else {
-					Store(4, OSVR)		/* Gotta be WinCE */
-				}
-			}
-			Return(OSVR)
-		}
-
-		Method(_PIC, 0x01, NotSerialized)
-		{
-			If (Arg0)
-			{
-				\_SB.CIRQ()
-			}
-			Store(Arg0, PMOD)
-		}
-		Method(CIRQ, 0x00, NotSerialized){
-			Store(0, PINA)
-			Store(0, PINB)
-			Store(0, PINC)
-			Store(0, PIND)
-			Store(0, PINE)
-			Store(0, PINF)
-			Store(0, PING)
-			Store(0, PINH)
-		}
-
-		Name(IRQB, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Shared){15}
-		})
-
-		Name(IRQP, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
-		})
-
-		Name(PITF, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Exclusive){9}
-		})
-
-		Device(INTA) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 1)
-
-			Method(_STA, 0) {
-				if (PINA) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTA._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_DIS\n") */
-				Store(0, PINA)
-			} /* End Method(_SB.INTA._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTA._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINA, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTA._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINA)
-			} /* End Method(_SB.INTA._SRS) */
-		} /* End Device(INTA) */
-
-		Device(INTB) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 2)
-
-			Method(_STA, 0) {
-				if (PINB) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTB._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_DIS\n") */
-				Store(0, PINB)
-			} /* End Method(_SB.INTB._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTB._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINB, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTB._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINB)
-			} /* End Method(_SB.INTB._SRS) */
-		} /* End Device(INTB)  */
-
-		Device(INTC) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 3)
-
-			Method(_STA, 0) {
-				if (PINC) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTC._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_DIS\n") */
-				Store(0, PINC)
-			} /* End Method(_SB.INTC._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTC._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINC, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTC._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINC)
-			} /* End Method(_SB.INTC._SRS) */
-		} /* End Device(INTC)  */
-
-		Device(INTD) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 4)
-
-			Method(_STA, 0) {
-				if (PIND) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTD._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_DIS\n") */
-				Store(0, PIND)
-			} /* End Method(_SB.INTD._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTD._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PIND, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTD._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PIND)
-			} /* End Method(_SB.INTD._SRS) */
-		} /* End Device(INTD)  */
-
-		Device(INTE) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 5)
-
-			Method(_STA, 0) {
-				if (PINE) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTE._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_DIS\n") */
-				Store(0, PINE)
-			} /* End Method(_SB.INTE._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTE._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINE, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTE._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINE)
-			} /* End Method(_SB.INTE._SRS) */
-		} /* End Device(INTE)  */
-
-		Device(INTF) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 6)
-
-			Method(_STA, 0) {
-				if (PINF) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTF._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_DIS\n") */
-				Store(0, PINF)
-			} /* End Method(_SB.INTF._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_PRS\n") */
-				Return(PITF)
-			} /* Method(_SB.INTF._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINF, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTF._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINF)
-			} /*  End Method(_SB.INTF._SRS) */
-		} /* End Device(INTF)  */
-
-		Device(INTG) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 7)
-
-			Method(_STA, 0) {
-				if (PING) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTG._STA)  */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_DIS\n") */
-				Store(0, PING)
-			} /* End Method(_SB.INTG._DIS)  */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTG._CRS)  */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PING, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTG._CRS)  */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PING)
-			} /* End Method(_SB.INTG._SRS)  */
-		} /* End Device(INTG)  */
-
-		Device(INTH) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 8)
-
-			Method(_STA, 0) {
-				if (PINH) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTH._STA)  */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_DIS\n") */
-				Store(0, PINH)
-			} /* End Method(_SB.INTH._DIS)  */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTH._CRS)  */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINH, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTH._CRS)  */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINH)
-			} /* End Method(_SB.INTH._SRS)  */
-		} /* End Device(INTH)   */
-
-	}   /* End Scope(_SB)  */
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Wake status package */
-	Name(WKST,Package(){Zero, Zero})
-
-	/*
-	* \_PTS - Prepare to Sleep method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-	*
-	* Exit:
-	*		-none-
-	*
-	* The _PTS control method is executed at the beginning of the sleep process
-	* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-	* control method may be executed a relatively long time before entering the
-	* sleep state and the OS may abort the operation without notification to
-	* the ACPI driver.  This method cannot modify the configuration or power
-	* state of any device in the system.
-	*/
-	Method(\_PTS, 1) {
-		/* DBGO("\\_PTS\n") */
-		/* DBGO("From S0 to S") */
-		/* DBGO(Arg0) */
-		/* DBGO("\n") */
-
-		/* Don't allow PCIRST# to reset USB */
-		if (LEqual(Arg0,3)){
-			Store(0,URRE)
-		}
-
-		/* Clear sleep SMI status flag and enable sleep SMI trap. */
-		/*Store(One, CSSM)
-		Store(One, SSEN)*/
-
-		/* On older chips, clear PciExpWakeDisEn */
-		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
-		*    	Store(0,\_SB.PWDE)
-		*}
-		*/
-
-		/* Clear wake status structure. */
-		Store(0, Index(WKST,0))
-		Store(0, Index(WKST,1))
-		\_SB.PCI0.SIOS (Arg0)
-	} /* End Method(\_PTS) */
-
-	/*
-	*  The following method results in a "not a valid reserved NameSeg"
-	*  warning so I have commented it out for the duration.  It isn't
-	*  used, so it could be removed.
-	*
-	*
-	*  	\_GTS OEM Going To Sleep method
-	*
-	*  	Entry:
-	*  		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*  	Exit:
-	*  		-none-
-	*
-	*  Method(\_GTS, 1) {
-	*  DBGO("\\_GTS\n")
-	*  DBGO("From S0 to S")
-	*  DBGO(Arg0)
-	*  DBGO("\n")
-	*  }
-	*/
-
-	/*
-	*	\_BFS OEM Back From Sleep method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*	Exit:
-	*		-none-
-	*/
-	Method(\_BFS, 1) {
-		/* DBGO("\\_BFS\n") */
-		/* DBGO("From S") */
-		/* DBGO(Arg0) */
-		/* DBGO(" to S0\n") */
-	}
-
-	/*
-	*  \_WAK System Wake method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*	Exit:
-	*		Return package of 2 DWords
-	*		Dword 1 - Status
-	*			0x00000000	wake succeeded
-	*			0x00000001	Wake was signaled but failed due to lack of power
-	*			0x00000002	Wake was signaled but failed due to thermal condition
-	*		Dword 2 - Power Supply state
-	*			if non-zero the effective S-state the power supply entered
-	*/
-	Method(\_WAK, 1) {
-		/* DBGO("\\_WAK\n") */
-		/* DBGO("From S") */
-		/* DBGO(Arg0) */
-		/* DBGO(" to S0\n") */
-
-		/* Re-enable HPET */
-		Store(1,HPDE)
-
-		/* Restore PCIRST# so it resets USB */
-		if (LEqual(Arg0,3)){
-			Store(1,URRE)
-		}
-
-		/* Arbitrarily clear PciExpWakeStatus */
-		Store(PWST, Local1)
-		Store(Local1, PWST)
-
-		/* if(DeRefOf(Index(WKST,0))) {
-		*	Store(0, Index(WKST,1))
-		* } else {
-		*	Store(Arg0, Index(WKST,1))
-		* }
-		*/
-		\_SB.PCI0.SIOW (Arg0)
-		Return(WKST)
-	} /* End Method(\_WAK) */
-
-	Scope(\_GPE) {	/* Start Scope GPE */
-		/*  General event 0  */
-		Method(_L00) {
-		      //DBGO("\\_GPE\\_L00\n")
-		}
-
-		/*  General event 1  */
-		Method(_L01) {
-		      //DBGO("\\_GPE\\_L01\n")
-		}
-
-		/*  General event 2  */
-		Method(_L02) {
-		      //DBGO("\\_GPE\\_L02\n")
-		}
-
-		/*  General event 3  */
-		Method(_L03) {
-			//DBGO("\\_GPE\\_L00\n")
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  General event 4  */
-		Method(_L04) {
-		      //DBGO("\\_GPE\\_L04\n")
-		}
-
-		/*  General event 5  */
-		Method(_L05) {
-		      //DBGO("\\_GPE\\_L05\n")
-		}
-
-		/* _L06 General event 6 - Used for GPM6, moved to USB.asl */
-		/* _L07 General event 7 - Used for GPM7, moved to USB.asl */
-
-		/*  Legacy PM event  */
-		Method(_L08) {
-			//DBGO("\\_GPE\\_L08\n")
-		}
-
-		/*  Temp warning (TWarn) event  */
-		Method(_L09) {
-			//DBGO("\\_GPE\\_L09\n")
-			Notify (\_TZ.TZ00, 0x80)
-		}
-
-		/*  Reserved  */
-		Method(_L0A) {
-		      //DBGO("\\_GPE\\_L0A\n")
-		}
-
-		/*  USB controller PME#  */
-		Method(_L0B) {
-			//DBGO("\\_GPE\\_L0B\n")
-			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  AC97 controller PME#  */
-		Method(_L0C) {
-		      //DBGO("\\_GPE\\_L0C\n")
-		}
-
-		/*  OtherTherm PME#  */
-		Method(_L0D) {
-		      //DBGO("\\_GPE\\_L0D\n")
-		}
-
-		/* _L0E GPM9 SCI event - Moved to USB.asl */
-
-		/*  PCIe HotPlug event  */
-		Method(_L0F) {
-			//DBGO("\\_GPE\\_L0F\n")
-		}
-
-		/*  ExtEvent0 SCI event  */
-		Method(_L10) {
-			//DBGO("\\_GPE\\_L10\n")
-		}
-
-
-		/*  ExtEvent1 SCI event  */
-		Method(_L11) {
-			//DBGO("\\_GPE\\_L11\n")
-		}
-
-		/*  PCIe PME# event  */
-		Method(_L12) {
-		      //DBGO("\\_GPE\\_L12\n")
-		}
-
-		/* _L13 GPM0 SCI event - Moved to USB.asl */
-		/* _L14 GPM1 SCI event - Moved to USB.asl */
-		/* _L15 GPM2 SCI event - Moved to USB.asl */
-		/* _L16 GPM3 SCI event - Moved to USB.asl */
-		/* _L17 GPM8 SCI event - Moved to USB.asl */
-
-		/*  GPIO0 or GEvent8 event  */
-		Method(_L18) {
-			//DBGO("\\_GPE\\_L18\n")
-			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBRb, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBRc, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBRd, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/* _L19 GPM4 SCI event - Moved to USB.asl */
-		/* _L1A GPM5 SCI event - Moved to USB.asl */
-
-		/*  Azalia SCI event  */
-		Method(_L1B) {
-			//DBGO("\\_GPE\\_L1B\n")
-			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  GPM6 SCI event - Reassigned to _L06 */
-		Method(_L1C) {
-		      //DBGO("\\_GPE\\_L1C\n")
-		}
-
-		/*  GPM7 SCI event - Reassigned to _L07 */
-		Method(_L1D) {
-		      //DBGO("\\_GPE\\_L1D\n")
-		}
-
-		/*  GPIO2 or GPIO66 SCI event  */
-		Method(_L1E) {
-			//DBGO("\\_GPE\\_L1E\n")
-		}
-
-		/* _L1F SATA SCI event - Moved to sata.asl */
-
-	} 	/* End Scope GPE */
-
-	#include "acpi/usb.asl"
-
-	/* System Bus */
-	Scope(\_SB) { /* Start \_SB scope */
-		#include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
-
-		/*  _SB.PCI0 */
-		/* Note: Only need HID on Primary Bus */
-		Device(PCI0) {
-			External (TOM1) //assigned when update_ssdt()
-			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
-
-			Name(_HID, EISAID("PNP0A03"))
-			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
-			Method(_BBN, 0) { /* Bus number = 0 */
-				Return(0)
-			}
-			Method(_STA, 0) {
-				/* DBGO("\\_SB\\PCI0\\_STA\n") */
-				Return(0x0B)     /* Status is visible */
-			}
-
-			Method(_PRT,0) {
-				If(PMOD){ Return(APR0) }	/* APIC mode */
-				Return (PR0)			/* PIC Mode */
-			} /* end _PRT */
-
-			/* Describe the Northbridge devices */
-			Device(AMRT) {
-				Name(_ADR, 0x00000000)
-			} /* end AMRT */
-
-			/* The external GFX bridge */
-			Device(PBR2) {
-				Name(_ADR, 0x00020000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APS2) }	/* APIC mode */
-					Return (PS2)			/* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR2 */
-
-			/* Dev3 is also an external GFX bridge */
-
-			Device(PBR4) {
-				Name(_ADR, 0x00040000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APS4) }	/* APIC mode */
-					Return (PS4)			/* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR4 */
-
-			Device(PBRb) {
-				Name(_ADR, 0x000b0000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APSb) }	/* APIC mode */
-					Return (PSb)			/* PIC Mode */
-				} /* end _PRT */
-			} /* end PBRb */
-
-			Device(PBRc) {
-				Name(_ADR, 0x000c0000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APSc) }	/* APIC mode */
-					Return (PSc)			/* PIC Mode */
-				} /* end _PRT */
-			} /* end PBRc */
-
-			Device(PBRd) {
-				Name(_ADR, 0x000d0000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APSd) }	/* APIC mode */
-					Return (PSd)			/*  PIC Mode */
-				} /* end _PRT */
-			} /* end PBRd */
-
-			/* Describe the Southbridge devices */
-			Device(STCR) {
-				Name(_ADR, 0x00110000)
-				#include "acpi/sata.asl"
-			} /* end STCR */
-
-			Device(UOH1) {
-				Name(_ADR, 0x00130000)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH1 */
-
-			Device(UOH2) {
-				Name(_ADR, 0x00130001)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH2 */
-
-			Device(UOH3) {
-				Name(_ADR, 0x00130002)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH3 */
-
-			Device(UOH4) {
-				Name(_ADR, 0x00130003)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH4 */
-
-			Device(UOH5) {
-				Name(_ADR, 0x00130004)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH5 */
-
-			Device(UEH1) {
-				Name(_ADR, 0x00130005)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UEH1 */
-
-			Device(SBUS) {
-				Name(_ADR, 0x00140000)
-			} /* end SBUS */
-
-			Device(AZHD) {
-				Name(_ADR, 0x00140002)
-				OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
-					Field(AZPD, AnyAcc, NoLock, Preserve) {
-					offset (0x42),
-					NSDI, 1,
-					NSDO, 1,
-					NSEN, 1,
-					offset (0x44),
-					IPCR, 4,
-					offset (0x54),
-					PWST, 2,
-					, 6,
-					PMEB, 1,
-					, 6,
-					PMST, 1,
-					offset (0x62),
-					MMCR, 1,
-					offset (0x64),
-					MMLA, 32,
-					offset (0x68),
-					MMHA, 32,
-					offset (0x6C),
-					MMDT, 16,
-				}
-
-				Method(_INI) {
-					If(LEqual(OSVR,3)){   /* If we are running Linux */
-						Store(zero, NSEN)
-						Store(one, NSDO)
-						Store(one, NSDI)
-					}
-				}
-			} /* end AZHD */
-
-			Device(LIBR) {
-				Name(_ADR, 0x00140003)
-				/* Method(_INI) {
-				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
-				} */ /* End Method(_SB.SBRDG._INI) */
-
-				/* Real Time Clock Device */
-				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
-					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){8}
-						IO(Decode16,0x0070, 0x0070, 0, 2)
-						/* IO(Decode16,0x0070, 0x0070, 0, 4) */
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
-				Device(TMR) {	/* Timer */
-					Name(_HID,EISAID("PNP0100"))	/* System Timer */
-					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){0}
-						IO(Decode16, 0x0040, 0x0040, 0, 4)
-						/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
-				Device(SPKR) {	/* Speaker */
-					Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
-					Name(_CRS, ResourceTemplate() {
-						IO(Decode16, 0x0061, 0x0061, 0, 1)
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
-				Device(PIC) {
-					Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
-					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){2}
-						IO(Decode16,0x0020, 0x0020, 0, 2)
-						IO(Decode16,0x00A0, 0x00A0, 0, 2)
-						/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
-						/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
-				Device(MAD) { /* 8257 DMA */
-					Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
-					Name(_CRS, ResourceTemplate() {
-						DMA(Compatibility,BusMaster,Transfer8){4}
-						IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
-						IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
-						IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
-						IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
-						IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
-						IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
-					}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
-				} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
-				Device(COPR) {
-					Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
-					Name(_CRS, ResourceTemplate() {
-						IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
-						IRQNoFlags(){13}
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
-				Device (PS2M) {
-					Name (_HID, EisaId ("PNP0F13"))
-					Name (_CRS, ResourceTemplate () {
-						IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
-						IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
-						IRQNoFlags () {12}
-					})
-					Method (_STA, 0, NotSerialized) {
-						And (FLG0, 0x04, Local0)
-						If (LEqual (Local0, 0x04)) {
-							Return (0x0F)
-						} Else {
-							Return (0x00)
-						}
-					}
-				}
-
-				Device (PS2K) {
-					Name (_HID, EisaId ("PNP0303"))
-					Method (_STA, 0, NotSerialized) {
-						And (FLG0, 0x04, Local0)
-						If (LEqual (Local0, 0x04)) {
-							Return (0x0F)
-						} Else {
-							Return (0x00)
-						}
-					}
-					Name (_CRS, ResourceTemplate () {
-						IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
-						IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
-						IRQNoFlags () {1}
-					})
-				}
-
-#if 0 //acpi_create_hpet
-				Device(HPET) {
-					Name(_HID,EISAID("PNP0103"))
-					Name(CRS, ResourceTemplate() {
-		    				IRQNoFlags () {0}
-		    				IRQNoFlags () {2}
-		   			 	IRQNoFlags () {8}
-						Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, MNT)	/* 1kb reserved space */
-					})
-					Method(_STA, 0, NotSerialized) {
-						Return(0x0F) /* sata is visible */
-					}
-					Method(_CRS, 0, NotSerialized) {
-						CreateDwordField(CRS, ^MNT._BAS, HPT)
-						Store(HPBA, HPT)
-						Return(CRS)
-					}
-				} /* End Device(_SB.PCI0.LIBR.HPET) */
-#endif
-			} /* end LIBR */
-
-			Device(HPBR) {
-				Name(_ADR, 0x00140004)
-			} /* end HostPciBr */
-
-			Device(ACAD) {
-				Name(_ADR, 0x00140005)
-			} /* end Ac97audio */
-
-			Device(ACMD) {
-				Name(_ADR, 0x00140006)
-			} /* end Ac97modem */
-
-			/* ITE8718 Support */
-			OperationRegion (IOID, SystemIO, 0x2E, 0x02)	/* sometimes it is 0x4E */
-				Field (IOID, ByteAcc, NoLock, Preserve)
-				{
-					SIOI,   8,    SIOD,   8		/* 0x2E and 0x2F */
-				}
-
-			IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
-			{
-					Offset (0x07),
-				LDN,	8,	/* Logical Device Number */
-					Offset (0x20),
-				CID1,	8,	/* Chip ID Byte 1, 0x87 */
-				CID2,	8,	/* Chip ID Byte 2, 0x12 */
-					Offset (0x30),
-				ACTR,	8,	/* Function activate */
-					Offset (0xF0),
-				APC0,	8,	/* APC/PME Event Enable Register */
-				APC1,	8,	/* APC/PME Status Register */
-				APC2,	8,	/* APC/PME Control Register 1 */
-				APC3,	8,	/* Environment Controller Special Configuration Register */
-				APC4,	8	/* APC/PME Control Register 2 */
-			}
-
-			/* Enter the 8718 MB PnP Mode */
-			Method (EPNP)
-			{
-				Store(0x87, SIOI)
-				Store(0x01, SIOI)
-				Store(0x55, SIOI)
-				Store(0x55, SIOI) /* 8718 magic number */
-			}
-			/* Exit the 8718 MB PnP Mode */
-			Method (XPNP)
-			{
-				Store (0x02, SIOI)
-				Store (0x02, SIOD)
-			}
-			/*
-			 * Keyboard PME is routed to SB700 Gevent3. We can wake
-			 * up the system by pressing the key.
-			 */
-			Method (SIOS, 1)
-			{
-				/* We only enable KBD PME for S5. */
-				If (LLess (Arg0, 0x05))
-				{
-					EPNP()
-					/* DBGO("8718F\n") */
-
-					Store (0x4, LDN)
-					Store (One, ACTR)  /* Enable EC */
-					/*
-					Store (0x4, LDN)
-					Store (0x04, APC4)
-					*/  /* falling edge. which mode? Not sure. */
-
-					Store (0x4, LDN)
-					Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
-					Store (0x4, LDN)
-					Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
-
-					XPNP()
-				}
-			}
-			Method (SIOW, 1)
-			{
-				EPNP()
-				Store (0x4, LDN)
-				Store (Zero, APC0) /* disable keyboard PME */
-				Store (0x4, LDN)
-				Store (0xFF, APC1) /* clear keyboard PME status */
-				XPNP()
-			}
-
-			Name (CRS, ResourceTemplate ()
-			{
-				WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
-					0x0000,             // Granularity
-					0x0000,             // Range Minimum
-					0x00FF,             // Range Maximum
-					0x0000,             // Translation Offset
-					0x0100,             // Length
-					,,)
-				IO (Decode16,
-					0x0CF8,             // Range Minimum
-					0x0CF8,             // Range Maximum
-					0x01,               // Alignment
-					0x08,               // Length
-					)
-
-				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,             // Granularity
-					0x0000,             // Range Minimum
-					0x03AF,             // Range Maximum
-					0x0000,             // Translation Offset
-					0x03B0,             // Length
-					,, , TypeStatic)
-				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,             // Granularity
-					0x03E0,             // Range Minimum
-					0x0CF7,             // Range Maximum
-					0x0000,             // Translation Offset
-					0x0918,             // Length
-					,, , TypeStatic)
-
-				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,             // Granularity
-					0x03B0,             // Range Minimum
-					0x03BB,             // Range Maximum
-					0x0000,             // Translation Offset
-					0x000C,             // Length
-					,, , TypeStatic)
-				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,             // Granularity
-					0x03C0,             // Range Minimum
-					0x03DF,             // Range Maximum
-					0x0000,             // Translation Offset
-					0x0020,             // Length
-					,, , TypeStatic)
-				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,             // Granularity
-					0x0D00,             // Range Minimum
-					0xFFFF,             // Range Maximum
-					0x0000,             // Translation Offset
-					0xF300,             // Length
-					,, , TypeStatic)
-				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	// VGA memory space
-
-				Memory32Fixed (ReadOnly,
-						0xE0000000,         // Address Base
-						0x10000000,         // Address Length, (1MB each Bus, 256 Buses by default)
-						MMIO)
-			})
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1)
-				CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1)
-
-				/*
-				 * Declare memory between TOM1 and 4GB as available
-				 * for PCI MMIO.
-				 * Use ShiftLeft to avoid 64bit constant (for XP).
-				 * This will work even if the OS does 32bit arithmetic, as
-				 * 32bit (0x00000000 - TOM1) will wrap and give the same
-				 * result as 64bit (0x100000000 - TOM1).
-				 */
-				Store(TOM1, BAS1)
-				ShiftLeft(0x10000000, 4, Local0)
-				Subtract(Local0, TOM1, Local0)
-				Store(Local0, LEN1)
-				//DBGO(TOM1)
-
-				Return (CRS)
-			}
-
-			/*
-			 *
-			 *               FIRST METHOD CALLED UPON BOOT
-			 *
-			 *  1. If debugging, print current OS and ACPI interpreter.
-			 *  2. Get PCI Interrupt routing from ACPI VSM, this
-			 *     value is based on user choice in BIOS setup.
-			 */
-			Method(_INI, 0) {
-				/* DBGO("\\_SB\\_INI\n") */
-				/* DBGO("   DSDT.ASL code from ") */
-				/* DBGO(__DATE__) */
-				/* DBGO(" ") */
-				/* DBGO(__TIME__) */
-				/* DBGO("\n   Sleep states supported: ") */
-				/* DBGO("\n") */
-				/* DBGO("   \\_OS=") */
-				/* DBGO(\_OS) */
-				/* DBGO("\n   \\_REV=") */
-				/* DBGO(\_REV) */
-				/* DBGO("\n") */
-
-				/* Determine the OS we're running on */
-				OSFL()
-				/* On older chips, clear PciExpWakeDisEn */
-				/*if (LLessEqual(\SBRI, 0x13)) {
-				 *    	Store(0,\PWDE)
-				 *}
-				 */
-			} /* End Method(_SB._INI) */
-		} /* End Device(PCI0)  */
-
-		Device(PWRB) {	/* Start Power button device */
-			Name(_HID, EISAID("PNP0C0C"))
-			Name(_UID, 0xAA)
-			Name(_PRW, Package () {3, 0x04})	/* wake from S1-S4 */
-			Name(_STA, 0x0B) /* sata is invisible */
-		}
-	} /* End \_SB scope */
-
-	Scope(\_SI) {
-		Method(_SST, 1) {
-			/* DBGO("\\_SI\\_SST\n") */
-			/* DBGO("   New Indicator state: ") */
-			/* DBGO(Arg0) */
-			/* DBGO("\n") */
-		}
-	} /* End Scope SI */
-
-	#include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
-
-	/* THERMAL */
-	Scope(\_TZ) {
-		Name (KELV, 2732)
-		Name (THOT, 800)
-		Name (TCRT, 850)
-
-		ThermalZone(TZ00) {
-			Method(_AC0,0) {	/* Active Cooling 0 (0=highest fan speed) */
-				/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
-				Return(Add(0, 2730))
-			}
-			Method(_AL0,0) {	/* Returns package of cooling device to turn on */
-				/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
-				Return(Package() {\_TZ.TZ00.FAN0})
-			}
-			Device (FAN0) {
-				Name(_HID, EISAID("PNP0C0B"))
-				Name(_PR0, Package() {PFN0})
-			}
-
-			PowerResource(PFN0,0,0) {
-				Method(_STA) {
-					Store(0xF,Local0)
-					Return(Local0)
-				}
-				Method(_ON) {
-					/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
-				}
-				Method(_OFF) {
-					/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
-				}
-			}
-
-			Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
-				/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
-				Return (Add (THOT, KELV))
-			}
-			Method(_CRT,0) {	/* return critical temp in tenths degree Kelvin */
-				/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
-				Return (Add (TCRT, KELV))
-			}
-			Method(_TMP,0) {	/* return current temp of this zone */
-				Store (SMBR (0x07, 0x4C,, 0x00), Local0)
-				If (LGreater (Local0, 0x10)) {
-					Store (Local0, Local1)
-				}
-				Else {
-					Add (Local0, THOT, Local0)
-					Return (Add (400, KELV))
-				}
-
-				Store (SMBR (0x07, 0x4C, 0x01), Local0)
-				/* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
-				/* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
-				If (LGreater (Local0, 0x10)) {
-					If (LGreater (Local0, Local1)) {
-						Store (Local0, Local1)
-					}
-
-					Multiply (Local1, 10, Local1)
-					Return (Add (Local1, KELV))
-				}
-				Else {
-					Add (Local0, THOT, Local0)
-					Return (Add (400 , KELV))
-				}
-			} /* end of _TMP */
-		} /* end of TZ00 */
-	}
-}
-/* End of ASL file */
diff --git a/src/mainboard/tyan/s8226/fadt.c b/src/mainboard/tyan/s8226/fadt.c
deleted file mode 100644
index fda488f7fe..0000000000
--- a/src/mainboard/tyan/s8226/fadt.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- */
-
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include "Platform.h" /*sb700 platform header*/
-
-#ifndef ACPI_BLK_BASE
-  #define ACPI_BLK_BASE	PM1_EVT_BLK_ADDRESS
-#endif
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
-	acpi_header_t *header = &(fadt->header);
-
-	printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
-	/* Prepare the header */
-	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
-	memcpy(header->signature, "FACP", 4);
-	header->length = 244;
-	header->revision = 3;
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, "AMD     ", 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-	header->asl_compiler_revision = 0;
-
-	if ((uintptr_t)facs > 0xffffffff)
-		printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n");
-	else
-		fadt->firmware_ctrl = (uintptr_t)facs;
-
-	if ((uintptr_t)dsdt > 0xffffffff)
-		printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n");
-	else
-		fadt->dsdt = (uintptr_t)dsdt;
-
-	/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
-	fadt->preferred_pm_profile = 0x03;
-	fadt->sci_int = 9;
-	/* disable system management mode by setting to 0: */
-	fadt->smi_cmd = 0;
-	fadt->acpi_enable = 0xf0;
-	fadt->acpi_disable = 0xf1;
-	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = 0xe2;
-
-	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
-	outl(0x1, PM1_CNT_BLK_ADDRESS);           /* set SCI_EN */
-	fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
-	fadt->pm1b_evt_blk = 0x0000;
-	fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
-	fadt->pm1b_cnt_blk = 0x0000;
-	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
-	fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
-	fadt->gpe0_blk = GPE0_BLK_ADDRESS;
-	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
-
-	fadt->pm1_evt_len = 4;
-	fadt->pm1_cnt_len = 2;
-	fadt->pm2_cnt_len = 1;
-	fadt->pm_tmr_len = 4;
-	fadt->gpe0_blk_len = 8;
-	fadt->gpe1_blk_len = 0;
-	fadt->gpe1_base = 0;
-
-	fadt->cst_cnt = 0xe3;
-	fadt->p_lvl2_lat = 101;
-	fadt->p_lvl3_lat = 1001;
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
-	fadt->duty_offset = 1;
-	fadt->duty_width = 3;
-	fadt->day_alrm = 0;	/* 0x7d these have to be */
-	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
-	fadt->century = 0;	/* 0x7f to make rtc alrm work */
-	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
-	fadt->flags = 0x0001c1a5;/* 0x25; */
-
-	fadt->res2 = 0;
-
-	fadt->reset_reg.space_id = 1;
-	fadt->reset_reg.bit_width = 8;
-	fadt->reset_reg.bit_offset = 0;
-	fadt->reset_reg.resv = 0;
-	fadt->reset_reg.addrl = 0xcf9;
-	fadt->reset_reg.addrh = 0x0;
-
-	fadt->reset_value = 6;
-	fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff;
-	fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32;
-	fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff;
-	fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32;
-
-	fadt->x_pm1a_evt_blk.space_id = 1;
-	fadt->x_pm1a_evt_blk.bit_width = 32;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.resv = 0;
-	fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
-	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_evt_blk.space_id = 1;
-	fadt->x_pm1b_evt_blk.bit_width = 4;
-	fadt->x_pm1b_evt_blk.bit_offset = 0;
-	fadt->x_pm1b_evt_blk.resv = 0;
-	fadt->x_pm1b_evt_blk.addrl = 0x0;
-	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-
-	fadt->x_pm1a_cnt_blk.space_id = 1;
-	fadt->x_pm1a_cnt_blk.bit_width = 16;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.resv = 0;
-	fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
-	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_cnt_blk.space_id = 1;
-	fadt->x_pm1b_cnt_blk.bit_width = 2;
-	fadt->x_pm1b_cnt_blk.bit_offset = 0;
-	fadt->x_pm1b_cnt_blk.resv = 0;
-	fadt->x_pm1b_cnt_blk.addrl = 0x0;
-	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-
-	fadt->x_pm2_cnt_blk.space_id = 1;
-	fadt->x_pm2_cnt_blk.bit_width = 0;
-	fadt->x_pm2_cnt_blk.bit_offset = 0;
-	fadt->x_pm2_cnt_blk.resv = 0;
-	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
-	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-
-	fadt->x_pm_tmr_blk.space_id = 1;
-	fadt->x_pm_tmr_blk.bit_width = 32;
-	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.resv = 0;
-	fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
-	fadt->x_pm_tmr_blk.addrh = 0x0;
-
-
-	fadt->x_gpe0_blk.space_id = 1;
-	fadt->x_gpe0_blk.bit_width = 32;
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.resv = 0;
-	fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
-	fadt->x_gpe0_blk.addrh = 0x0;
-
-
-	fadt->x_gpe1_blk.space_id = 1;
-	fadt->x_gpe1_blk.bit_width = 0;
-	fadt->x_gpe1_blk.bit_offset = 0;
-	fadt->x_gpe1_blk.resv = 0;
-	fadt->x_gpe1_blk.addrl = 0;
-	fadt->x_gpe1_blk.addrh = 0x0;
-
-	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-}
diff --git a/src/mainboard/tyan/s8226/irq_tables.c b/src/mainboard/tyan/s8226/irq_tables.c
deleted file mode 100644
index 52a99e77dd..0000000000
--- a/src/mainboard/tyan/s8226/irq_tables.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr += 15;
-	addr &= ~15;
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
-	return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/tyan/s8226/mainboard.c b/src/mainboard/tyan/s8226/mainboard.c
deleted file mode 100644
index caa43f3470..0000000000
--- a/src/mainboard/tyan/s8226/mainboard.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <device/pci_def.h>
-#include <NbPlatform.h>
-#include "chip.h"
-
-void set_pcie_dereset(void *nbconfig);
-void set_pcie_reset(void *nbconfig);
-
-/**
- *
- */
-void set_pcie_reset(void *nbconfig)
-{
-}
-
-/**
- * Mainboard specific RD890 CIMx callback
- * Release Resets to PCIe Links
- * For Both SR56X0 chips, PCIE_RESET_GPIO1 to reset pcie
- */
-void set_pcie_dereset(void *nbconfig)
-{
-	//u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
-	u32 i;
-	u32 val;
-	u32 nb_addr;
-
-	val = 0x00000007UL;
-	AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig;
-	for (i = 0; i < MAX_NB_COUNT; i ++) {
-		nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX;
-		LibNbPciIndexRMW(nb_addr,
-				NB_HTIU_REGA8,
-				AccessS3SaveWidth32,
-				~val,
-				val,
-				 &(pConfig->Northbridges[i]));
-	}
-}
-
-
-/*************************************************
- * enable the dedicated function in s8226 board.
- *************************************************/
-static void mainboard_enable(device_t dev)
-{
-	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-}
-
-struct chip_operations mainboard_ops = {
-		.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c
deleted file mode 100644
index 31379a6f56..0000000000
--- a/src/mainboard/tyan/s8226/mptable.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-	u32 apicid_sp5100;
-	u32 apicid_sr5650;
-	device_t dev;
-	u32 *dword;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/*
-	 * AGESA v5 Apply apic enumeration rules
-	 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
-	 * put the local-APICs at m..z
-	 * For systems with < 16 APICs, put the Local-APICs at 0..n and
-	 * put the IO-APICs at (n + 1)..z
-	 */
-	if (CONFIG_MAX_CPUS >= 16)
-		apicid_sp5100 = 0x0;
-	else
-		apicid_sp5100 = CONFIG_MAX_CPUS + 1;
-	apicid_sr5650 = apicid_sp5100 + 1;
-
-	dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	if (dev) {
-		/* Set SP5100 IOAPIC ID */
-		dword = (u32 *)(uintptr_t)(pci_read_config32(dev, 0x74) & 0xfffffff0);
-		smp_write_ioapic(mc, apicid_sp5100, 0x20, dword);
-
-#ifdef UNUSED_CODE
-		u8 byte;
-		/* Initialize interrupt mapping */
-		/* aza */
-		byte = pci_read_config8(dev, 0x63);
-		byte &= 0xf8;
-		byte |= 0; /* 0: INTA, ...., 7: INTH */
-		pci_write_config8(dev, 0x63, byte);
-		/* SATA */
-		dword = pci_read_config32(dev, 0xAC);
-		dword = dword & ~(7 << 26);
-		dword = dword | (6 << 26); /* 0: INTA, ...., 7: INTH */
-		/* dword |= 1 << 22; PIC and APIC co exists */
-		pci_write_config32(dev, 0xAC, dword);
-#endif
-
-		/*
-		 * 00:12.0: PROG SATA : INT F
-		 * 00:13.0: INTA USB_0
-		 * 00:13.1: INTB USB_1
-		 * 00:13.2: INTC USB_2
-		 * 00:13.3: INTD USB_3
-		 * 00:13.4: INTC USB_4
-		 * 00:13.5: INTD USB2
-		 * 00:14.1: INTA IDE
-		 * 00:14.2: Prog HDA : INT E
-		 * 00:14.5: INTB ACI
-		 * 00:14.6: INTB MCI
-		 */
-
-		/* Set RS5650 IOAPIC ID */
-		dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-		if (dev) {
-			pci_write_config32(dev, 0xF8, 0x1);
-			dword = (u32 *)(uintptr_t)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
-			smp_write_ioapic(mc, apicid_sr5650, 0x20, dword);
-		}
-
-	}
-
-	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
-	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0);
-
-	/* PCI interrupts are level triggered, and are
-	 * associated with a specific bus/device/function tuple.
-	 */
-#define PCI_INT(bus, dev, int_sign, pin) \
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sp5100, (pin))
-
-	/* SMBUS */
-	//PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0
-
-	/* HD Audio */
-	PCI_INT(0x0, 0x14, 0x2, 0x10);
-
-	/* USB */
-	/* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */
-	/* EHCI hard-wired to 02h, corresponding to using INTB# */
-	/* USB1 */
-	PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */
-	PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */
-	PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */
-
-	/* USB2 */
-	PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */
-	PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */
-	PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */
-
-	/* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */
-	PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */
-
-	/* SATA */
-	PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
-
-	/* PCI slots */
-	dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-	if (dev && dev->enabled) {
-		u8 bus_pci = dev->link_list->secondary;
-		/* PCI_SLOT 0. */
-		PCI_INT(bus_pci, 0x5, 0x0, 0x14);
-		PCI_INT(bus_pci, 0x5, 0x1, 0x15);
-		PCI_INT(bus_pci, 0x5, 0x2, 0x16);
-		PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
-		/* PCI_SLOT 1. */
-		PCI_INT(bus_pci, 0x6, 0x0, 0x15);
-		PCI_INT(bus_pci, 0x6, 0x1, 0x16);
-		PCI_INT(bus_pci, 0x6, 0x2, 0x17);
-		PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
-		/* PCI_SLOT 2. */
-		PCI_INT(bus_pci, 0x7, 0x0, 0x16);
-		PCI_INT(bus_pci, 0x7, 0x1, 0x17);
-		PCI_INT(bus_pci, 0x7, 0x2, 0x14);
-		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
-	}
-
-	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
-	IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/tyan/s8226/platform_cfg.h b/src/mainboard/tyan/s8226/platform_cfg.h
deleted file mode 100644
index f5a5c73882..0000000000
--- a/src/mainboard/tyan/s8226/platform_cfg.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-
-/* northbridge customize options */
-/**
- * Max number of northbridges in the system
- */
-#define MAX_NB_COUNT		1 //TODO: only 1 NB tested
-
-/**
- *  Enable check for PCIe endpoint to be ready for PCI enumeration.
- *
- */
-//#define EPREADY_WORKAROUND_DISABLED
-
-/**
- *  Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table.
- *
- */
-#define IOMMU_SUPPORT_DISABLE //TODO: enable it
-
-/**
- *  Disable server PCIe hotplug support.
- */
-
-//#define HOTPLUG_SUPPORT_DISABLED
-
-/**
- *  Disable support for device number remapping for PCIe portsserver PCIe hotplug support.
- */
-
-//#define DEVICE_REMAP_DISABLE
-
-#endif //_PLATFORM_CFG_H_
diff --git a/src/mainboard/tyan/s8226/rd890_cfg.c b/src/mainboard/tyan/s8226/rd890_cfg.c
deleted file mode 100644
index 9bbb02a50c..0000000000
--- a/src/mainboard/tyan/s8226/rd890_cfg.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "NbPlatform.h"
-#include "rd890_cfg.h"
-#include "northbridge/amd/cimx/rd890/chip.h"
-#include "nbInitializer.h"
-#include <string.h>
-#include <arch/ioapic.h>
-
-#ifndef __PRE_RAM__
-#include <device/device.h>
-extern void set_pcie_reset(void *config);
-extern void set_pcie_dereset(void *config);
-
-/**
- * Platform dependent configuration at ramstage
- */
-static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr)
-{
-	u16 i;
-	PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig;
-	//AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr);
-	struct northbridge_amd_cimx_rd890_config *rd890_info = NULL;
-	DEFAULT_PLATFORM_CONFIG(platform_config);
-
-	/* update the platform depentent configuration by devicetree */
-	rd890_info  = nb_dev->chip_info;
-	platform_config.PortEnableMap = rd890_info->port_enable;
-	if (rd890_info->gpp1_configuration == 0) {
-		platform_config.Gpp1Config = GFX_CONFIG_AAAA;
-	} else if (rd890_info->gpp1_configuration == 1) {
-		platform_config.Gpp1Config = GFX_CONFIG_AABB;
-	}
-	if (rd890_info->gpp2_configuration == 0) {
-		platform_config.Gpp2Config = GFX_CONFIG_AAAA;
-	} else if (rd890_info->gpp2_configuration == 1) {
-		platform_config.Gpp2Config = GFX_CONFIG_AABB;
-	}
-	platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration;
-
-	if (platform_config.Gpp1Config != 0) {
-		pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config;
-	}
-	if (platform_config.Gpp2Config != 0) {
-		pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config;
-	}
-	if (platform_config.Gpp3aConfig != 0) {
-		pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig;
-	}
-
-	pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20);
-	for (i = 0; i <= MAX_CORE_ID; i++) {
-		NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF;
-		NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF;
-	}
-	for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
-		NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2;
-	}
-
-	for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
-		if ((platform_config.PortEnableMap & (1 << i)) != 0) {
-			pPcieConfig->PortConfiguration[i].PortPresent = ON;
-			if ((platform_config.PortGen1Map & (1 << i)) != 0) {
-				pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1;
-			}
-			if ((platform_config.PortHotplugMap & (1 << i)) != 0) {
-				u16 j;
-				pPcieConfig->PortConfiguration[i].PortHotplug = ON; /* Enable Hotplug */
-				/* Set Hotplug descriptor info */
-				for (j = 0; j < 8; j++) {
-					u32 PortDescriptor;
-					PortDescriptor = platform_config.PortHotplugDescriptors[j];
-					if ((PortDescriptor & 0xF) == j) {
-						pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap  = (PortDescriptor >> 4)  & 3;
-						pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6)  & 1;
-						break;
-					}
-				}
-			}
-		}
-	}
-}
-#endif // __PRE_RAM__
-
-/**
- * @brief Entry point of Northbridge CIMx callout/CallBack
- *
- * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr);
- *
- * @param[in] func     Northbridge CIMx CallBackId
- * @param[in] data     Northbridge Input Data.
- * @param[in] *config  Northbridge configuration structure pointer.
- *
- */
-static u32 rd890_callout_entry(u32 func, uintptr_t data, void *config)
-{
-	u32 ret = 0;
-#ifndef __PRE_RAM__
-	device_t nb_dev = (device_t)data;
-#endif
-	AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config;
-
-	switch (func) {
-		case PHCB_AmdPortTrainingCompleted:
-			break;
-
-		case PHCB_AmdPortResetDeassert:
-#ifndef __PRE_RAM__
-			set_pcie_dereset(config);
-#endif
-			break;
-
-		case PHCB_AmdPortResetAssert:
-#ifndef __PRE_RAM__
-			set_pcie_reset(config);
-#endif
-			break;
-
-		case PHCB_AmdPortResetSupported:
-			break;
-		case PHCB_AmdGeneratePciReset:
-			break;
-		case PHCB_AmdGetExclusionTable:
-			break;
-		case PHCB_AmdAllocateBuffer:
-			break;
-		case PHCB_AmdUpdateApicInterruptMapping:
-			break;
-		case PHCB_AmdFreeBuffer:
-			break;
-		case PHCB_AmdLocateBuffer:
-			break;
-		case PHCB_AmdReportEvent:
-			break;
-		case PHCB_AmdPcieAsmpInfo:
-			break;
-
-		case CB_AmdSetNbPorConfig:
-			break;
-		case CB_AmdSetHtConfig:
-			/*TODO: different HT path and deempasis for each NB */
-			nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES;
-
-			break;
-		case CB_AmdSetPcieEarlyConfig:
-#ifndef __PRE_RAM__
-			nb_platform_config(nb_dev, nbConfigPtr);
-#endif
-			break;
-
-		case CB_AmdSetEarlyPostConfig:
-			break;
-
-		case CB_AmdSetMidPostConfig:
-			nbConfigPtr->pNbConfig->IoApicBaseAddress = IO_APIC_ADDR;
-#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu
-			/* SBIOS must alloc 16K memory for IOMMU MMIO */
-			UINT32  MmcfgBarAddress; //using default IOmmuBaseAddress
-			LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C,
-					AccessWidth32,
-					&MmcfgBarAddress,
-					nbConfigPtr);
-			MmcfgBarAddress &= ~0xf;
-			if (MmcfgBarAddress != 0) {
-				nbConfigPtr->IommuBaseAddress = MmcfgBarAddress;
-			}
-			nbConfigPtr->IommuBaseAddress = 0; //disable iommu
-#endif
-			break;
-
-		case CB_AmdSetLatePostConfig:
-			break;
-
-		case CB_AmdSetRecoveryConfig:
-			break;
-	}
-
-	return ret;
-}
-
-
-/**
- * @brief North Bridge CIMx configuration
- *
- * should be called before exeucte CIMx function.
- * this function will be called in romstage and ramstage.
- */
-void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig)
-{
-	u16 i = 0;
-	PCI_ADDR PciAddress;
-	u32 val, sbNode, sbLink;
-
-	if (!pConfig) {
-		return;
-	}
-
-	memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK));
-	for (i = 0; i < MAX_NB_COUNT; i++) {
-		pConfig->Northbridges[i].pNbConfig	= &nbConfig[i];
-		pConfig->Northbridges[i].pHtConfig	= &htConfig[i];
-		pConfig->Northbridges[i].pPcieConfig	= &pcieConfig[i];
-		pConfig->Northbridges[i].ConfigPtr	= &pConfig;
-	}
-
-	/* Initialize all NB structures */
-	AmdInitializer(pConfig);
-
-	pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
-	pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
-	pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;
-
-	/*
-	 * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform.
-	 * Always 0:0:0 on single NB platform.
-	 */
-	pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
-
-	/* Set HT path to NB by SbNode and SbLink */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
-	LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
-	sbNode = (val >> 8) & 0x07;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
-	LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
-	sbLink = (val >> 8) & 0x07; //assum ganged
-	pConfig->Northbridges[0].NbHtPath.NodeID = sbNode;
-	pConfig->Northbridges[0].NbHtPath.LinkID = sbLink;
-	//TODO: other NBs
-
-#ifndef __PRE_RAM__
-	/* If temporrary MMIO enable set up CPU MMIO */
-	for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) {
-		UINT32  MmioBase;
-		UINT32  LinkId;
-		UINT32  SubLinkId;
-		MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress;
-		if (MmioBase != 0) {
-			LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf;
-			SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0;
-			/* Set Limit */
-			LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84),
-					AccessWidth32,
-					0x0,
-					((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6),
-					&(pConfig->Northbridges[i]));
-			/* Set Base */
-			LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80),
-					AccessWidth32,
-					0x0,
-					(MmioBase << 12) | 0x3,
-					&(pConfig->Northbridges[i]));
-		}
-	}
-#endif
-}
diff --git a/src/mainboard/tyan/s8226/rd890_cfg.h b/src/mainboard/tyan/s8226/rd890_cfg.h
deleted file mode 100644
index 0227c3f54d..0000000000
--- a/src/mainboard/tyan/s8226/rd890_cfg.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef  _RD890_CFG_H_
-#define _RD890_CFG_H_
-
-#include "NbPlatform.h"
-
-/* platform dependent configuration default value */
-
-/**
- * Path from CPU to NB
- * [0..7]   - Node  (0..8)
- * [8..11]  - Link  (0..3)
- * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
- */
-#ifndef DEFAULT_HT_PATH
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
-#define DEFAULT_HT_PATH		{0x0, 0x1}
-#else /* FAMILY10 */
-#define DEFAULT_HT_PATH		{0x0, 0x3}
-#endif
-#endif
-
-/**
- * Bitmap of enabled ports on NB #0/1/2/3
- * Bit[0] - Reserved
- * Bit[1] - Reserved
- * Bit[2] - Enable PCIe port 2
- * Bit[3] - Enable PCIe port 3
- * Bit[4] - Enable PCIe port 4
- * Bit[5] - Enable PCIe port 5
- * Bit[6] - Enable PCIe port 2
- * Bit[7] - Enable PCIe port 7
- * Bit[8] - Reserved
- * Bit[9] - Enable PCIe port 9
- * Bit[10]- Enable PCIe port 10
- * Bit[11]- Enable PCIe port 11
- * Bit[12]- Enable PCIe port 12
- * Bit[13]- Enable PCIe port 13
- * Example:
- *  port_enable = 0x14
- *  Port 2 and 4 enabled for training/initialization
- */
-#ifndef DEFAULT_PORT_ENABLE_MAP
-#define DEFAULT_PORT_ENABLE_MAP		0x0014
-#endif
-
-/**
- * Bitmap of ports that have slot or onboard device connected.
- * Example force PCIe Gen1 supporton port 2 and 4  (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4)
- * define DEFAULT_PORT_FORCE_GEN1        0x604
- */
-#ifndef DEFAULT_PORT_FORCE_GEN1
-#define DEFAULT_PORT_FORCE_GEN1		0x0
-#endif
-
-/**
- * Bitmap of ports that have server hotplug support
- */
-#ifndef DEFAULT_HOTPLUG_SUPPORT
-#define DEFAULT_HOTPLUG_SUPPORT		0x0
-#endif
-
-#ifndef DEFAULT_HOTPLUG_DESCRIPTOR
-#define DEFAULT_HOTPLUG_DESCRIPTOR		{0, 0, 0, 0, 0, 0, 0, 0}
-#endif
-
-#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS
-#define DEFAULT_TEMPMMIO_BASE_ADDRESS		0xD0000000
-#endif
-
-/**
- * Default GPP1 core configuraton on NB #0/1/2/3.
- *  2  x8 slot, GFX_CONFIG_AABB
- *  1 x16 slot, GFX_CONFIG_AAAA
- */
-#ifndef DEFAULT_GPP1_CONFIG
-#define DEFAULT_GPP1_CONFIG		GFX_CONFIG_AABB
-#endif
-
-/**
- * Default GPP2 core configuraton on NB #0/1/2/3.
- *  2  x8 slot, GFX_CONFIG_AABB
- *  1 x16 slot, GFX_CONFIG_AAAA
- */
-#ifndef DEFAULT_GPP2_CONFIG
-#define DEFAULT_GPP2_CONFIG		GFX_CONFIG_AABB
-#endif
-
-/**
- * Default GPP3a core configuraton on NB #0/1/2/3.
- * 4:2:0:0:0:0   - GPP_CONFIG_GPP420000, 0x1
- * 4:1:1:0:0:0   - GPP_CONFIG_GPP411000, 0x2
- * 2:2:2:0:0:0   - GPP_CONFIG_GPP222000, 0x3
- * 2:2:1:1:0:0   - GPP_CONFIG_GPP221100, 0x4
- * 2:1:1:1:1:0   - GPP_CONFIG_GPP211110, 0x5
- * 1:1:1:1:1:1   - GPP_CONFIG_GPP111111, 0x6
- */
-#ifndef DEFAULT_GPP3A_CONFIG
-#define DEFAULT_GPP3A_CONFIG		GPP_CONFIG_GPP111111
-#endif
-
-
-/**
- * Default HT Transmitter de-emphasis setting
- */
-#ifndef DEFAULT_HT_DEEMPASIES
-#define DEFAULT_HT_DEEMPASIES		0x3
-#endif
-
-/**
- * Default APIC nterrupt base for IOAPIC
- */
-#ifndef DEFAULT_APIC_INTERRUPT_BASE
-#define DEFAULT_APIC_INTERRUPT_BASE	24
-#endif
-
-
-#define DEFAULT_PLATFORM_CONFIG(name) \
-	NB_PLATFORM_CONFIG name = { \
-		DEFAULT_PORT_ENABLE_MAP, \
-		DEFAULT_PORT_FORCE_GEN1, \
-		DEFAULT_HOTPLUG_SUPPORT, \
-		DEFAULT_HOTPLUG_DESCRIPTOR, \
-		DEFAULT_TEMPMMIO_BASE_ADDRESS, \
-		DEFAULT_GPP1_CONFIG, \
-		DEFAULT_GPP2_CONFIG, \
-		DEFAULT_GPP3A_CONFIG, \
-		DEFAULT_HT_DEEMPASIES, \
-		/*DEFAULT_HT_PATH,*/ \
-		DEFAULT_APIC_INTERRUPT_BASE, \
-	}
-
-/**
- * Platform configuration
- */
-typedef struct {
-	UINT16  PortEnableMap;            ///< Bitmap of enabled ports
-	UINT16  PortGen1Map;              ///< Bitmap of ports to disable Gen2
-	UINT16  PortHotplugMap;           ///< Bitmap of ports support hotplug
-	UINT8   PortHotplugDescriptors[8];///< Ports Hotplug descriptors
-	UINT32  TemporaryMmio;            ///< Temporary MMIO
-	UINT32  Gpp1Config;               ///< Default PCIe GFX core configuration
-	UINT32  Gpp2Config;               ///< Default PCIe GPP2 core configuration
-	UINT32  Gpp3aConfig;              ///< Default PCIe GPP3a core configuration
-	UINT8   NbTransmitterDeemphasis;  ///< HT transmitter de-emphasis level
-	//	HT_PATH NbHtPath;                 ///< HT path to NB
-	UINT8   GlobalApicInterruptBase;  ///< Global APIC interrupt base that is used in MADT table for IO APIC.
-} NB_PLATFORM_CONFIG;
-
-/**
- * Bridge CIMx configuration
- */
-void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig);
-
-#endif //_RD890_CFG_H_
diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c
deleted file mode 100644
index d326a55020..0000000000
--- a/src/mainboard/tyan/s8226/romstage.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <lib.h>
-#include <reset.h>
-#include <stdint.h>
-#include <arch/io.h>
-#include <arch/cpu.h>
-#include <console/console.h>
-#include <arch/stages.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <northbridge/amd/agesa/family15/reset_test.h>
-#include <nb_cimx.h>
-#include <sb_cimx.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627dhg/w83627dhg.h>
-
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
-#define DUMMY_DEV PNP_DEV(0x2e, 0)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	u32 val;
-
-	/* Must come first to enable PCI MMCONF. */
-	amd_initmmio();
-
-	post_code(0x31);
-
-	/* For serial port. */
-	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
-	pci_write_config32(dev, 0x44, 0xff03ffd5);
-
-	/* Halt if there was a built in self test failure */
-	post_code(0x33);
-	report_bist_failure(bist);
-
-	sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
-	winbond_set_clksel_48(DUMMY_DEV);
-	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	sb7xx_51xx_disable_wideio(0);
-	post_code(0x34);
-
-	post_code(0x35);
-	console_init();
-
-	val = cpuid_eax(1);
-	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
-	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
-	post_code(0x37);
-	agesawrapper_amdinitreset();
-
-	if (!cpu_init_detectedx && boot_cpu()) {
-		post_code(0x38);
-		/*
-		 * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
-		 * Disable all Pcie Bridges to work around It.
-		 */
-		sr56x0_rd890_disable_pcie_bridge();
-		post_code(0x39);
-		nb_Poweron_Init();
-		post_code(0x3A);
-		sb_Poweron_Init();
-	}
-	post_code(0x3B);
-	agesawrapper_amdinitearly();
-
-	post_code(0x3C);
-	/* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default.
-	 * In order to access W83795G/ADG HWM using I2C protocol,
-	 * we select function to SDA, SCL function (or GP33, GP32 function).
-	 */
-	w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI));
-
-	nb_Ht_Init();
-	post_code(0x3D);
-	/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
-	if (!warm_reset_detect(0)) {
-		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
-		distinguish_cpu_resets(0);
-		soft_reset();
-		die("After soft_reset - shouldn't see this message!!!\n");
-	}
-
-	post_code(0x40);
-	agesawrapper_amdinitpost();
-
-	post_code(0x41);
-	agesawrapper_amdinitenv();
-	post_code(0x42);
-
-	post_code(0x50);
-	printk(BIOS_DEBUG, "Disabling cache as RAM ");
-	disable_cache_as_ram();
-	printk(BIOS_DEBUG, "done\n");
-
-	post_code(0x51);
-	copy_and_run();
-
-	/* We will not return,  Should never see this message and post code. */
-	printk(BIOS_DEBUG, "should not be here -\n");
-	post_code(0x54);
-}
diff --git a/src/mainboard/tyan/s8226/sb700_cfg.c b/src/mainboard/tyan/s8226/sb700_cfg.c
deleted file mode 100644
index d3a2651dc4..0000000000
--- a/src/mainboard/tyan/s8226/sb700_cfg.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#include <string.h>
-#include <console/console.h>    /* printk */
-#include "Platform.h"
-#include "sb700_cfg.h"
-
-
-/**
- * @brief South Bridge CIMx configuration
- *
- * should be called before exeucte CIMx function.
- * this function will be called in romstage and ramstage.
- */
-void sb700_cimx_config(AMDSBCFG *sb_config)
-{
-	if (!sb_config) {
-		printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - No sb_config.\n");
-		return;
-	}
-	printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - Start.\n");
-	memset(sb_config, 0, sizeof(AMDSBCFG));
-
-	/* SB_POWERON_INIT */
-	sb_config->StdHeader.Func = SB_POWERON_INIT;
-
-	/* header */
-	sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS;
-
-	/* static Build Parameters */
-	sb_config->BuildParameters.BiosSize = BIOS_SIZE;
-	sb_config->BuildParameters.LegacyFree = LEGACY_FREE;
-	sb_config->BuildParameters.EcKbd = 0;
-	sb_config->BuildParameters.EcChannel0 = 0;
-	sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS;
-	sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS;
-	sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS;
-	sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS;
-	sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS;
-
-	sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS;
-	sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS;
-	sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS;
-	sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS;
-	sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS;
-	sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT;
-	sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS;
-
-	sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID;
-	sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID;
-	sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID;
-	sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID;
-	sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID;
-	sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID;
-	sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID;
-	sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID;
-	sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID;
-	sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID;
-	sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID;
-	sb_config->BuildParameters.SmbusSsid = SMBUS_SSID;
-	sb_config->BuildParameters.IdeSsid = IDE_SSID;
-	sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID;
-	sb_config->BuildParameters.LpcSsid = LPC_SSID;
-
-	sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS;
-
-	/* General */
-	sb_config->Spi33Mhz = 1;
-	sb_config->SpreadSpectrum = 0;
-	sb_config->PciClk5 = 0;
-	sb_config->PciClks = 0x1F;
-	sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood
-	sb_config->TimerClockSource = 2;  // Auto
-	sb_config->S3Resume = 0;
-	sb_config->RebootRequired = 0;
-
-	/* HPET */
-	sb_config->HpetTimer = HPET_TIMER;
-
-	/* USB */
-	sb_config->UsbIntClock = 0;     // Use external clock
-	sb_config->Usb1Ohci0 = 1; //0:disable  1:enable Bus 0 Dev 18 Func0
-	sb_config->Usb1Ohci1 = 1; //0:disable  1:enable Bus 0 Dev 18 Func1
-	sb_config->Usb1Ehci  = 1; //0:disable  1:enable Bus 0 Dev 18 Func2
-	sb_config->Usb2Ohci0 = 1; //0:disable  1:enable Bus 0 Dev 19 Func0
-	sb_config->Usb2Ohci1 = 1; //0:disable  1:enable Bus 0 Dev 19 Func1
-	sb_config->Usb2Ehci  = 1; //0:disable  1:enable Bus 0 Dev 19 Func2
-	sb_config->Usb3Ohci  = 1; //0:disable  1:enable Bus 0 Dev 20 Func5
-	sb_config->UsbOhciLegacyEmulation = 1; //0:Enable  1:Disable
-
-	sb_config->AcpiS1Supported = 1;
-
-	/* SATA */
-	sb_config->SataController = 1;
-	sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci
-	sb_config->SataSmbus = 0;
-	sb_config->SataAggrLinkPmCap = 1;
-	sb_config->SataPortMultCap = 1;
-	sb_config->SataClkAutoOff = 1;
-	sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
-	//TODO: set to secondary not take effect.
-	sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled
-	sb_config->SataEspPort = 0;
-	sb_config->SataClkAutoOffAhciMode = 1;
-	sb_config->SataHpcpButNonESP = 0;
-	sb_config->SataHideUnusedPort = 0;
-
-	/* Azalia HDA */
-	sb_config->AzaliaController = AZALIA_CONTROLLER;
-	sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG;
-	sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN;
-	sb_config->pAzaliaOemCodecTablePtr = NULL;
-
-#ifndef __PRE_RAM__
-	/* ramstage cimx config here */
-	if (!sb_config->StdHeader.pCallBack) {
-		sb_config->StdHeader.pCallBack = sb700_callout_entry;
-	}
-
-	//sb_config->
-#endif //!__PRE_RAM__
-	printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - End.\n");
-}
diff --git a/src/mainboard/tyan/s8226/sb700_cfg.h b/src/mainboard/tyan/s8226/sb700_cfg.h
deleted file mode 100644
index bed9161f29..0000000000
--- a/src/mainboard/tyan/s8226/sb700_cfg.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#ifndef _SB700_CFG_H_
-#define _SB700_CFG_H_
-
-#include <stdint.h>
-
-
-/**
- * @def BIOS_SIZE_1M
- * @def BIOS_SIZE_2M
- * @def BIOS_SIZE_4M
- * @def BIOS_SIZE_8M
- */
-#define BIOS_SIZE_1M                    0
-#define BIOS_SIZE_2M                    1
-#define BIOS_SIZE_4M                    3
-#define BIOS_SIZE_8M                    7
-
-/* In SB700, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024)
-#define BIOS_SIZE BIOS_SIZE_1M
-#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048)
-#define BIOS_SIZE BIOS_SIZE_2M
-#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096)
-#define BIOS_SIZE BIOS_SIZE_4M
-#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192)
-#define BIOS_SIZE BIOS_SIZE_8M
-#endif
-#endif
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- *  0 - Disable Spread Spectrum function
- *  1 - Enable  Spread Spectrum function
- */
-#define SPREAD_SPECTRUM                 0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- *  0 - Disable hpet
- *  1 - Enable  hpet
- */
-#define HPET_TIMER                      1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- *   0 - Disable
- *   1 - Enable
- *  Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
- *  Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
- *  Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
- *  Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
- *  Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
- *  Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
- *  Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
- */
-#define USB_CINFIG              0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- *   0 - disable
- *   1 - enable
- *  PCI SLOT 0 define at BIT0
- *  PCI SLOT 1 define at BIT1
- *  PCI SLOT 2 define at BIT2
- *  PCI SLOT 3 define at BIT3
- *  PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL                  0x1F
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#ifndef SATA_CONTROLLER
-#define SATA_CONTROLLER               1
-#endif
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#ifndef SATA_MODE
-#define SATA_MODE                     NATIVE_IDE_MODE
-#endif
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE                 0
-#define IDE_NATIVE_MODE                 1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#ifndef SATA_IDE_MODE
-#define SATA_IDE_MODE                 IDE_LEGACY_MODE
-#endif
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- *  PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK          0x00
-#define INTERNAL_CLOCK          0x01
-
-#define SATA_CLOCK_SOURCE       EXTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED     1
-
-
-/**
- * @def   AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def   AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def   AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO                     0
-#define AZALIA_DISABLE                  1
-#define AZALIA_ENABLE                   2
-
-/**
- * @brief INCHIP HDA controller
- */
-#ifndef AZALIA_CONTROLLER
-#define AZALIA_CONTROLLER             AZALIA_AUTO
-#endif
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- *  0 - disable
- *  1 - enable
- */
-#ifndef AZALIA_PIN_CONFIG
-#define AZALIA_PIN_CONFIG             1
-#endif
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- *  SDIN0 is define at BIT0 & BIT1
- *   00 - GPIO PIN
- *   01 - Reserved
- *   10 - As a Azalia SDIN pin
- *  SDIN1 is define at BIT2 & BIT3
- *  SDIN2 is define at BIT4 & BIT5
- *  SDIN3 is define at BIT6 & BIT7
- */
-#ifndef AZALIA_SDIN_PIN
-#define AZALIA_SDIN_PIN              0x02
-#endif
-
-/**
- * @def GPP_CONTROLLER
- */
-#ifndef GPP_CONTROLLER
-#define GPP_CONTROLLER                1
-#endif
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- *  GPP_CFGMODE_X4000
- *  GPP_CFGMODE_X2200
- *  GPP_CFGMODE_X2110
- *  GPP_CFGMODE_X1111
- */
-#ifndef GPP_CFGMODE
-#define GPP_CFGMODE                   GPP_CFGMODE_X1111
-#endif
-
-
-/**
- * @brief South Bridge CIMx configuration
- *
- */
-void sb700_cimx_config(AMDSBCFG *sb_cfg);
-
-/**
- * @brief Entry point of Southbridge CIMx callout
- *
- * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
- *
- * @param[in] func    Southbridge CIMx Function ID.
- * @param[in] data    Southbridge Input Data.
- * @param[in] config  Southbridge configuration structure pointer.
- *
- */
-u32 sb700_callout_entry(u32 func, u32 data, void* config);
-
-#endif //_SB700_CFG_H_
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index 1f787f90b2..96f5e33fa7 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -96,7 +96,6 @@ void sb_before_pci_init(void)
 
 void sb_After_Pci_Init(void)
 {
-#if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
 	AMDSBCFG sb_early_cfg;
 
 	printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - Start.\n");
@@ -108,7 +107,6 @@ void sb_After_Pci_Init(void)
 	// VerifyImage() will fail, LocateImage() takes minutes to find the image.
 	sbAfterPciInit(&sb_early_cfg);
 	printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - End.\n");
-#endif
 }
 
 void sb_Mid_Post_Init(void)
@@ -128,7 +126,6 @@ void sb_Mid_Post_Init(void)
 
 void sb_Late_Post(void)
 {
-#if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
 	AMDSBCFG sb_early_cfg;
 	u8 data;
 
@@ -159,5 +156,4 @@ void sb_Late_Post(void)
 	}
 
 	printk(BIOS_SPEW, "SB900 - Early.c - sb_Late_Post - End.\n");
-#endif
 }
author	Kyösti Mälkki <kyosti.malkki@gmail.com>	2017-09-26 13:13:23 +0300
committer	Kyösti Mälkki <kyosti.malkki@gmail.com>	2018-01-17 13:23:33 +0000
commit	2bd6939dc5d2542e28734fa92aad6382535b8604 (patch)
tree	add236d8ffb48792ba18e57ed2057e96919f577e
parent	9e3ba212f34c6d9f2eb7dac8e4651f8ce12ab0c0 (diff)