mb/google/coral: Copy devicetree.cb from baseboard

It is a copy from baseboard/devicetree.cb  (coreboot.org ToT)

BUG=b:64880573
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage

Change-Id: I5db730c1974a96547fe7fda63689b7c5bfaefc66
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2 files changed, 232 insertions, 0 deletions

diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
index 61509b95d4..41d3dcb441 100644
--- a/src/mainboard/google/reef/Kconfig
+++ b/src/mainboard/google/reef/Kconfig
@@ -61,6 +61,7 @@ config VARIANT_DIR
 
 config DEVICETREE
 	string
+	default "variants/coral/devicetree.cb" if BOARD_GOOGLE_CORAL
 	default "variants/pyro/devicetree.cb" if BOARD_GOOGLE_PYRO
 	default "variants/sand/devicetree.cb" if BOARD_GOOGLE_SAND
 	default "variants/snappy/devicetree.cb" if BOARD_GOOGLE_SNAPPY
diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb
new file mode 100644
index 0000000000..d5f546c99b
--- /dev/null
+++ b/src/mainboard/google/reef/variants/coral/devicetree.cb
@@ -0,0 +1,231 @@
+chip soc/intel/apollolake
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	register "pcie_rp0_clkreq_pin" = "0"    # wifi/bt
+	# Disable unused clkreq of PCIe root ports
+	register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+
+	# GPIO for PERST_0
+	# If the Board has PERST_0 signal, assign the GPIO
+	# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
+	register "prt0_gpio" = "GPIO_122"
+
+	# GPIO for SD card detect
+	register "sdcard_cd_gpio" = "GPIO_177"
+
+	# EMMC TX DATA Delay 1
+	# Refer to EDS-Vol2-22.3.
+	# [14:8] steps of delay for HS400, each 125ps.
+	# [6:0] steps of delay for SDR104/HS200, each 125ps.
+	register "emmc_tx_data_cntl1" = "0x0C16"
+
+	# EMMC TX DATA Delay 2
+	# Refer to EDS-Vol2-22.3.
+	# [30:24] steps of delay for SDR50, each 125ps.
+	# [22:16] steps of delay for DDR50, each 125ps.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps.
+	# [6:0] steps of delay for SDR12, each 125ps.
+	register "emmc_tx_data_cntl2" = "0x28162828"
+
+	# EMMC RX CMD/DATA Delay 1
+	# Refer to EDS-Vol2-22.3.
+	# [30:24] steps of delay for SDR50, each 125ps.
+	# [22:16] steps of delay for DDR50, each 125ps.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps.
+	# [6:0] steps of delay for SDR12, each 125ps.
+	register "emmc_rx_cmd_data_cntl1" = "0x00181717"
+
+	# EMMC RX CMD/DATA Delay 2
+	# Refer to EDS-Vol2-22.3.
+	# [17:16] stands for Rx Clock before Output Buffer
+	# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
+	# [6:0] steps of delay for HS200, each 125ps.
+	register "emmc_rx_cmd_data_cntl2" = "0x10008"
+
+	# Enable DPTF
+	register "dptf_enable" = "1"
+
+	# PL1 override 12000 mW: the energy calculation is wrong with the
+	# current VR solution. Experiments show that SoC TDP max (6W) can
+	# be reached when RAPL PL1 is set to 12W.
+	register "tdp_pl1_override_mw" = "12000"
+	# Set RAPL PL2 to 15W.
+	register "tdp_pl2_override_mw" = "15000"
+
+	# Enable Audio Clock and Power gating
+	register "hdaudio_clk_gate_enable" = "1"
+	register "hdaudio_pwr_gate_enable" = "1"
+	register "hdaudio_bios_config_lockdown" = "1"
+
+	# Enable lpss s0ix
+	register "lpss_s0ix_enable" = "1"
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route, i.e., if this route changes then the affected GPE
+	# offset bits also need to be changed. This sets the PMC register
+	# GPE_CFG fields.
+	register "gpe0_dw1" = "PMC_GPE_N_31_0"
+	register "gpe0_dw2" = "PMC_GPE_N_63_32"
+	register "gpe0_dw3" = "PMC_GPE_SW_31_0"
+
+	# Enable I2C0 for audio codec at 400kHz
+	register "i2c[0]" = "{
+		.speed = I2C_SPEED_FAST,
+		.rise_time_ns = 104,
+		.fall_time_ns = 52,
+	}"
+
+	# Enable I2C2 bus early for TPM at 400kHz
+	register "i2c[2]" = "{
+		.early_init = 1,
+		.speed = I2C_SPEED_FAST,
+		.rise_time_ns = 57,
+		.fall_time_ns = 28,
+	}"
+
+	# touchscreen at 400kHz
+	register "i2c[3]" = "{
+		.speed = I2C_SPEED_FAST,
+		.rise_time_ns = 76,
+		.fall_time_ns = 164,
+	}"
+
+	# trackpad at 400kHz
+	register "i2c[4]" = "{
+		.speed = I2C_SPEED_FAST,
+		.rise_time_ns = 114,
+		.fall_time_ns = 164,
+		.data_hold_time_ns = 350,
+	}"
+
+	# digitizer at 400kHz
+	register "i2c[5]" = "{
+		.speed = I2C_SPEED_FAST,
+		.rise_time_ns = 152,
+		.fall_time_ns = 30,
+	}"
+
+	# Minimum SLP S3 assertion width 28ms.
+	register "slp_s3_assertion_width_usecs" = "28000"
+
+	device domain 0 on
+		device pci 00.0 on  end	# - Host Bridge
+		device pci 00.1 on  end	# - DPTF
+		device pci 00.2 on  end	# - NPK
+		device pci 02.0 on  end	# - Gen
+		device pci 03.0 on  end	# - Iunit
+		device pci 0d.0 on  end	# - P2SB
+		device pci 0d.1 on  end	# - PMC
+		device pci 0d.2 on  end	# - SPI
+		device pci 0d.3 on  end	# - Shared SRAM
+		device pci 0e.0 on	# - Audio
+			chip drivers/generic/max98357a
+				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
+				register "sdmode_delay" = "5"
+				device generic 0 on end
+			end
+		end
+		device pci 11.0 off end	# - ISH
+		device pci 12.0 off end	# - SATA
+		device pci 13.0 off end	# - Root Port 2 - PCIe-A 0
+		device pci 13.1 off end	# - Root Port 3 - PCIe-A 1
+		device pci 13.2 off end	# - Root Port 4 - PCIe-A 2
+		device pci 13.3 off end	# - Root Port 5 - PCIe-A 3
+		device pci 14.0 on
+			chip drivers/intel/wifi
+				register "wake" = "GPE0_DW3_00"
+				device pci 00.0 on end
+			end
+		end	# - Root Port 0 - PCIe-B 0 - Wifi
+		device pci 14.1 off end	# - Root Port 1 - PCIe-B 1
+		device pci 15.0 on  end	# - XHCI
+		device pci 15.1 off end # - XDCI
+		device pci 16.0 on	# - I2C 0
+			chip drivers/i2c/da7219
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
+				register "btn_cfg" = "50"
+				register "mic_det_thr" = "500"
+				register "jack_ins_deb" = "20"
+				register "jack_det_rate" = ""32ms_64ms""
+				register "jack_rem_deb" = "1"
+				register "a_d_btn_thr" = "0xa"
+				register "d_b_btn_thr" = "0x16"
+				register "b_c_btn_thr" = "0x21"
+				register "c_mic_btn_thr" = "0x3e"
+				register "btn_avg" = "4"
+				register "adc_1bit_rpt" = "1"
+				register "micbias_lvl" = "2600"
+				register "mic_amp_in_sel" = ""diff""
+				device i2c 1a on end
+			end
+		end
+		device pci 16.1 on  end	# - I2C 1
+		device pci 16.2 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
+				device i2c 50 on end
+			end
+		end	# - I2C 2
+		device pci 16.3 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0001""
+				register "desc" = ""ELAN Touchscreen""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)"
+				register "probed" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
+				register "reset_delay_ms" = "20"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
+				register "enable_delay_ms" = "1"
+				register "has_power_resource" = "1"
+				device i2c 10 on end
+			end
+		end	# - I2C 3
+		device pci 17.0 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_18_IRQ)"
+				register "wake" = "GPE0_DW1_15"
+				register "probed" = "1"
+				device i2c 15 on end
+			end
+		end # - I2C 4
+		device pci 17.1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""WCOM50C1""
+				register "generic.desc" = ""WCOM Digitizer""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_13_IRQ)"
+				register "hid_desc_reg_offset" = "0x1"
+				device i2c 0x9 on end
+			end
+		end	# - I2C 5
+		device pci 17.2 off end	# - I2C 6
+		device pci 17.3 off end	# - I2C 7
+		device pci 18.0 on  end	# - UART 0
+		device pci 18.1 on  end	# - UART 1
+		device pci 18.2 on  end	# - UART 2
+		device pci 18.3 off end	# - UART 3
+		device pci 19.0 on  end	# - SPI 0
+		device pci 19.1 off end	# - SPI 1
+		device pci 19.2 off end	# - SPI 2
+		device pci 1a.0 on  end	# - PWM
+		device pci 1b.0 on  end	# - SDCARD
+		device pci 1c.0 on  end	# - eMMC
+		device pci 1e.0 off end	# - SDIO
+		device pci 1f.0 on	# - LPC
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end
+		device pci 1f.1 on  end	# - SMBUS
+	end
+end