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authorArthur Heymans <arthur@aheymans.xyz>2021-01-18 00:48:27 +0100
committerAngel Pons <th3fanbus@gmail.com>2021-01-19 23:04:34 +0000
commit15ef9b651312fef3842fb5541e835ada8751b3fe (patch)
tree6f40e5afb285770e28fcf227b5ae5f1ad6fbc131
parenta6e4afc1cb44124562cdac1bea1c9fd81b9ecf27 (diff)
nb/intel/i945/northbridge.c: Reserve upper part of lower memory
This memory is used for option roms and BIOS. This matches the ACPI code. Change-Id: I53dd4b967569889108352ca70086a12ce252e8e0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--src/northbridge/intel/i945/northbridge.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 00d5be95b5..d2256729e9 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -107,12 +107,14 @@ static void mch_domain_read_resources(struct device *dev)
/* Report the memory regions */
ram_resource(dev, 3, 0, 0xa0000 / KiB);
- ram_resource(dev, 4, 0xc0000 / KiB, (tomk - 0xc0000 / KiB));
+ ram_resource(dev, 4, 1 * MiB / KiB, (tomk - 1 * MiB / KiB));
uma_resource(dev, 5, uma_memory_base / KiB, uma_memory_size / KiB);
mmio_resource(dev, 6, tseg_memory_base / KiB, tseg_memory_size / KiB);
uma_resource(dev, 7, cbmem_topk, delta_cbmem);
/* legacy VGA memory */
mmio_resource(dev, 8, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
+ /* RAM to be used for option roms and BIOS */
+ reserved_ram_resource(dev, 9, 0xc0000 / KiB, (1 * MiB - 0xc0000) / KiB);
}
static void mch_domain_set_resources(struct device *dev)