Samsung/exynos5250: convert unsigned {int,char} to u32/u8

The types are (esp. int) are confusing at times as to size.
Make them definite as to size.

Change-Id: Id7808f1f61649ec0a3403c1afc3c2c3d4302b7fb
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3103
Tested-by: build bot (Jenkins)
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>

1 files changed, 138 insertions, 137 deletions

diff --git a/src/cpu/samsung/exynos5250/s5p-dp.h b/src/cpu/samsung/exynos5250/s5p-dp.h
index 5322383e82..e11ac3b067 100644
--- a/src/cpu/samsung/exynos5250/s5p-dp.h
+++ b/src/cpu/samsung/exynos5250/s5p-dp.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2013 Google Inc.
  * (C) Copyright 2012 Samsung Electronics
  * Register map for Exynos5 DP
  *
@@ -23,143 +24,143 @@
 
 /* DSIM register map */
 struct exynos5_dp {
-	unsigned char	res1[0x10];
-	unsigned int	dp_tx_version;
-	unsigned int	dp_tx_sw_reset;
-	unsigned int	func_en_1;
-	unsigned int	func_en_2;
-	unsigned int	video_ctl_1;
-	unsigned int	video_ctl_2;
-	unsigned int	video_ctl_3;
-	unsigned int	video_ctl_4;
-	unsigned int	clr_blue_cb;
-	unsigned int	clr_green_y;
-	unsigned int	clr_red_cr;
-	unsigned int	video_ctl_8;
-	unsigned char	res2[0x4];
-	unsigned int	video_ctl_10;
-	unsigned int	total_line_l;
-	unsigned int	total_line_h;
-	unsigned int	active_line_l;
-	unsigned int	active_line_h;
-	unsigned int	v_f_porch;
-	unsigned int	vsync;
-	unsigned int	v_b_porch;
-	unsigned int	total_pixel_l;
-	unsigned int	total_pixel_h;
-	unsigned int	active_pixel_l;
-	unsigned int	active_pixel_h;
-	unsigned int	h_f_porch_l;
-	unsigned int	h_f_porch_h;
-	unsigned int	hsync_l;
-	unsigned int	hysnc_h;
-	unsigned int	h_b_porch_l;
-	unsigned int	h_b_porch_h;
-	unsigned int	vid_status;
-	unsigned int	total_line_sta_l;
-	unsigned int	total_line_sta_h;
-	unsigned int	active_line_sta_l;
-	unsigned int	active_line_sta_h;
-	unsigned int	v_f_porch_sta;
-	unsigned int	vsync_sta;
-	unsigned int	v_b_porch_sta;
-	unsigned int	total_pixel_sta_l;
-	unsigned int	total_pixel_sta_h;
-	unsigned int	active_pixel_sta_l;
-	unsigned int	active_pixel_sta_h;
-	unsigned int	h_f_porch_sta_l;
-	unsigned int	h_f_porch_sta_h;
-	unsigned int	hsync_sta_l;
-	unsigned int	hsync_sta_h;
-	unsigned int	h_b_porch_sta_l;
-	unsigned int	h_b_porch__sta_h;
-	unsigned char	res3[0x288];
-	unsigned int	lane_map;
-	unsigned char	res4[0x10];
-	unsigned int	analog_ctl_1;
-	unsigned int	analog_ctl_2;
-	unsigned int	analog_ctl_3;
-	unsigned int	pll_filter_ctl_1;
-	unsigned int	tx_amp_tuning_ctl;
-	unsigned char	res5[0xc];
-	unsigned int	aux_hw_retry_ctl;
-	unsigned char	res6[0x2c];
-	unsigned int	int_state;
-	unsigned int	common_int_sta_1;
-	unsigned int	common_int_sta_2;
-	unsigned int	common_int_sta_3;
-	unsigned int	common_int_sta_4;
-	unsigned char	res7[0x8];
-	unsigned int	dp_int_sta;
-	unsigned int	common_int_mask_1;
-	unsigned int	common_int_mask_2;
-	unsigned int	common_int_mask_3;
-	unsigned int	common_int_mask_4;
-	unsigned char	res8[0x08];
-	unsigned int	int_sta_mask;
-	unsigned int	int_ctl;
-	unsigned char	res9[0x200];
-	unsigned int	sys_ctl_1;
-	unsigned int	sys_ctl_2;
-	unsigned int	sys_ctl_3;
-	unsigned int	sys_ctl_4;
-	unsigned int	dp_vid_ctl;
-	unsigned char	res10[0x2c];
-	unsigned int	pkt_send_ctl;
-	unsigned char	res11[0x4];
-	unsigned int	dp_hdcp_ctl;
-	unsigned char	res12[0x34];
-	unsigned int	link_bw_set;
-	unsigned int	lane_count_set;
-	unsigned int	dp_training_ptn_set;
-	unsigned int	ln0_link_trn_ctl;
-	unsigned int	ln1_link_trn_ctl;
-	unsigned int	ln2_link_trn_ctl;
-	unsigned int	ln3_link_trn_ctl;
-	unsigned int	dp_dn_spread;
-	unsigned int	dp_hw_link_training;
-	unsigned char	res13[0x1c];
-	unsigned int	dp_debug_ctl;
-	unsigned int	dp_hpd_deglitch_l;
-	unsigned int	dp_hpd_deglitch_h;
-	unsigned char	res14[0x14];
-	unsigned int	dp_link_debug_ctl;
-	unsigned char	res15[0x1c];
-	unsigned int	m_vid_0;
-	unsigned int	m_vid_1;
-	unsigned int	m_vid_2;
-	unsigned int	n_vid_0;
-	unsigned int	n_vid_1;
-	unsigned int	n_vid_2;
-	unsigned int	m_vid_mon;
-	unsigned int	dp_pll_ctl;
-	unsigned int	dp_phy_pd;
-	unsigned int	dp_phy_test;
-	unsigned char	res16[0x8];
-	unsigned int	dp_video_fifo_thrd;
-	unsigned char	res17[0x8];
-	unsigned int	dp_audio_margin;
-	unsigned int	dp_dn_spread_ctl_1;
-	unsigned int	dp_dn_spread_ctl_2;
-	unsigned char	res18[0x18];
-	unsigned int	dp_m_cal_ctl;
-	unsigned int	m_vid_gen_filter_th;
-	unsigned char	res19[0x14];
-	unsigned int	m_aud_gen_filter_th;
-	unsigned int	aux_ch_sta;
-	unsigned int	aux_err_num;
-	unsigned int	aux_ch_defer_dtl;
-	unsigned int	aux_rx_comm;
-	unsigned int	buf_data_ctl;
-	unsigned int	aux_ch_ctl_1;
-	unsigned int	aux_addr_7_0;
-	unsigned int	aux_addr_15_8;
-	unsigned int	aux_addr_19_16;
-	unsigned int	aux_ch_ctl_2;
-	unsigned char   res20[0x18];
-	unsigned int	buf_data_0;
-	unsigned char	res21[0x3c];
-	unsigned int	soc_general_ctl;
+	u8	res1[0x10];
+	u32	dp_tx_version;
+	u32	dp_tx_sw_reset;
+	u32	func_en_1;
+	u32	func_en_2;
+	u32	video_ctl_1;
+	u32	video_ctl_2;
+	u32	video_ctl_3;
+	u32	video_ctl_4;
+	u32	clr_blue_cb;
+	u32	clr_green_y;
+	u32	clr_red_cr;
+	u32	video_ctl_8;
+	u8	res2[0x4];
+	u32	video_ctl_10;
+	u32	total_line_l;
+	u32	total_line_h;
+	u32	active_line_l;
+	u32	active_line_h;
+	u32	v_f_porch;
+	u32	vsync;
+	u32	v_b_porch;
+	u32	total_pixel_l;
+	u32	total_pixel_h;
+	u32	active_pixel_l;
+	u32	active_pixel_h;
+	u32	h_f_porch_l;
+	u32	h_f_porch_h;
+	u32	hsync_l;
+	u32	hysnc_h;
+	u32	h_b_porch_l;
+	u32	h_b_porch_h;
+	u32	vid_status;
+	u32	total_line_sta_l;
+	u32	total_line_sta_h;
+	u32	active_line_sta_l;
+	u32	active_line_sta_h;
+	u32	v_f_porch_sta;
+	u32	vsync_sta;
+	u32	v_b_porch_sta;
+	u32	total_pixel_sta_l;
+	u32	total_pixel_sta_h;
+	u32	active_pixel_sta_l;
+	u32	active_pixel_sta_h;
+	u32	h_f_porch_sta_l;
+	u32	h_f_porch_sta_h;
+	u32	hsync_sta_l;
+	u32	hsync_sta_h;
+	u32	h_b_porch_sta_l;
+	u32	h_b_porch__sta_h;
+	u8	res3[0x288];
+	u32	lane_map;
+	u8	res4[0x10];
+	u32	analog_ctl_1;
+	u32	analog_ctl_2;
+	u32	analog_ctl_3;
+	u32	pll_filter_ctl_1;
+	u32	tx_amp_tuning_ctl;
+	u8	res5[0xc];
+	u32	aux_hw_retry_ctl;
+	u8	res6[0x2c];
+	u32	int_state;
+	u32	common_int_sta_1;
+	u32	common_int_sta_2;
+	u32	common_int_sta_3;
+	u32	common_int_sta_4;
+	u8	res7[0x8];
+	u32	dp_int_sta;
+	u32	common_int_mask_1;
+	u32	common_int_mask_2;
+	u32	common_int_mask_3;
+	u32	common_int_mask_4;
+	u8	res8[0x08];
+	u32	int_sta_mask;
+	u32	int_ctl;
+	u8	res9[0x200];
+	u32	sys_ctl_1;
+	u32	sys_ctl_2;
+	u32	sys_ctl_3;
+	u32	sys_ctl_4;
+	u32	dp_vid_ctl;
+	u8	res10[0x2c];
+	u32	pkt_send_ctl;
+	u8	res11[0x4];
+	u32	dp_hdcp_ctl;
+	u8	res12[0x34];
+	u32	link_bw_set;
+	u32	lane_count_set;
+	u32	dp_training_ptn_set;
+	u32	ln0_link_trn_ctl;
+	u32	ln1_link_trn_ctl;
+	u32	ln2_link_trn_ctl;
+	u32	ln3_link_trn_ctl;
+	u32	dp_dn_spread;
+	u32	dp_hw_link_training;
+	u8	res13[0x1c];
+	u32	dp_debug_ctl;
+	u32	dp_hpd_deglitch_l;
+	u32	dp_hpd_deglitch_h;
+	u8	res14[0x14];
+	u32	dp_link_debug_ctl;
+	u8	res15[0x1c];
+	u32	m_vid_0;
+	u32	m_vid_1;
+	u32	m_vid_2;
+	u32	n_vid_0;
+	u32	n_vid_1;
+	u32	n_vid_2;
+	u32	m_vid_mon;
+	u32	dp_pll_ctl;
+	u32	dp_phy_pd;
+	u32	dp_phy_test;
+	u8	res16[0x8];
+	u32	dp_video_fifo_thrd;
+	u8	res17[0x8];
+	u32	dp_audio_margin;
+	u32	dp_dn_spread_ctl_1;
+	u32	dp_dn_spread_ctl_2;
+	u8	res18[0x18];
+	u32	dp_m_cal_ctl;
+	u32	m_vid_gen_filter_th;
+	u8	res19[0x14];
+	u32	m_aud_gen_filter_th;
+	u32	aux_ch_sta;
+	u32	aux_err_num;
+	u32	aux_ch_defer_dtl;
+	u32	aux_rx_comm;
+	u32	buf_data_ctl;
+	u32	aux_ch_ctl_1;
+	u32	aux_addr_7_0;
+	u32	aux_addr_15_8;
+	u32	aux_addr_19_16;
+	u32	aux_ch_ctl_2;
+	u8   res20[0x18];
+	u32	buf_data_0;
+	u8	res21[0x3c];
+	u32	soc_general_ctl;
 };
 /* DP_TX_SW_RESET */
 #define RESET_DP_TX				(1 << 0)