diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2009-06-30 15:17:49 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2009-06-30 15:17:49 +0000 |
| commit | 0867062412dd4bfe5a556e5f3fd85ba5b682d79b (patch) | |
| tree | 81ca5db12b8567b48daaa23a541bfb8a5dc011f8 | |
| parent | 9702b6bf7ec5a4fb16934f1cf2724480e2460c89 (diff) | |
This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
863 files changed, 14663 insertions, 14663 deletions
diff --git a/documentation/LinuxBIOS-AMD64.tex b/documentation/LinuxBIOS-AMD64.tex index 7ef2cdee3b..94fd8d7312 100644 --- a/documentation/LinuxBIOS-AMD64.tex +++ b/documentation/LinuxBIOS-AMD64.tex @@ -286,7 +286,7 @@ the build target configuration file All local configuration variables have to be declared before they can be used. Example: \begin{verbatim} - uses ROM_IMAGE_SIZE + uses CONFIG_ROM_IMAGE_SIZE \end{verbatim} \textbf{NOTE:} Only configuration variables known to the configuration @@ -303,20 +303,20 @@ configuration files. Example: \begin{verbatim} - default ROM_IMAGE_SIZE=0x10000 + default CONFIG_ROM_IMAGE_SIZE=0x10000 \end{verbatim} It is also possible to assign the value of one configuration variable to another one, i.e.: \begin{verbatim} - default FALLBACK_SIZE=ROM_SIZE + default CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE \end{verbatim} Also, simple expressions are allowed: \begin{verbatim} - default FALLBACK_SIZE=(ROM_SIZE - NORMAL_SIZE) + default CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE - NORMAL_SIZE) \end{verbatim} If an option contains a string, this string has to be protected with @@ -365,8 +365,8 @@ path to a static elf binary (i.e Linux kernel or etherboot) \begin{verbatim} romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Normal" mainboard amd/solo payload /suse/stepan/tg3ide_ @@ -382,7 +382,7 @@ together to the final coreboot image. It also specifies the order of the images and the final image size: \begin{verbatim} - buildrom ./solo.rom ROM_SIZE "normal" "fallback" + buildrom ./solo.rom CONFIG_ROM_SIZE "normal" "fallback" \end{verbatim} \end{itemize} @@ -408,12 +408,12 @@ machine. Use new \textit{chip\_configure} method for configuring (nonpci) devices. Set to \texttt{1} for all AMD64 mainboards. -\item \begin{verbatim}MAXIMUM_CONSOLE_LOGLEVEL\end{verbatim} +\item \begin{verbatim}CONFIG_MAXIMUM_CONSOLE_LOGLEVEL\end{verbatim} Errors or log messages up to this level can be printed. Default is \texttt{8}, minimum is \texttt{0}, maximum is \texttt{10}. -\item \begin{verbatim}DEFAULT_CONSOLE_LOGLEVEL\end{verbatim} +\item \begin{verbatim}CONFIG_DEFAULT_CONSOLE_LOGLEVEL\end{verbatim} Console will log at this level unless changed. Default is \texttt{7}, minimum is \texttt{0}, maximum is \texttt{10}. @@ -424,16 +424,16 @@ Log messages to 8250 uart based serial console. Default is \texttt{0} (don't log to serial console). This value should be set to \texttt{1} for all AMD64 builds. -\item \begin{verbatim}ROM_SIZE\end{verbatim} +\item \begin{verbatim}CONFIG_ROM_SIZE\end{verbatim} Size of final ROM image. This option has no default value. -\item \begin{verbatim}FALLBACK_SIZE\end{verbatim} +\item \begin{verbatim}CONFIG_FALLBACK_SIZE\end{verbatim} Fallback image size. Defaults to \texttt{65536} bytes. \textbf{NOTE:} This does not include the fallback payload. -\item \begin{verbatim}HAVE_OPTION_TABLE\end{verbatim} +\item \begin{verbatim}CONFIG_HAVE_OPTION_TABLE\end{verbatim} Export CMOS option table. Default is \texttt{0}. Set to \texttt{1} if your mainboard has CMOS memory and you want to use it to store @@ -444,7 +444,7 @@ coreboot parameters (Loglevel, serial line speed, ...) Boot image is located in ROM (as opposed to \texttt{CONFIG\_IDE\_PAYLOAD}, which will boot from an IDE disk) -\item \begin{verbatim}HAVE_FALLBACK_BOOT\end{verbatim} +\item \begin{verbatim}CONFIG_HAVE_FALLBACK_BOOT\end{verbatim} Set to \texttt{1} if fallback booting is required. Defaults to \texttt{0}. @@ -456,11 +456,11 @@ The following options should be used within a romimage section: \begin{itemize} -\item \begin{verbatim}USE_FALLBACK_IMAGE\end{verbatim} +\item \begin{verbatim}CONFIG_USE_FALLBACK_IMAGE\end{verbatim} Set to \texttt{1} to build a fallback image. Defaults to \texttt{0} -\item \begin{verbatim}ROM_IMAGE_SIZE\end{verbatim} +\item \begin{verbatim}CONFIG_ROM_IMAGE_SIZE\end{verbatim} Default image size. Defaults to \texttt{65535} bytes. @@ -544,14 +544,14 @@ do: \begin{verbatim} makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ./romcc" action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) \ - $(MAINBOARD)/auto.c -o $@" + $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ./romcc" action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) \ - $(MAINBOARD)/auto.c -o $@" + $(CONFIG_MAINBOARD)/auto.c -o $@" end \end{verbatim} @@ -747,26 +747,26 @@ They should be set using the \texttt{default} keyword: \begin{itemize} -\item \begin{verbatim}HAVE_HARD_RESET\end{verbatim} +\item \begin{verbatim}CONFIG_HAVE_HARD_RESET\end{verbatim} If set to \texttt{1}, this option defines that there is a hard reset function for this mainboard. This option is not defined per default. -\item \begin{verbatim}HAVE_PIRQ_TABLE\end{verbatim} +\item \begin{verbatim}CONFIG_HAVE_PIRQ_TABLE\end{verbatim} If set to \texttt{1}, this option defines that there is an IRQ Table for this mainboard. This option is not defined per default. -\item \begin{verbatim}IRQ_SLOT_COUNT\end{verbatim} +\item \begin{verbatim}CONFIG_IRQ_SLOT_COUNT\end{verbatim} Number of IRQ slots. This option is not defined per default. -\item \begin{verbatim}HAVE_MP_TABLE\end{verbatim} +\item \begin{verbatim}CONFIG_HAVE_MP_TABLE\end{verbatim} Define this option to build an MP table (v1.4). The default is not to build an MP table. -\item \begin{verbatim}HAVE_OPTION_TABLE\end{verbatim} +\item \begin{verbatim}CONFIG_HAVE_OPTION_TABLE\end{verbatim} Define this option to export a CMOS option table. The default is not to export a CMOS option table. @@ -787,23 +787,23 @@ system. Defaults to \texttt{1}. Set this option to \texttt{1} to enable IOAPIC support. This is mandatory if you want to boot a 64bit Linux kernel on an AMD64 system. -\item \begin{verbatim}STACK_SIZE\end{verbatim} +\item \begin{verbatim}CONFIG_STACK_SIZE\end{verbatim} coreboot stack size. The size of the function call stack defaults to \texttt{0x2000} (8k). -\item \begin{verbatim}HEAP_SIZE\end{verbatim} +\item \begin{verbatim}CONFIG_HEAP_SIZE\end{verbatim} coreboot heap size. The heap is used when coreboot allocates memory with malloc(). The default heap size is \texttt{0x2000}, but AMD64 boards generally set it to \texttt{0x4000} (16k) -\item \begin{verbatim}XIP_ROM_BASE\end{verbatim} +\item \begin{verbatim}CONFIG_XIP_ROM_BASE\end{verbatim} Start address of area to cache during coreboot execution directly from ROM. -\item \begin{verbatim}XIP_ROM_SIZE\end{verbatim} +\item \begin{verbatim}CONFIG_XIP_ROM_SIZE\end{verbatim} Size of area to cache during coreboot execution directly from ROM @@ -1075,8 +1075,8 @@ Mainboards that provide an IRQ table should have the following two variables set in their \texttt{Config.lb} file: \begin{verbatim} -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=7 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=7 \end{verbatim} This will make coreboot look for the file \\ @@ -1106,7 +1106,7 @@ mainboard specific configuration file \begin{verbatim} default CONFIG_SMP=1 default CONFIG_MAX_CPUS=1 # 2,4,.. -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 \end{verbatim} coreboot will then look for a function for setting up the MP table in @@ -1136,9 +1136,9 @@ framework that can generate the following tables: To enable ACPI in your coreboot build, add the following lines to your configuration files: \begin{verbatim} -uses HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_TABLES [..] -option HAVE_ACPI_TABLES=1 +option CONFIG_HAVE_ACPI_TABLES=1 \end{verbatim} To keep Linux doing it's pci ressource allocation based on IRQ tables and MP @@ -1234,12 +1234,12 @@ When changing speed and width of hypertransport chain connections coreboot has to either assert an LDTSTOP or a reset to make the changes become active. Additionally Linux can do a firmware reset, if coreboot provides the needed infrastructure. To use this capability, define the -option \texttt{HAVE\_HARD\_RESET} and add an object file specifying the +option \texttt{HAVE\_HARD\CONFIG_RESET} and add an object file specifying the reset code in your mainboard specific configuration file \texttt{coreboot-v2/src/mainboard/$<$vendor$>$/$<$mainboard$>$/Config.lb}: \begin{verbatim} - default HAVE_HARD_RESET=1 + default CONFIG_HAVE_HARD_RESET=1 object reset.o \end{verbatim} @@ -1529,7 +1529,7 @@ was added for many AMD CPUs, which both simplified and complicated things. Simpl There are two big additions to the build process and, furthermore, more than two new CONFIG variables to control them. \begin{itemize} -\item \begin{verbatim}USE_DCACHE_RAM\end{verbatim} +\item \begin{verbatim}CONFIG_USE_DCACHE_RAM\end{verbatim} Set to \texttt{1} to use Cache As Ram (CAR). Defaults to \texttt{0} @@ -1552,7 +1552,7 @@ A coreboot rom file consists of one or more \textit{images}. All images consist ROMCC images are so-called because C code for the ROM part is compiled with romcc. romcc is an optimizing C compiler which compiles one, and only one file; to get more than one file, one must include the C code via include statements. The main ROM code .c file is usually called auto.c. \subsubsection{How it is built} -Romcc compiles auto.c to produce auto.inc. auto.inc is included in the main crt0.S, which is then preprocessed to produce crt0.s. The inclusion of files into crt0.S is controlled by the CRT0\_INCLUDES variable. crt0.s is then assembled. +Romcc compiles auto.c to produce auto.inc. auto.inc is included in the main crt0.S, which is then preprocessed to produce crt0.s. The inclusion of files into crt0.S is controlled by the CONFIG_CRT0\_INCLUDES variable. crt0.s is then assembled. File for the ram part are compiled in a conventional manner. @@ -1575,8 +1575,8 @@ As we mentioned, the ROM file consists of multiple images. In the basic file, th \begin{itemize} \item PAYLOAD\_SIZE. Each image may have a different payload size. -\item \_ROMBASE Each image must have a different base in rom. -\item \_RESET Unclear what this is used for. +\item \CONFIG_ROMBASE Each image must have a different base in rom. +\item \CONFIG_RESET Unclear what this is used for. \item \_EXCEPTION\_VECTORS where an optional IDT might go. \item USE\_OPTION\_TABLE if set, an option table section will be linked in. \item CONFIG\_ROM\_PAYLOAD\_START This is the soon-to-be-deprecated way of locating a payload. cbfs eliminates this. @@ -1608,7 +1608,7 @@ If fallback has been built in, some setup needs to be done. On some machines, it ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -1619,7 +1619,7 @@ If fallback has been built in, some setup needs to be done. On some machines, it How does the fallback image get the symbol for normal entry? Via magic in the ldscript.ld -- remember, the images are not linked to each other. Finally, we can see this in the Config.lb for most mainboards: \begin{verbatim} -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -1771,10 +1771,10 @@ Confusingly enough, almost all the uses of these two variables are either nested The fallback and normal builds are the same. The target config has a new clause that looks like this: \begin{verbatim} romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="\$(shell cat ../../VERSION)\_Failover" end \end{verbatim} diff --git a/documentation/RFC/config.tex b/documentation/RFC/config.tex index d5626b92e1..879083e971 100644 --- a/documentation/RFC/config.tex +++ b/documentation/RFC/config.tex @@ -173,7 +173,7 @@ A sample file: target x # over-ride the default rom size in the mainboard file -option ROM_SIZE=1024*1024 +option CONFIG_ROM_SIZE=1024*1024 mainboard amd/solo end @@ -188,8 +188,8 @@ Sample mainboard file arch i386 end cpu k8 end # -option DEBUG=1 -default USE_FALLBACK_IMAGE=1 +option CONFIG_DEBUG=1 +default CONFIG_USE_FALLBACK_IMAGE=1 option A=(1+2) option B=0xa # @@ -204,7 +204,7 @@ ldscript cpu/i386/entry32.lds ### ### Build our reset vector (This is where linuxBIOS is entered) ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/i386/reset16.inc ldscript cpu/i386/reset16.lds else @@ -214,15 +214,15 @@ end . . . -if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end +if CONFIG_USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end # ### ### Romcc output ### -#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E" +#makerule ./failover.E dep "$(CONFIG_MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c > ./failever.E" #makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc" #mainboardinit ./failover.inc -makerule ./auto.E dep "$(MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" +makerule ./auto.E dep "$(CONFIG_MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c > ./auto.E" makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc" mainboardinit ./auto.inc # @@ -250,8 +250,8 @@ cpu k8 end ##object mainboard.o driver mainboard.o object static_devices.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end ### Location of the DIMM EEPROMS on the SMBUS ### This is fixed into a narrow range by the DIMM package standard. ### @@ -261,8 +261,8 @@ option SMBUS_MEM_DEVICE_INC=1 # ### The linuxBIOS bootloader. ### -option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE) +option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) # \end{verbatim} @@ -272,17 +272,17 @@ handle. Makefile.settings looks like this, for example: \begin{verbatim} TOP:=/home/rminnich/src/yapps2/freebios2 TARGET_DIR:=x -export MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo -export ARCH:=i386 -export _RAMBASE:=0x4000 -export ROM_IMAGE_SIZE:=65535 -export PAYLOAD_SIZE:=131073 +export CONFIG_MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo +export CONFIG_ARCH:=i386 +export CONFIG_RAMBASE:=0x4000 +export CONFIG_ROM_IMAGE_SIZE:=65535 +export CONFIG_PAYLOAD_SIZE:=131073 export CONFIG_MAX_CPUS:=1 -export HEAP_SIZE:=8192 -export STACK_SIZE:=8192 -export MEMORY_HOLE:=0 +export CONFIG_HEAP_SIZE:=8192 +export CONFIG_STACK_SIZE:=8192 +export CONFIG_MEMORY_HOLE:=0 export COREBOOT_VERSION:=1.1.0 -export CC:=$(CROSS_COMPILE)gcc +export CC:=$(CONFIG_CROSS_COMPILE)gcc \end{verbatim} diff --git a/src/arch/i386/Config.lb b/src/arch/i386/Config.lb index 68b4310248..6a851a5cb7 100644 --- a/src/arch/i386/Config.lb +++ b/src/arch/i386/Config.lb @@ -2,14 +2,14 @@ uses CONFIG_CBFS uses CONFIG_SMP uses CONFIG_PRECOMPRESSED_PAYLOAD uses CONFIG_USE_INIT -uses HAVE_FAILOVER_BOOT -uses USE_FAILOVER_IMAGE -uses USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_USE_FALLBACK_IMAGE init init/crt0.S.lb if CONFIG_CBFS - if USE_FAILOVER_IMAGE + if CONFIG_USE_FAILOVER_IMAGE else initobject /src/lib/cbfs.o initobject /src/console/vsprintf.o @@ -17,8 +17,8 @@ if CONFIG_CBFS end end -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript init/ldscript_failover.lb else if CONFIG_CBFS @@ -29,13 +29,13 @@ if HAVE_FAILOVER_BOOT end else if CONFIG_CBFS - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript init/ldscript_fallback_cbfs.lb else ldscript init/ldscript_cbfs.lb end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript init/ldscript_fallback.lb else ldscript init/ldscript.lb @@ -54,7 +54,7 @@ end makerule nrv2b depends "$(TOP)/util/nrv2b/nrv2b.c" - action "$(HOSTCC) -O2 -DENCODE -DDECODE -DMAIN -DVERBOSE -DNDEBUG -DBITSIZE=32 -DENDIAN=0 $< -o $@" + action "$(CONFIG_HOSTCC) -O2 -DENCODE -DDECODE -DMAIN -DVERBOSE -DNDEBUG -DBITSIZE=32 -DENDIAN=0 $< -o $@" end makerule payload @@ -91,7 +91,7 @@ if CONFIG_PRECOMPRESSED_PAYLOAD makedefine PAYLOAD-1:=payload end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE makedefine COREBOOT_APC:= makedefine COREBOOT_RAM_ROM:= @@ -102,13 +102,13 @@ if USE_FAILOVER_IMAGE else makerule coreboot.rom depends "coreboot.strip buildrom $(PAYLOAD-1)" - action "PAYLOAD=$(PAYLOAD-1); if [ $(CONFIG_CBFS) -eq 1 ]; then PAYLOAD=/dev/null; touch cbfs-support; fi; ./buildrom $< $@ $$PAYLOAD $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)" + action "PAYLOAD=$(PAYLOAD-1); if [ $(CONFIG_CBFS) -eq 1 ]; then PAYLOAD=/dev/null; touch cbfs-support; fi; ./buildrom $< $@ $$PAYLOAD $(CONFIG_ROM_IMAGE_SIZE) $(CONFIG_ROM_SECTION_SIZE)" action "if [ $(CONFIG_COMPRESSED_PAYLOAD_LZMA) -eq 1 -a $(CONFIG_CBFS) -eq 1 ]; then echo l > cbfs-support; fi" end end makerule crt0.S - depends "$(CRT0)" + depends "$(CONFIG_CRT0)" action "cp $< $@" end @@ -118,13 +118,13 @@ if CONFIG_USE_INIT makerule init.o depends "$(INIT-OBJECTS)" action "$(LD) -melf_i386 -r -o init.pre.o $(INIT-OBJECTS)" - action "$(OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o" + action "$(CONFIG_OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o" end makerule coreboot depends "crt0.o init.o $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld" action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o" - action "$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map" + action "$(CONFIG_CROSS_COMPILE)nm -n coreboot | sort > coreboot.map" end end diff --git a/src/arch/i386/boot/Config.lb b/src/arch/i386/boot/Config.lb index 4b22010461..9c576921a0 100644 --- a/src/arch/i386/boot/Config.lb +++ b/src/arch/i386/boot/Config.lb @@ -1,7 +1,7 @@ -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_MULTIBOOT -uses HAVE_ACPI_RESUME +uses CONFIG_HAVE_ACPI_RESUME object boot.o object coreboot_table.o @@ -9,13 +9,13 @@ if CONFIG_MULTIBOOT object multiboot.o end object tables.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object pirq_routing.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi.o object acpigen.o -if HAVE_ACPI_RESUME +if CONFIG_HAVE_ACPI_RESUME object wakeup.S end end diff --git a/src/arch/i386/boot/acpi.c b/src/arch/i386/boot/acpi.c index 658c1b32d8..c0c57190ad 100644 --- a/src/arch/i386/boot/acpi.c +++ b/src/arch/i386/boot/acpi.c @@ -390,18 +390,18 @@ void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt) rsdp->ext_checksum = acpi_checksum((void *)rsdp, sizeof(acpi_rsdp_t)); } -#if HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME == 1 void suspend_resume(void) { void *wake_vec; #if 0 -#if MEM_TRAIN_SEQ != 0 - #error "So far it works on AMD and MEM_TRAIN_SEQ == 0" +#if CONFIG_MEM_TRAIN_SEQ != 0 + #error "So far it works on AMD and CONFIG_MEM_TRAIN_SEQ == 0" #endif -#if _RAMBASE < 0x1F00000 - #error "For ACPI RESUME you need to have _RAMBASE at least 31MB" +#if CONFIG_RAMBASE < 0x1F00000 + #error "For ACPI RESUME you need to have CONFIG_RAMBASE at least 31MB" #error "Chipset support (S3_NVRAM_EARLY and ACPI_IS_WAKEUP_EARLY functions and memory ctrl)" #error "And coreboot memory reserved in mainboard.c" #endif diff --git a/src/arch/i386/boot/coreboot_table.c b/src/arch/i386/boot/coreboot_table.c index 431ff368cd..659ab0f90e 100644 --- a/src/arch/i386/boot/coreboot_table.c +++ b/src/arch/i386/boot/coreboot_table.c @@ -76,15 +76,15 @@ struct lb_memory *lb_memory(struct lb_header *header) struct lb_serial *lb_serial(struct lb_header *header) { -#if defined(TTYS0_BASE) +#if defined(CONFIG_TTYS0_BASE) struct lb_record *rec; struct lb_serial *serial; rec = lb_new_record(header); serial = (struct lb_serial *)rec; serial->tag = LB_TAG_SERIAL; serial->size = sizeof(*serial); - serial->ioport = TTYS0_BASE; - serial->baud = TTYS0_BAUD; + serial->ioport = CONFIG_TTYS0_BASE; + serial->baud = CONFIG_TTYS0_BAUD; return serial; #else return header; @@ -157,9 +157,9 @@ struct cmos_checksum *lb_cmos_checksum(struct lb_header *header) cmos_checksum->size = (sizeof(*cmos_checksum)); - cmos_checksum->range_start = LB_CKS_RANGE_START * 8; - cmos_checksum->range_end = ( LB_CKS_RANGE_END * 8 ) + 7; - cmos_checksum->location = LB_CKS_LOC * 8; + cmos_checksum->range_start = CONFIG_LB_CKS_RANGE_START * 8; + cmos_checksum->range_end = ( CONFIG_LB_CKS_RANGE_END * 8 ) + 7; + cmos_checksum->location = CONFIG_LB_CKS_LOC * 8; cmos_checksum->type = CHECKSUM_PCBIOS; return cmos_checksum; @@ -413,7 +413,7 @@ static struct lb_memory *build_lb_mem(struct lb_header *head) return mem; } -#if HAVE_HIGH_TABLES == 1 +#if CONFIG_HAVE_HIGH_TABLES == 1 extern uint64_t high_tables_base, high_tables_size; #endif @@ -424,7 +424,7 @@ unsigned long write_coreboot_table( struct lb_header *head; struct lb_memory *mem; -#if HAVE_HIGH_TABLES == 1 +#if CONFIG_HAVE_HIGH_TABLES == 1 printk_debug("Writing high table forward entry at 0x%08lx\n", low_table_end); head = lb_table_init(low_table_end); @@ -460,7 +460,7 @@ unsigned long write_coreboot_table( rom_table_end &= ~0xffff; printk_debug("0x%08lx \n", rom_table_end); -#if (HAVE_OPTION_TABLE == 1) +#if (CONFIG_HAVE_OPTION_TABLE == 1) { struct lb_record *rec_dest, *rec_src; /* Write the option config table... */ @@ -482,13 +482,13 @@ unsigned long write_coreboot_table( lb_add_memory_range(mem, LB_MEM_TABLE, rom_table_start, rom_table_end-rom_table_start); -#if HAVE_HIGH_TABLES == 1 +#if CONFIG_HAVE_HIGH_TABLES == 1 printk_debug("Adding high table area\n"); lb_add_memory_range(mem, LB_MEM_TABLE, high_tables_base, high_tables_size); #endif -#if (HAVE_MAINBOARD_RESOURCES == 1) +#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1) add_mainboard_resources(mem); #endif diff --git a/src/arch/i386/boot/pirq_routing.c b/src/arch/i386/boot/pirq_routing.c index 598cc3ca8d..0c470082e0 100644 --- a/src/arch/i386/boot/pirq_routing.c +++ b/src/arch/i386/boot/pirq_routing.c @@ -3,7 +3,7 @@ #include <string.h> #include <device/pci.h> -#if (DEBUG==1 && HAVE_PIRQ_TABLE==1) +#if (CONFIG_DEBUG==1 && CONFIG_HAVE_PIRQ_TABLE==1) static void check_pirq_routing_table(struct irq_routing_table *rt) { uint8_t *addr = (uint8_t *)rt; @@ -12,7 +12,7 @@ static void check_pirq_routing_table(struct irq_routing_table *rt) printk_info("Checking Interrupt Routing Table consistency...\n"); -#if defined(IRQ_SLOT_COUNT) +#if defined(CONFIG_IRQ_SLOT_COUNT) if (sizeof(struct irq_routing_table) != rt->size) { printk_warning("Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n", sizeof(struct irq_routing_table), @@ -83,7 +83,7 @@ static int verify_copy_pirq_routing_table(unsigned long addr) #define verify_copy_pirq_routing_table(addr) #endif -#if HAVE_PIRQ_TABLE==1 +#if CONFIG_HAVE_PIRQ_TABLE==1 unsigned long copy_pirq_routing_table(unsigned long addr) { /* Align the table to be 16 byte aligned. */ @@ -100,7 +100,7 @@ unsigned long copy_pirq_routing_table(unsigned long addr) } #endif -#if (PIRQ_ROUTE==1 && HAVE_PIRQ_TABLE==1) +#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_HAVE_PIRQ_TABLE==1) void pirq_routing_irqs(unsigned long addr) { int i, j, k, num_entries; diff --git a/src/arch/i386/boot/tables.c b/src/arch/i386/boot/tables.c index 2dbfa7adcc..9991415eda 100644 --- a/src/arch/i386/boot/tables.c +++ b/src/arch/i386/boot/tables.c @@ -104,7 +104,7 @@ struct lb_memory *write_tables(void) post_code(0x9a); /* Write ACPI tables to F segment and high tables area */ -#if HAVE_ACPI_TABLES == 1 +#if CONFIG_HAVE_ACPI_TABLES == 1 if (high_tables_base) { unsigned long acpi_start = high_table_end; rom_table_end = ALIGN(rom_table_end, 16); @@ -129,7 +129,7 @@ struct lb_memory *write_tables(void) #endif post_code(0x9b); -#if HAVE_MP_TABLE == 1 +#if CONFIG_HAVE_MP_TABLE == 1 /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ rom_table_end = write_smp_table(rom_table_end); rom_table_end = ALIGN(rom_table_end, 1024); @@ -139,7 +139,7 @@ struct lb_memory *write_tables(void) high_table_end = write_smp_table(high_table_end); high_table_end = ALIGN(high_table_end, 1024); } -#endif /* HAVE_MP_TABLE */ +#endif /* CONFIG_HAVE_MP_TABLE */ post_code(0x9c); diff --git a/src/arch/i386/include/arch/acpi.h b/src/arch/i386/include/arch/acpi.h index c2ed67971e..5b5797fcd1 100644 --- a/src/arch/i386/include/arch/acpi.h +++ b/src/arch/i386/include/arch/acpi.h @@ -13,11 +13,11 @@ #ifndef __ASM_ACPI_H #define __ASM_ACPI_H -#if HAVE_ACPI_TABLES==1 +#if CONFIG_HAVE_ACPI_TABLES==1 #include <stdint.h> -#if HAVE_ACPI_RESUME +#if CONFIG_HAVE_ACPI_RESUME /* 0 = S0, 1 = S1 ...*/ extern u8 acpi_slp_type; #endif @@ -88,13 +88,13 @@ typedef struct acpi_table_header /* ACPI common table header */ /* RSDT */ typedef struct acpi_rsdt { struct acpi_table_header header; - u32 entry[7+ACPI_SSDTX_NUM+CONFIG_MAX_CPUS]; /* MCONFIG, HPET, FADT, SRAT, SLIT, MADT(APIC), SSDT, SSDTX, and SSDT for CPU pstate*/ + u32 entry[7+CONFIG_ACPI_SSDTX_NUM+CONFIG_MAX_CPUS]; /* MCONFIG, HPET, FADT, SRAT, SLIT, MADT(APIC), SSDT, SSDTX, and SSDT for CPU pstate*/ } __attribute__ ((packed)) acpi_rsdt_t; /* XSDT */ typedef struct acpi_xsdt { struct acpi_table_header header; - u64 entry[6+ACPI_SSDTX_NUM]; + u64 entry[6+CONFIG_ACPI_SSDTX_NUM]; } __attribute__ ((packed)) acpi_xsdt_t; /* HPET TIMERS */ @@ -367,7 +367,7 @@ void acpi_create_facs(acpi_facs_t *facs); void acpi_write_rsdt(acpi_rsdt_t *rsdt); void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt); -#if HAVE_ACPI_RESUME +#if CONFIG_HAVE_ACPI_RESUME void suspend_resume(void); void *acpi_find_wakeup_vector(void); void *acpi_get_wakeup_rsdp(void); @@ -390,7 +390,7 @@ do { \ #define IO_APIC_ADDR 0xfec00000UL -#else // HAVE_ACPI_TABLES +#else // CONFIG_HAVE_ACPI_TABLES #define write_acpi_tables(start) (start) diff --git a/src/arch/i386/include/arch/cpu.h b/src/arch/i386/include/arch/cpu.h index ebe6ed155c..f49b7cb50a 100644 --- a/src/arch/i386/include/arch/cpu.h +++ b/src/arch/i386/include/arch/cpu.h @@ -128,8 +128,8 @@ static inline struct cpu_info *cpu_info(void) __asm__("andl %%esp,%0; " "orl %2, %0 " :"=r" (ci) - : "0" (~(STACK_SIZE - 1)), - "r" (STACK_SIZE - sizeof(struct cpu_info)) + : "0" (~(CONFIG_STACK_SIZE - 1)), + "r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) ); return ci; } diff --git a/src/arch/i386/include/arch/pci_ops.h b/src/arch/i386/include/arch/pci_ops.h index 04b93196aa..9c4e029b24 100644 --- a/src/arch/i386/include/arch/pci_ops.h +++ b/src/arch/i386/include/arch/pci_ops.h @@ -4,7 +4,7 @@ extern const struct pci_bus_operations pci_cf8_conf1; extern const struct pci_bus_operations pci_cf8_conf2; -#if MMCONF_SUPPORT==1 +#if CONFIG_MMCONF_SUPPORT==1 extern const struct pci_bus_operations pci_ops_mmconf; #endif diff --git a/src/arch/i386/include/arch/pciconf.h b/src/arch/i386/include/arch/pciconf.h index 5887522c8b..09133b5567 100644 --- a/src/arch/i386/include/arch/pciconf.h +++ b/src/arch/i386/include/arch/pciconf.h @@ -5,7 +5,7 @@ #define PCI_CONF_REG_INDEX 0xcf8 #define PCI_CONF_REG_DATA 0xcfc -#if PCI_IO_CFG_EXT == 0 +#if CONFIG_PCI_IO_CFG_EXT == 0 #define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where)) #else #define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where & 0xff) | ((where & 0xf00)<<16) ) diff --git a/src/arch/i386/include/arch/pirq_routing.h b/src/arch/i386/include/arch/pirq_routing.h index d3d61a282d..15c616b442 100644 --- a/src/arch/i386/include/arch/pirq_routing.h +++ b/src/arch/i386/include/arch/pirq_routing.h @@ -16,8 +16,8 @@ struct irq_info { uint8_t rfu; } __attribute__((packed)); -#if defined(IRQ_SLOT_COUNT) -#define IRQ_SLOTS_COUNT IRQ_SLOT_COUNT +#if defined(CONFIG_IRQ_SLOT_COUNT) +#define IRQ_SLOTS_COUNT CONFIG_IRQ_SLOT_COUNT #elif (__GNUC__ < 3) #define IRQ_SLOTS_COUNT 1 #else @@ -39,10 +39,10 @@ struct irq_routing_table { extern const struct irq_routing_table intel_irq_routing_table; -#if HAVE_PIRQ_TABLE==1 +#if CONFIG_HAVE_PIRQ_TABLE==1 unsigned long copy_pirq_routing_table(unsigned long start); unsigned long write_pirq_routing_table(unsigned long start); -#if PIRQ_ROUTE==1 +#if CONFIG_PIRQ_ROUTE==1 void pirq_routing_irqs(unsigned long start); void pirq_assign_irqs(const unsigned char pIntAtoD[4]); #else diff --git a/src/arch/i386/include/arch/romcc_io.h b/src/arch/i386/include/arch/romcc_io.h index aaba32ab01..fca27c4ec6 100644 --- a/src/arch/i386/include/arch/romcc_io.h +++ b/src/arch/i386/include/arch/romcc_io.h @@ -34,7 +34,7 @@ static inline __attribute__((always_inline)) void write32(unsigned long addr, ui *((volatile uint32_t *)(addr)) = value; } -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT #include <arch/mmio_conf.h> @@ -92,7 +92,7 @@ typedef unsigned device_t; /* pci and pci_mmio need to have different ways to ha static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where) { unsigned addr; -#if PCI_IO_CFG_EXT == 0 +#if CONFIG_PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; #else addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0 @@ -101,17 +101,17 @@ static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_ return inb(0xCFC + (addr & 3)); } -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where) { unsigned addr; - addr = MMCONF_BASE_ADDRESS | dev | where; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; return read8x(addr); } #endif static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where) { -#if MMCONF_SUPPORT_DEFAULT +#if CONFIG_MMCONF_SUPPORT_DEFAULT return pci_mmio_read_config8(dev, where); #else return pci_io_read_config8(dev, where); @@ -121,7 +121,7 @@ static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t d static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where) { unsigned addr; -#if PCI_IO_CFG_EXT == 0 +#if CONFIG_PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; #else addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); @@ -130,18 +130,18 @@ static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(devic return inw(0xCFC + (addr & 2)); } -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where) { unsigned addr; - addr = MMCONF_BASE_ADDRESS | dev | where; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; return read16x(addr); } #endif static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where) { -#if MMCONF_SUPPORT_DEFAULT +#if CONFIG_MMCONF_SUPPORT_DEFAULT return pci_mmio_read_config16(dev, where); #else return pci_io_read_config16(dev, where); @@ -152,7 +152,7 @@ static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where) { unsigned addr; -#if PCI_IO_CFG_EXT == 0 +#if CONFIG_PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; #else addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); @@ -161,18 +161,18 @@ static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(devic return inl(0xCFC); } -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where) { unsigned addr; - addr = MMCONF_BASE_ADDRESS | dev | where; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; return read32x(addr); } #endif static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where) { -#if MMCONF_SUPPORT_DEFAULT +#if CONFIG_MMCONF_SUPPORT_DEFAULT return pci_mmio_read_config32(dev, where); #else return pci_io_read_config32(dev, where); @@ -182,7 +182,7 @@ static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) { unsigned addr; -#if PCI_IO_CFG_EXT == 0 +#if CONFIG_PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; #else addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); @@ -191,18 +191,18 @@ static inline __attribute__((always_inline)) void pci_io_write_config8(device_t outb(value, 0xCFC + (addr & 3)); } -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value) { unsigned addr; - addr = MMCONF_BASE_ADDRESS | dev | where; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; write8x(addr, value); } #endif static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value) { -#if MMCONF_SUPPORT_DEFAULT +#if CONFIG_MMCONF_SUPPORT_DEFAULT pci_mmio_write_config8(dev, where, value); #else pci_io_write_config8(dev, where, value); @@ -213,7 +213,7 @@ static inline __attribute__((always_inline)) void pci_write_config8(device_t dev static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) { unsigned addr; -#if PCI_IO_CFG_EXT == 0 +#if CONFIG_PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; #else addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); @@ -222,18 +222,18 @@ static inline __attribute__((always_inline)) void pci_io_write_config16(device_t outw(value, 0xCFC + (addr & 2)); } -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value) { unsigned addr; - addr = MMCONF_BASE_ADDRESS | dev | where; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; write16x(addr, value); } #endif static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value) { -#if MMCONF_SUPPORT_DEFAULT +#if CONFIG_MMCONF_SUPPORT_DEFAULT pci_mmio_write_config16(dev, where, value); #else pci_io_write_config16(dev, where, value); @@ -244,7 +244,7 @@ static inline __attribute__((always_inline)) void pci_write_config16(device_t de static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) { unsigned addr; -#if PCI_IO_CFG_EXT == 0 +#if CONFIG_PCI_IO_CFG_EXT == 0 addr = (dev>>4) | where; #else addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); @@ -253,18 +253,18 @@ static inline __attribute__((always_inline)) void pci_io_write_config32(device_t outl(value, 0xCFC); } -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value) { unsigned addr; - addr = MMCONF_BASE_ADDRESS | dev | where; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; write32x(addr, value); } #endif static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value) { -#if MMCONF_SUPPORT_DEFAULT +#if CONFIG_MMCONF_SUPPORT_DEFAULT pci_mmio_write_config32(dev, where, value); #else pci_io_write_config32(dev, where, value); @@ -286,7 +286,7 @@ static device_t pci_io_locate_device(unsigned pci_id, device_t dev) static device_t pci_locate_device(unsigned pci_id, device_t dev) { - for(; dev <= PCI_DEV(255|(((1<<PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) { + for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) { unsigned int id; id = pci_read_config32(dev, 0); if (id == pci_id) { diff --git a/src/arch/i386/init/car.S b/src/arch/i386/init/car.S index 94ffc648c5..98e40ad0cf 100644 --- a/src/arch/i386/init/car.S +++ b/src/arch/i386/init/car.S @@ -72,8 +72,8 @@ __protected_stage0: * the other is very similar to the AMD CAR, except remove amd specific msr */ -#define CacheSize DCACHE_RAM_SIZE -#define CacheBase DCACHE_RAM_BASE +#define CacheSize CONFIG_DCACHE_RAM_SIZE +#define CacheBase CONFIG_DCACHE_RAM_BASE #include <cpu/x86/mtrr.h> @@ -241,14 +241,14 @@ clear_fixed_var_mtrr_out: */ movl $0x202, %ecx xorl %edx, %edx - movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax wrmsr movl $0x203, %ecx movl $0x0000000f, %edx - movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr -#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ /* enable cache */ movl %cr0, %eax diff --git a/src/arch/i386/init/crt0.S.lb b/src/arch/i386/init/crt0.S.lb index cf7c2ab5e9..e60144840c 100644 --- a/src/arch/i386/init/crt0.S.lb +++ b/src/arch/i386/init/crt0.S.lb @@ -37,14 +37,14 @@ #include "crt0_includes.h" -#if USE_DCACHE_RAM == 0 +#if CONFIG_USE_DCACHE_RAM == 0 #ifndef CONSOLE_DEBUG_TX_STRING /* uses: esp, ebx, ax, dx */ # define __CRT_CONSOLE_TX_STRING(string) \ mov string, %ebx ; \ CALLSP(crt_console_tx_string) -# if defined(TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) +# if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) # define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string) # else # define CONSOLE_DEBUG_TX_STRING(string) @@ -102,26 +102,26 @@ crt_console_tx_string: RETSP 9: /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif /* Data */ -#define TTYS0_RBR (TTYS0_BASE+0x00) +#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00) /* Control */ #define TTYS0_TBR TTYS0_RBR -#define TTYS0_IER (TTYS0_BASE+0x01) -#define TTYS0_IIR (TTYS0_BASE+0x02) +#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01) +#define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02) #define TTYS0_FCR TTYS0_IIR -#define TTYS0_LCR (TTYS0_BASE+0x03) -#define TTYS0_MCR (TTYS0_BASE+0x04) +#define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03) +#define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04) #define TTYS0_DLL TTYS0_RBR #define TTYS0_DLM TTYS0_IER /* Status */ -#define TTYS0_LSR (TTYS0_BASE+0x05) -#define TTYS0_MSR (TTYS0_BASE+0x06) -#define TTYS0_SCR (TTYS0_BASE+0x07) +#define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05) +#define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06) +#define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07) mov %al, %ah 10: mov $TTYS0_LSR, %dx @@ -143,7 +143,7 @@ str_copying_to_ram: .string "Uncompressing coreboot to RAM.\r\n" str_copying_to_ram: .string "Copying coreboot to RAM.\r\n" #endif #if CONFIG_CBFS -# if USE_FALLBACK_IMAGE == 1 +# if CONFIG_USE_FALLBACK_IMAGE == 1 str_coreboot_ram_name: .string "fallback/coreboot_ram" # else str_coreboot_ram_name: .string "normal/coreboot_ram" @@ -154,4 +154,4 @@ str_pre_main: .string "Jumping to coreboot.\r\n" #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */ -#endif /* USE_DCACHE_RAM */ +#endif /* CONFIG_USE_DCACHE_RAM */ diff --git a/src/arch/i386/init/ldscript.lb b/src/arch/i386/init/ldscript.lb index 50a8c9965d..0ed5c47f53 100644 --- a/src/arch/i386/init/ldscript.lb +++ b/src/arch/i386/init/ldscript.lb @@ -1,12 +1,12 @@ /* * Memory map: * - * _RAMBASE + * CONFIG_RAMBASE * : data segment * : bss segment * : heap * : stack - * _ROMBASE + * CONFIG_ROMBASE * : coreboot text * : readonly text */ @@ -35,7 +35,7 @@ TARGET(binary) INPUT(coreboot_ram.rom) SECTIONS { - . = _ROMBASE; + . = CONFIG_ROMBASE; .ram . : { _ram = . ; @@ -56,7 +56,7 @@ SECTIONS _lrom = LOADADDR(.rom); _elrom = LOADADDR(.rom) + SIZEOF(.rom); - _iseg = _RAMBASE; + _iseg = CONFIG_RAMBASE; _eiseg = _iseg + SIZEOF(.ram); _liseg = _ram; _eliseg = _eram; diff --git a/src/arch/i386/init/ldscript_apc.lb b/src/arch/i386/init/ldscript_apc.lb index ce491547b0..2c8cb84e63 100644 --- a/src/arch/i386/init/ldscript_apc.lb +++ b/src/arch/i386/init/ldscript_apc.lb @@ -6,7 +6,7 @@ SECTIONS coreboot_apc.rom(*) _eapcrom = .; } - _iseg_apc = DCACHE_RAM_BASE; + _iseg_apc = CONFIG_DCACHE_RAM_BASE; _eiseg_apc = _iseg_apc + SIZEOF(.apcrom); _liseg_apc = _apcrom; _eliseg_apc = _eapcrom; diff --git a/src/arch/i386/init/ldscript_cbfs.lb b/src/arch/i386/init/ldscript_cbfs.lb index e86befb1ca..37e867db21 100644 --- a/src/arch/i386/init/ldscript_cbfs.lb +++ b/src/arch/i386/init/ldscript_cbfs.lb @@ -1,12 +1,12 @@ /* * Memory map: * - * _RAMBASE + * CONFIG_RAMBASE * : data segment * : bss segment * : heap * : stack - * _ROMBASE + * CONFIG_ROMBASE * : coreboot text * : readonly text */ @@ -34,7 +34,7 @@ ENTRY(_start) TARGET(binary) SECTIONS { - . = _ROMBASE; + . = CONFIG_ROMBASE; /* This section might be better named .setup */ .rom . : { diff --git a/src/arch/i386/init/ldscript_failover.lb b/src/arch/i386/init/ldscript_failover.lb index 064f159a50..099cae9d8a 100644 --- a/src/arch/i386/init/ldscript_failover.lb +++ b/src/arch/i386/init/ldscript_failover.lb @@ -1,12 +1,12 @@ /* * Memory map: * - * _RAMBASE + * CONFIG_RAMBASE * : data segment * : bss segment * : heap * : stack - * _ROMBASE + * CONFIG_ROMBASE * : coreboot text * : readonly text */ @@ -34,7 +34,7 @@ ENTRY(_start) TARGET(binary) SECTIONS { - . = _ROMBASE; + . = CONFIG_ROMBASE; /* This section might be better named .setup */ .rom . : { diff --git a/src/arch/i386/init/ldscript_fallback.lb b/src/arch/i386/init/ldscript_fallback.lb index a46c374520..6d41cbde87 100644 --- a/src/arch/i386/init/ldscript_fallback.lb +++ b/src/arch/i386/init/ldscript_fallback.lb @@ -1,12 +1,12 @@ /* * Memory map: * - * _RAMBASE + * CONFIG_RAMBASE * : data segment * : bss segment * : heap * : stack - * _ROMBASE + * CONFIG_ROMBASE * : coreboot text * : readonly text */ @@ -35,7 +35,7 @@ TARGET(binary) INPUT(coreboot_ram.rom) SECTIONS { - . = _ROMBASE; + . = CONFIG_ROMBASE; .ram . : { _ram = . ; @@ -45,7 +45,7 @@ SECTIONS /* cut _start into last 64k*/ _x = .; - . = (_x < (_ROMBASE - 0x10000 + ROM_IMAGE_SIZE)) ? (_ROMBASE - 0x10000 + ROM_IMAGE_SIZE) : _x; + . = (_x < (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE)) ? (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE) : _x; /* This section might be better named .setup */ .rom . : { @@ -61,7 +61,7 @@ SECTIONS _lrom = LOADADDR(.rom); _elrom = LOADADDR(.rom) + SIZEOF(.rom); - _iseg = _RAMBASE; + _iseg = CONFIG_RAMBASE; _eiseg = _iseg + SIZEOF(.ram); _liseg = _ram; _eliseg = _eram; diff --git a/src/arch/i386/init/ldscript_fallback_cbfs.lb b/src/arch/i386/init/ldscript_fallback_cbfs.lb index 52274d1356..eb3bf3f0d7 100644 --- a/src/arch/i386/init/ldscript_fallback_cbfs.lb +++ b/src/arch/i386/init/ldscript_fallback_cbfs.lb @@ -1,12 +1,12 @@ /* * Memory map: * - * _RAMBASE + * CONFIG_RAMBASE * : data segment * : bss segment * : heap * : stack - * _ROMBASE + * CONFIG_ROMBASE * : coreboot text * : readonly text */ @@ -34,11 +34,11 @@ ENTRY(_start) TARGET(binary) SECTIONS { - . = _ROMBASE; + . = CONFIG_ROMBASE; /* cut _start into last 64k*/ _x = .; - . = (_x < (_ROMBASE - 0x10000 + ROM_IMAGE_SIZE)) ? (_ROMBASE - 0x10000 + ROM_IMAGE_SIZE) : _x; + . = (_x < (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE)) ? (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE) : _x; /* This section might be better named .setup */ .rom . : { diff --git a/src/arch/i386/lib/Config.lb b/src/arch/i386/lib/Config.lb index 52da9d5e59..0a07e3b9be 100644 --- a/src/arch/i386/lib/Config.lb +++ b/src/arch/i386/lib/Config.lb @@ -1,6 +1,6 @@ uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses USE_FAILOVER_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE uses CONFIG_CBFS object c_start.S @@ -13,7 +13,7 @@ object exception.c initobject printk_init.o -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_CBFS initobject cbfs_and_run.o diff --git a/src/arch/i386/lib/console_printk.c b/src/arch/i386/lib/console_printk.c index f4b35a192c..a3c409c5c1 100644 --- a/src/arch/i386/lib/console_printk.c +++ b/src/arch/i386/lib/console_printk.c @@ -11,39 +11,39 @@ extern int do_printk(int msg_level, const char *fmt, ...); #define printk_debug(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg) #define printk_spew(fmt, arg...) do_printk(BIOS_SPEW ,fmt, ##arg) -#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_EMERG +#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_EMERG #undef printk_emerg #define printk_emerg(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg) #endif -#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ALERT +#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ALERT #undef printk_alert #define printk_alert(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg) #endif -#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_CRIT +#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_CRIT #undef printk_crit #define printk_crit(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg) #endif -#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ERR +#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ERR #undef printk_err #define printk_err(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg) #endif -#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_WARNING +#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_WARNING #undef printk_warning #define printk_warning(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg) #endif -#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_NOTICE +#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_NOTICE #undef printk_notice #define printk_notice(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg) #endif -#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_INFO +#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_INFO #undef printk_info #define printk_info(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg) #endif -#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_DEBUG +#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_DEBUG #undef printk_debug #define printk_debug(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg) #endif -#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_SPEW +#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_SPEW #undef printk_spew #define printk_spew(fmt, arg...) do_printk(BIOS_EMERG , "", ##arg) #endif diff --git a/src/arch/i386/lib/failover_failover.lds b/src/arch/i386/lib/failover_failover.lds index 814f2000fb..ec8c12a9e4 100644 --- a/src/arch/i386/lib/failover_failover.lds +++ b/src/arch/i386/lib/failover_failover.lds @@ -1,2 +1,2 @@ __fallback_image = (CONFIG_ROM_PAYLOAD_START & 0xfffffff0) - 8; - __normal_image = ((CONFIG_ROM_PAYLOAD_START - FALLBACK_SIZE) & 0xfffffff0) - 8; + __normal_image = ((CONFIG_ROM_PAYLOAD_START - CONFIG_FALLBACK_SIZE) & 0xfffffff0) - 8; diff --git a/src/arch/i386/lib/id.inc b/src/arch/i386/lib/id.inc index 46b4424511..c2f634ea00 100644 --- a/src/arch/i386/lib/id.inc +++ b/src/arch/i386/lib/id.inc @@ -3,12 +3,12 @@ .globl __id_start __id_start: vendor: - .asciz MAINBOARD_VENDOR + .asciz CONFIG_MAINBOARD_VENDOR part: - .asciz MAINBOARD_PART_NUMBER + .asciz CONFIG_MAINBOARD_PART_NUMBER .long __id_end + 0x10 - vendor /* Reverse offset to the vendor id */ .long __id_end + 0x10 - part /* Reverse offset to the part number */ -.long PAYLOAD_SIZE + ROM_IMAGE_SIZE /* Size of this romimage */ +.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE /* Size of this romimage */ .globl __id_end __id_end: diff --git a/src/arch/i386/lib/id.lds b/src/arch/i386/lib/id.lds index ccdf7008f7..8f9149a6a1 100644 --- a/src/arch/i386/lib/id.lds +++ b/src/arch/i386/lib/id.lds @@ -1,5 +1,5 @@ SECTIONS { - . = (_ROMBASE + ROM_IMAGE_SIZE - 0x10) - (__id_end - __id_start); + . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__id_end - __id_start); .id (.): { *(.id) } diff --git a/src/arch/i386/lib/pci_ops_conf1.c b/src/arch/i386/lib/pci_ops_conf1.c index 4c4cd672e6..36db54c21b 100644 --- a/src/arch/i386/lib/pci_ops_conf1.c +++ b/src/arch/i386/lib/pci_ops_conf1.c @@ -8,7 +8,7 @@ * Functions for accessing PCI configuration space with type 1 accesses */ -#if PCI_IO_CFG_EXT == 0 +#if CONFIG_PCI_IO_CFG_EXT == 0 #define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3)) #else #define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | ((where & 0xff) & ~3) | ((where & 0xf00)<<16) ) diff --git a/src/arch/i386/lib/pci_ops_mmconf.c b/src/arch/i386/lib/pci_ops_mmconf.c index c037a7b4cd..a6057084f0 100644 --- a/src/arch/i386/lib/pci_ops_mmconf.c +++ b/src/arch/i386/lib/pci_ops_mmconf.c @@ -1,4 +1,4 @@ -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT #include <console/console.h> #include <arch/io.h> @@ -13,7 +13,7 @@ */ #define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE) ( \ - MMCONF_BASE_ADDRESS | \ + CONFIG_MMCONF_BASE_ADDRESS | \ (((SEGBUS) & 0xFFF) << 20) | \ (((DEVFN) & 0xFF) << 12) | \ ((WHERE) & 0xFFF)) diff --git a/src/arch/i386/lib/printk_init.c b/src/arch/i386/lib/printk_init.c index 7c03664a4f..4b26930580 100644 --- a/src/arch/i386/lib/printk_init.c +++ b/src/arch/i386/lib/printk_init.c @@ -14,7 +14,7 @@ /* Keep together for sysctl support */ /* Using an global varible can cause problem when we reset the stack from cache as ram to ram*/ #if 0 -int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; +int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; #else #define console_loglevel ASM_CONSOLE_LOGLEVEL #endif @@ -25,8 +25,8 @@ extern void uart8250_tx_byte(unsigned, unsigned char); void console_tx_byte(unsigned char byte) { if (byte == '\n') - uart8250_tx_byte(TTYS0_BASE, '\r'); - uart8250_tx_byte(TTYS0_BASE, byte); + uart8250_tx_byte(CONFIG_TTYS0_BASE, '\r'); + uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); } int do_printk(int msg_level, const char *fmt, ...) diff --git a/src/arch/i386/smp/Config.lb b/src/arch/i386/smp/Config.lb index b41f5c295e..18aa70ac86 100644 --- a/src/arch/i386/smp/Config.lb +++ b/src/arch/i386/smp/Config.lb @@ -1,6 +1,6 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE -if HAVE_MP_TABLE +if CONFIG_HAVE_MP_TABLE object mpspec.o end #object ioapic.o CONFIG_IOAPIC diff --git a/src/arch/ppc/boot/coreboot_table.c b/src/arch/ppc/boot/coreboot_table.c index b1420a7491..dc154b2a71 100644 --- a/src/arch/ppc/boot/coreboot_table.c +++ b/src/arch/ppc/boot/coreboot_table.c @@ -340,7 +340,7 @@ unsigned long write_coreboot_table( head = lb_table_init(low_table_end); low_table_end = (unsigned long)head; - if (HAVE_OPTION_TABLE == 1) { + if (CONFIG_HAVE_OPTION_TABLE == 1) { struct lb_record *rec_dest, *rec_src; /* Write the option config table... */ rec_dest = lb_new_record(head); diff --git a/src/arch/ppc/include/arch/cpu.h b/src/arch/ppc/include/arch/cpu.h index e0ed4ff66a..3026486420 100644 --- a/src/arch/ppc/include/arch/cpu.h +++ b/src/arch/ppc/include/arch/cpu.h @@ -13,24 +13,24 @@ struct cpu_driver { struct cpu_device_id *id_table; }; -#ifndef STACK_SIZE -#error STACK_SIZE not defined +#ifndef CONFIG_STACK_SIZE +#error CONFIG_STACK_SIZE not defined #endif /* The basic logic comes from the Linux kernel. - * The invariant is that (1 << 31 - STACK_BITS) == STACK_SIZE + * The invariant is that (1 << 31 - STACK_BITS) == CONFIG_STACK_SIZE * I wish there was simpler way to support multiple stack sizes. * Oh well. */ -#if STACK_SIZE == 4096 +#if CONFIG_STACK_SIZE == 4096 #define STACK_BITS "19" -#elif STACK_SIZE == 8192 +#elif CONFIG_STACK_SIZE == 8192 #define STACK_BITS "18" -#elif STACK_SIZE == 16384 +#elif CONFIG_STACK_SIZE == 16384 #define STACK_BITS "17" -#elif STACK_SIZE == 32768 +#elif CONFIG_STACK_SIZE == 32768 #define STACK_BITS "16" -#elif STACK_SIZE == 65536 +#elif CONFIG_STACK_SIZE == 65536 #define STACK_BITS "15" #else #error Unimplemented stack size diff --git a/src/arch/ppc/include/arch/io.h b/src/arch/ppc/include/arch/io.h index fd0d1e4654..ba8ce4fa85 100644 --- a/src/arch/ppc/include/arch/io.h +++ b/src/arch/ppc/include/arch/io.h @@ -11,8 +11,8 @@ #define SLOW_DOWN_IO -#ifndef _IO_BASE -#define _IO_BASE 0 +#ifndef CONFIG_IO_BASE +#define CONFIG_IO_BASE 0 #endif #define readb(addr) in_8((volatile uint8_t *)(addr)) @@ -36,15 +36,15 @@ * are arrays of bytes, and byte-swapping is not appropriate in * that case. - paulus */ -#define insw(port, buf, ns) _insw_ns((uint16_t *)((port)+_IO_BASE), (buf), (ns)) -#define outsw(port, buf, ns) _outsw_ns((uint16_t *)((port)+_IO_BASE), (buf), (ns)) +#define insw(port, buf, ns) _insw_ns((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns)) +#define outsw(port, buf, ns) _outsw_ns((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns)) -#define inb(port) in_8((uint8_t *)((port)+_IO_BASE)) -#define outb(val, port) out_8((uint8_t *)((port)+_IO_BASE), (val)) -#define inw(port) in_le16((uint16_t *)((port)+_IO_BASE)) -#define outw(val, port) out_le16((uint16_t *)((port)+_IO_BASE), (val)) -#define inl(port) in_le32((uint32_t *)((port)+_IO_BASE)) -#define outl(val, port) out_le32((uint32_t *)((port)+_IO_BASE), (val)) +#define inb(port) in_8((uint8_t *)((port)+CONFIG_IO_BASE)) +#define outb(val, port) out_8((uint8_t *)((port)+CONFIG_IO_BASE), (val)) +#define inw(port) in_le16((uint16_t *)((port)+CONFIG_IO_BASE)) +#define outw(val, port) out_le16((uint16_t *)((port)+CONFIG_IO_BASE), (val)) +#define inl(port) in_le32((uint32_t *)((port)+CONFIG_IO_BASE)) +#define outl(val, port) out_le32((uint32_t *)((port)+CONFIG_IO_BASE), (val)) #define inb_p(port) inb((port)) #define outb_p(val, port) outb((val), (port)) @@ -56,8 +56,8 @@ /* * The *_ns versions below do byte-swapping. */ -#define insw_ns(port, buf, ns) _insw((uint16_t *)((port)+_IO_BASE), (buf), (ns)) -#define outsw_ns(port, buf, ns) _outsw((uint16_t *)((port)+_IO_BASE), (buf), (ns)) +#define insw_ns(port, buf, ns) _insw((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns)) +#define outsw_ns(port, buf, ns) _outsw((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns)) #define IO_SPACE_LIMIT ~0 diff --git a/src/arch/ppc/include/arch/pirq_routing.h b/src/arch/ppc/include/arch/pirq_routing.h index dad8531eb5..00c9556319 100644 --- a/src/arch/ppc/include/arch/pirq_routing.h +++ b/src/arch/ppc/include/arch/pirq_routing.h @@ -16,8 +16,8 @@ struct irq_info { u8 rfu; } __attribute__((packed)); -#if defined(IRQ_SLOT_COUNT) -#define IRQ_SLOTS_COUNT IRQ_SLOT_COUNT +#if defined(CONFIG_IRQ_SLOT_COUNT) +#define IRQ_SLOTS_COUNT CONFIG_IRQ_SLOT_COUNT #elif (__GNUC__ < 3) #define IRQ_SLOTS_COUNT 1 #else @@ -39,13 +39,13 @@ struct irq_routing_table { extern const struct irq_routing_table intel_irq_routing_table; -#if defined(DEBUG) && defined(HAVE_PIRQ_TABLE) +#if defined(CONFIG_DEBUG) && defined(CONFIG_HAVE_PIRQ_TABLE) void check_pirq_routing_table(void); #else #define check_pirq_routing_table() do {} while(0) #endif -#if defined(HAVE_PIRQ_TABLE) +#if defined(CONFIG_HAVE_PIRQ_TABLE) unsigned long copy_pirq_routing_table(unsigned long start); #else #define copy_pirq_routing_table(start) (start) diff --git a/src/arch/ppc/init/crt0.S.lb b/src/arch/ppc/init/crt0.S.lb index 738d4b4a67..bbccc59213 100644 --- a/src/arch/ppc/init/crt0.S.lb +++ b/src/arch/ppc/init/crt0.S.lb @@ -30,8 +30,8 @@ system_reset: */ %%PROCESSOR_INIT%% -#if USE_DCACHE_RAM == 1 -#define DCACHE_RAM_END (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - 1) +#if CONFIG_USE_DCACHE_RAM == 1 +#define DCACHE_RAM_END (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 1) /* * Initialize data cache blocks * (assumes cache block size of 32 bytes) @@ -39,9 +39,9 @@ system_reset: * NOTE: This may need to be moved to FAMILY_INIT if * dcbz is not supported on all CPU's */ - lis r1, DCACHE_RAM_BASE@h - ori r1, r1, DCACHE_RAM_BASE@l - li r3, (DCACHE_RAM_SIZE / 32) + lis r1, CONFIG_DCACHE_RAM_BASE@h + ori r1, r1, CONFIG_DCACHE_RAM_BASE@l + li r3, (CONFIG_DCACHE_RAM_SIZE / 32) mtctr r3 0: dcbz r0, r1 addi r1, r1, 32 @@ -53,8 +53,8 @@ system_reset: * it 16-byte aligned to cover both cases. Also we have to ensure that * the first word is located within the cache. */ - lis r1, (DCACHE_RAM_BASE+DCACHE_RAM_SIZE)@h - ori r1, r1, (DCACHE_RAM_BASE+DCACHE_RAM_SIZE)@l + lis r1, (CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE)@h + ori r1, r1, (CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE)@l lis r0, 0 stwu r0, -4(r1) stwu r0, -4(r1) @@ -65,8 +65,8 @@ system_reset: /* * Clear stack */ - lis r4, DCACHE_RAM_BASE@h - ori r4, r4, DCACHE_RAM_BASE@l + lis r4, CONFIG_DCACHE_RAM_BASE@h + ori r4, r4, CONFIG_DCACHE_RAM_BASE@l lis r7, DCACHE_RAM_END@h ori r7, r7, DCACHE_RAM_END@l lis r5, 0 @@ -110,7 +110,7 @@ system_reset: * Complete rest of initialization in C (ppc_main) */ rfi -#endif /* USE_DCACHE_RAM */ +#endif /* CONFIG_USE_DCACHE_RAM */ /* * Stop here if something goes wrong diff --git a/src/arch/ppc/init/ldscript.lb b/src/arch/ppc/init/ldscript.lb index a81d9b9bb8..453c99c13b 100644 --- a/src/arch/ppc/init/ldscript.lb +++ b/src/arch/ppc/init/ldscript.lb @@ -1,14 +1,14 @@ /* * Memory map: * - * _ROMBASE : start of ROM - * _RESET : reset vector (may be at top of ROM) + * CONFIG_ROMBASE : start of ROM + * CONFIG_RESET : reset vector (may be at top of ROM) * _EXCEPTIONS_VECTORS : exception table * - * _ROMSTART : coreboot text + * CONFIG_ROMSTART : coreboot text * : payload text * - * _RAMBASE : address to copy payload + * CONFIG_RAMBASE : address to copy payload */ /* @@ -32,13 +32,13 @@ SECTIONS /* * Absolute location of base of ROM */ - . = _ROMBASE; + . = CONFIG_ROMBASE; /* * Absolute location of reset vector. This may actually be at the * the top of ROM. */ - . = _RESET; + . = CONFIG_RESET; .reset . : { *(.rom.reset); . = ALIGN(16); @@ -47,7 +47,7 @@ SECTIONS /* * Absolute location of exception vector table. */ - . = _EXCEPTION_VECTORS; + . = CONFIG_EXCEPTION_VECTORS; .exception_vectors . : { *(.rom.exception_vectors); . = ALIGN(16); @@ -56,7 +56,7 @@ SECTIONS /* * Absolute location of coreboot initialization code in ROM. */ - . = _ROMSTART; + . = CONFIG_ROMSTART; .rom . : { _rom = .; *(.rom.text); @@ -94,7 +94,7 @@ SECTIONS /* * Absolute location of where coreboot will be relocated in RAM. */ - _iseg = _RAMBASE; + _iseg = CONFIG_RAMBASE; _eiseg = _iseg + SIZEOF(.ram); _liseg = _ram; _eliseg = _eram; diff --git a/src/arch/ppc/lib/pci_dev.c b/src/arch/ppc/lib/pci_dev.c index adb047e3fe..d821f17c77 100644 --- a/src/arch/ppc/lib/pci_dev.c +++ b/src/arch/ppc/lib/pci_dev.c @@ -9,8 +9,8 @@ uint8_t pci_ppc_read_config8(unsigned char bus, int devfn, int where) { uint8_t res; - out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where)); - res = in_8((unsigned char *)PCIC0_CFGDATA + (where & 3)); + out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where)); + res = in_8((unsigned char *)CONFIG_PCIC0_CFGDATA + (where & 3)); return res; } @@ -18,8 +18,8 @@ uint16_t pci_ppc_read_config16(unsigned char bus, int devfn, int where) { uint16_t res; - out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where)); - res = in_le16((unsigned short *)PCIC0_CFGDATA + (where & 2)); + out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where)); + res = in_le16((unsigned short *)CONFIG_PCIC0_CFGDATA + (where & 2)); return res; } @@ -27,28 +27,28 @@ uint32_t pci_ppc_read_config32(unsigned char bus, int devfn, int where) { uint32_t res; - out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where)); - res = in_le32((unsigned *)PCIC0_CFGDATA); + out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where)); + res = in_le32((unsigned *)CONFIG_PCIC0_CFGDATA); return res; } int pci_ppc_write_config8(unsigned char bus, int devfn, int where, uint8_t data) { - out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where)); - out_8((unsigned char *)PCIC0_CFGDATA + (where & 3), data); + out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where)); + out_8((unsigned char *)CONFIG_PCIC0_CFGDATA + (where & 3), data); return 0; } int pci_ppc_write_config16(unsigned char bus, int devfn, int where, uint16_t data) { - out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where)); - out_le16((unsigned short *)PCIC0_CFGDATA + (where & 2), data); + out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where)); + out_le16((unsigned short *)CONFIG_PCIC0_CFGDATA + (where & 2), data); return 0; } int pci_ppc_write_config32(unsigned char bus, int devfn, int where, uint32_t data) { - out_le32((unsigned *)PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where)); - out_le32((unsigned *)PCIC0_CFGDATA, data); + out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where)); + out_le32((unsigned *)CONFIG_PCIC0_CFGDATA, data); return 0; } diff --git a/src/arch/ppc/lib/printk_init.c b/src/arch/ppc/lib/printk_init.c index 401d271391..98d78b3fc4 100644 --- a/src/arch/ppc/lib/printk_init.c +++ b/src/arch/ppc/lib/printk_init.c @@ -12,7 +12,7 @@ /* Keep together for sysctl support */ -int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; +int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; extern int vtxprintf(void (*)(unsigned char), const char *, va_list); extern void uart8250_tx_byte(unsigned, unsigned char); @@ -20,8 +20,8 @@ extern void uart8250_tx_byte(unsigned, unsigned char); void console_tx_byte(unsigned char byte) { if (byte == '\n') - uart8250_tx_byte(TTYS0_BASE, '\r'); - uart8250_tx_byte(TTYS0_BASE, byte); + uart8250_tx_byte(CONFIG_TTYS0_BASE, '\r'); + uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); } int do_printk(int msg_level, const char *fmt, ...) diff --git a/src/boot/filo.c b/src/boot/filo.c index cd14fa13b3..d6ee9305e9 100644 --- a/src/boot/filo.c +++ b/src/boot/filo.c @@ -14,11 +14,11 @@ #define ENTER '\r' #define ESCAPE '\x1b' -#ifndef AUTOBOOT_CMDLINE +#ifndef CONFIG_AUTOBOOT_CMDLINE #define autoboot(mem) #endif -#if !AUTOBOOT_DELAY +#if !CONFIG_AUTOBOOT_DELAY #define autoboot_delay() 0 /* success */ #endif @@ -115,8 +115,8 @@ static void boot(struct lb_memory *mem, const char *line) free(boot_file); } -#ifdef AUTOBOOT_CMDLINE -#if AUTOBOOT_DELAY +#ifdef CONFIG_AUTOBOOT_CMDLINE +#if CONFIG_AUTOBOOT_DELAY static inline int autoboot_delay(void) { unsigned int timeout; @@ -126,7 +126,7 @@ static inline int autoboot_delay(void) key = 0; printk_info("Press <Enter> for default boot, or <Esc> for boot prompt... "); - for (sec = AUTOBOOT_DELAY; sec>0 && key==0; sec--) { + for (sec = CONFIG_AUTOBOOT_DELAY; sec>0 && key==0; sec--) { printk_info("%d", sec); timeout = 10; while (timeout-- > 0) { @@ -151,7 +151,7 @@ static inline int autoboot_delay(void) return 0; /* default accepted */ } } -#endif /* AUTOBOOT_DELAY */ +#endif /* CONFIG_AUTOBOOT_DELAY */ static void autoboot(struct lb_memory *mem) { @@ -160,11 +160,11 @@ static void autoboot(struct lb_memory *mem) return; if (autoboot_delay()==0) { - printk_info("boot: %s\n", AUTOBOOT_CMDLINE); - boot(mem, AUTOBOOT_CMDLINE); + printk_info("boot: %s\n", CONFIG_AUTOBOOT_CMDLINE); + boot(mem, CONFIG_AUTOBOOT_CMDLINE); } } -#endif /* AUTOBOOT_CMDLINE */ +#endif /* CONFIG_AUTOBOOT_CMDLINE */ /* The main routine */ int filo(struct lb_memory *mem) @@ -179,8 +179,8 @@ int filo(struct lb_memory *mem) /* The above didn't work, ask user */ while (havechar()) getchar(); -#ifdef AUTOBOOT_CMDLINE - strncpy(line, AUTOBOOT_CMDLINE, sizeof(line)-1); +#ifdef CONFIG_AUTOBOOT_CMDLINE + strncpy(line, CONFIG_AUTOBOOT_CMDLINE, sizeof(line)-1); line[sizeof(line)-1] = '\0'; #else line[0] = '\0'; diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index 2419dc2134..058be24ebc 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -37,7 +37,7 @@ it with the version available from LANL. #include <boot/tables.h> #include <boot/elf.h> #include <cbfs.h> -#if HAVE_ACPI_RESUME +#if CONFIG_HAVE_ACPI_RESUME #include <arch/acpi.h> #endif @@ -88,7 +88,7 @@ void hardwaremain(int boot_complete) dev_initialize(); post_code(0x89); -#if HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME == 1 suspend_resume(); post_code(0x8a); #endif @@ -98,7 +98,7 @@ void hardwaremain(int boot_complete) */ lb_mem = write_tables(); #if CONFIG_CBFS == 1 -# if USE_FALLBACK_IMAGE == 1 +# if CONFIG_USE_FALLBACK_IMAGE == 1 cbfs_load_payload(lb_mem, "fallback/payload"); # else cbfs_load_payload(lb_mem, "normal/payload"); diff --git a/src/config/Config.lb b/src/config/Config.lb index 2a30a91ef9..5ca864db3f 100644 --- a/src/config/Config.lb +++ b/src/config/Config.lb @@ -1,18 +1,18 @@ ## This is Architecture independant part of the makefile -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_AP_CODE_IN_CAR -uses ASSEMBLER_DEBUG +uses CONFIG_ASSEMBLER_DEBUG makedefine CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name) makedefine GCC ?= $(CC) makedefine GCC_INC_DIR := $(shell LC_ALL=C $(GCC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp") -makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS) -makedefine CFLAGS := $(CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc -nostdlib -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer +makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(CONFIG_ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS) +makedefine CFLAGS := $(CONFIG_CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc -nostdlib -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -if ASSEMBLER_DEBUG +if CONFIG_ASSEMBLER_DEBUG makedefine DEBUG_CFLAGS := -g -dA -fverbose-asm end @@ -35,25 +35,25 @@ end makerule coreboot.strip depends "coreboot" - action "$(OBJCOPY) -O binary coreboot coreboot.strip" + action "$(CONFIG_OBJCOPY) -O binary coreboot coreboot.strip" end makerule coreboot.a depends "$(OBJECTS)" action "rm -f coreboot.a" - action "$(CROSS_COMPILE)ar cr coreboot.a $(OBJECTS)" + action "$(CONFIG_CROSS_COMPILE)ar cr coreboot.a $(OBJECTS)" end makerule coreboot_ram.o - depends "src/arch/$(ARCH)/lib/c_start.o $(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)" - action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ src/arch/$(ARCH)/lib/c_start.o $(DRIVER) -Wl,-\( coreboot.a $(LIBGCC_FILE_NAME) -Wl,-\)" + depends "src/arch/$(CONFIG_ARCH)/lib/c_start.o $(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)" + action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ src/arch/$(CONFIG_ARCH)/lib/c_start.o $(DRIVER) -Wl,-\( coreboot.a $(LIBGCC_FILE_NAME) -Wl,-\)" end makerule coreboot_ram depends "coreboot_ram.o $(TOP)/src/config/coreboot_ram.ld ldoptions" action "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/coreboot_ram.ld coreboot_ram.o" - action "$(CROSS_COMPILE)nm -n coreboot_ram | sort > coreboot_ram.map" + action "$(CONFIG_CROSS_COMPILE)nm -n coreboot_ram | sort > coreboot_ram.map" end ## @@ -64,7 +64,7 @@ makedefine COREBOOT_RAM-$(CONFIG_UNCOMPRESSED):=coreboot_ram.bin makerule coreboot_ram.bin depends "coreboot_ram" - action "$(OBJCOPY) -O binary $< $@" + action "$(CONFIG_OBJCOPY) -O binary $< $@" end makerule coreboot_ram.nrv2b @@ -85,18 +85,18 @@ if CONFIG_AP_CODE_IN_CAR makerule coreboot_apc.a depends "apc_auto.o" action "rm -f coreboot_apc.a" - action "$(CROSS_COMPILE)ar cr coreboot_apc.a apc_auto.o" + action "$(CONFIG_CROSS_COMPILE)ar cr coreboot_apc.a apc_auto.o" end makerule coreboot_apc.o - depends "src/arch/$(ARCH)/lib/c_start.o coreboot_apc.a $(LIBGCC_FILE_NAME)" + depends "src/arch/$(CONFIG_ARCH)/lib/c_start.o coreboot_apc.a $(LIBGCC_FILE_NAME)" action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ $^" end makerule coreboot_apc depends "coreboot_apc.o $(TOP)/src/config/coreboot_apc.ld ldoptions" action "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/coreboot_apc.ld coreboot_apc.o" - action "$(CROSS_COMPILE)nm -n coreboot_apc | sort > coreboot_apc.map" + action "$(CONFIG_CROSS_COMPILE)nm -n coreboot_apc | sort > coreboot_apc.map" end ## @@ -107,7 +107,7 @@ if CONFIG_AP_CODE_IN_CAR makerule coreboot_apc.bin depends "coreboot_apc" - action "$(OBJCOPY) -O binary $< $@" + action "$(CONFIG_OBJCOPY) -O binary $< $@" end makerule coreboot_apc.nrv2b @@ -129,14 +129,14 @@ makedefine COREBOOT_RAM_ROM:=coreboot_ram.rom makerule coreboot depends "crt0.o $(INIT-OBJECTS) $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld" action "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o $(INIT-OBJECTS)" - action "$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map" - action "$(CROSS_COMPILE)objdump -dS coreboot > coreboot.disasm" + action "$(CONFIG_CROSS_COMPILE)nm -n coreboot | sort > coreboot.map" + action "$(CONFIG_CROSS_COMPILE)objdump -dS coreboot > coreboot.disasm" end # the buildrom tool makerule buildrom depends "$(TOP)/util/buildrom/buildrom.c" - action "$(HOSTCC) -o $@ $<" + action "$(CONFIG_HOSTCC) -o $@ $<" end # Force crt0.s (which has build time version code in it to rebuild every time) @@ -149,7 +149,7 @@ end # generate an assembly listing via -a switch. makerule crt0.o depends "crt0.s" - action "$(CC) -Wa,-acdlns -c $(CPU_OPT) -o $@ $< >crt0.disasm" + action "$(CC) -Wa,-acdlns -c $(CONFIG_CPU_OPT) -o $@ $< >crt0.disasm" end makerule etags @@ -178,21 +178,21 @@ end # be in a correct and valid state if it exists because the move is atomic. makerule ../romcc depends "$(TOP)/util/romcc/romcc.c" - action "$(HOSTCC) -g $(HOSTCFLAGS) $< -o romcc.tmpfile" + action "$(CONFIG_HOSTCC) -g $(HOSTCFLAGS) $< -o romcc.tmpfile" action "mv romcc.tmpfile $@" end makerule build_opt_tbl depends "$(TOP)/util/options/build_opt_tbl.c $(TOP)/src/include/pc80/mc146818rtc.h $(TOP)/src/include/boot/coreboot_tables.h Makefile.settings Makefile" - action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) $< -o $@" + action "$(CONFIG_HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) $< -o $@" end makerule option_table.h option_table.c - depends "build_opt_tbl $(MAINBOARD)/cmos.layout" - action "./build_opt_tbl --config $(MAINBOARD)/cmos.layout --header option_table.h --option option_table.c" + depends "build_opt_tbl $(CONFIG_MAINBOARD)/cmos.layout" + action "./build_opt_tbl --config $(CONFIG_MAINBOARD)/cmos.layout --header option_table.h --option option_table.c" end -if HAVE_OPTION_TABLE +if CONFIG_HAVE_OPTION_TABLE object ./option_table.o end diff --git a/src/config/Options.lb b/src/config/Options.lb index a6524ede03..428e657a9d 100644 --- a/src/config/Options.lb +++ b/src/config/Options.lb @@ -61,12 +61,12 @@ define CONFIG_ARCH_X86 export always comment "X86 is the default" end -define ARCH +define CONFIG_ARCH default "i386" export always comment "Default architecture is i386, options are alpha and ppc" end -define HAVE_MOVNTI +define CONFIG_HAVE_MOVNTI default 0 export always comment "This cpu supports the MOVNTI directive" @@ -76,28 +76,28 @@ end # Build options ############################################### -define CROSS_COMPILE +define CONFIG_CROSS_COMPILE default "" export always comment "Cross compiler prefix" end define CC - default "$(CROSS_COMPILE)gcc" + default "$(CONFIG_CROSS_COMPILE)gcc" export always comment "Target C Compiler" end -define HOSTCC +define CONFIG_HOSTCC default "gcc" export always comment "Host C Compiler" end -define CPU_OPT +define CONFIG_CPU_OPT default none export used comment "Additional per-cpu CFLAGS" end -define OBJCOPY - default "$(CROSS_COMPILE)objcopy --gap-fill 0xff" +define CONFIG_OBJCOPY + default "$(CONFIG_CROSS_COMPILE)objcopy --gap-fill 0xff" export always comment "Objcopy command" end @@ -186,143 +186,143 @@ end # ROM image options ############################################### -define HAVE_FALLBACK_BOOT +define CONFIG_HAVE_FALLBACK_BOOT format "%d" default 0 export always comment "Set if fallback booting required" end -define HAVE_FAILOVER_BOOT +define CONFIG_HAVE_FAILOVER_BOOT format "%d" default 0 export always comment "Set if failover booting required" end -define USE_FALLBACK_IMAGE +define CONFIG_USE_FALLBACK_IMAGE format "%d" default 0 export used comment "Set to build a fallback image" end -define USE_FAILOVER_IMAGE +define CONFIG_USE_FAILOVER_IMAGE format "%d" default 0 export used comment "Set to build a failover image" end -define FALLBACK_SIZE +define CONFIG_FALLBACK_SIZE default 65536 format "0x%x" export used comment "Default fallback image size" end -define FAILOVER_SIZE +define CONFIG_FAILOVER_SIZE default 0 format "0x%x" export used comment "Default failover image size" end -define ROM_SIZE +define CONFIG_ROM_SIZE default none format "0x%x" export used comment "Size of your ROM" end -define ROM_IMAGE_SIZE +define CONFIG_ROM_IMAGE_SIZE default 65535 format "0x%x" export always comment "Default image size" end -define ROM_SECTION_SIZE - default {FALLBACK_SIZE} +define CONFIG_ROM_SECTION_SIZE + default {CONFIG_FALLBACK_SIZE} format "0x%x" export used comment "Default rom section size" end -define ROM_SECTION_OFFSET - default {ROM_SIZE - FALLBACK_SIZE} +define CONFIG_ROM_SECTION_OFFSET + default {CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE} format "0x%x" export used comment "Default rom section offset" end -define PAYLOAD_SIZE - default {ROM_SECTION_SIZE - ROM_IMAGE_SIZE} +define CONFIG_PAYLOAD_SIZE + default {CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE} format "0x%x" export always comment "Default payload size" end -define _ROMBASE - default {PAYLOAD_SIZE} +define CONFIG_ROMBASE + default {CONFIG_PAYLOAD_SIZE} format "0x%x" export always comment "Base address of coreboot in ROM" end -define _ROMSTART +define CONFIG_ROMSTART default none format "0x%x" export used comment "Start address of coreboot in ROM" end -define _RESET - default {_ROMBASE} +define CONFIG_RESET + default {CONFIG_ROMBASE} format "0x%x" export always comment "Hardware reset vector address" end -define _EXCEPTION_VECTORS - default {_ROMBASE+0x100} +define CONFIG_EXCEPTION_VECTORS + default {CONFIG_ROMBASE+0x100} format "0x%x" export always comment "Address of exception vector table" end -define STACK_SIZE +define CONFIG_STACK_SIZE default 0x2000 format "0x%x" export always comment "Default stack size" end -define HEAP_SIZE +define CONFIG_HEAP_SIZE default 0x2000 format "0x%x" export always comment "Default heap size" end -define _RAMBASE +define CONFIG_RAMBASE default none format "0x%x" export always comment "Base address of coreboot in RAM" end -define _RAMSTART +define CONFIG_RAMSTART default none format "0x%x" export used comment "Start address of coreboot in RAM" end -define USE_DCACHE_RAM +define CONFIG_USE_DCACHE_RAM default 0 export always comment "Use data cache as temporary RAM if possible" end -define CAR_FAM10 +define CONFIG_CAR_FAM10 default 0 export always comment "AMD family 10 CAR requires additional setup" end -define DCACHE_RAM_BASE +define CONFIG_DCACHE_RAM_BASE default 0xc0000 format "0x%x" export always comment "Base address of data cache when using it for temporary RAM" end -define DCACHE_RAM_SIZE +define CONFIG_DCACHE_RAM_SIZE default 0x1000 format "0x%x" export always comment "Size of data cache when using it for temporary RAM" end -define DCACHE_RAM_GLOBAL_VAR_SIZE +define CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE default 0 format "0x%x" export always @@ -333,23 +333,23 @@ define CONFIG_AP_CODE_IN_CAR export always comment "will copy coreboot_apc to AP cache ane execute in AP" end -define MEM_TRAIN_SEQ +define CONFIG_MEM_TRAIN_SEQ default 0 export always comment "0: three for in bsp, 1: on every core0, 2: one for on bsp" end -define WAIT_BEFORE_CPUS_INIT +define CONFIG_WAIT_BEFORE_CPUS_INIT default 0 export always comment "execute cpus_ready_for_init if it is set to 1" end -define XIP_ROM_BASE +define CONFIG_XIP_ROM_BASE default 0 format "0x%x" export used comment "Start address of area to cache during coreboot execution directly from ROM" end -define XIP_ROM_SIZE +define CONFIG_XIP_ROM_SIZE default 0 format "0x%x" export used @@ -372,14 +372,14 @@ define CONFIG_LB_MEM_TOPK export always comment "Kilobytes of memory to initialized before executing code from RAM" end -define HAVE_OPTION_TABLE +define CONFIG_HAVE_OPTION_TABLE default 0 export always comment "Export CMOS option table" end -define USE_OPTION_TABLE +define CONFIG_USE_OPTION_TABLE format "%d" - default {HAVE_OPTION_TABLE && !USE_FALLBACK_IMAGE} + default {CONFIG_HAVE_OPTION_TABLE && !CONFIG_USE_FALLBACK_IMAGE} export always comment "Use option table" end @@ -387,19 +387,19 @@ end ############################################### # CMOS variable options ############################################### -define LB_CKS_RANGE_START +define CONFIG_LB_CKS_RANGE_START default 49 format "%d" export always comment "First CMOS byte to use for coreboot options" end -define LB_CKS_RANGE_END +define CONFIG_LB_CKS_RANGE_END default 125 format "%d" export always comment "Last CMOS byte to use for coreboot options" end -define LB_CKS_LOC +define CONFIG_LB_CKS_LOC default 126 format "%d" export always @@ -411,8 +411,8 @@ end # Build targets ############################################### -define CRT0 - default "$(TOP)/src/arch/$(ARCH)/init/crt0.S.lb" +define CONFIG_CRT0 + default "$(TOP)/src/arch/$(CONFIG_ARCH)/init/crt0.S.lb" export always comment "Main initialization target" end @@ -421,7 +421,7 @@ end # Debugging/Logging options ############################################### -define DEBUG +define CONFIG_DEBUG default 0 export always comment "Enable x86emu debugging code" @@ -466,12 +466,12 @@ define CONFIG_USBDEBUG_DIRECT export always comment "Log messages to ehci debug port console" end -define DEFAULT_CONSOLE_LOGLEVEL +define CONFIG_DEFAULT_CONSOLE_LOGLEVEL default 7 export always comment "Console will log at this level unless changed" end -define MAXIMUM_CONSOLE_LOGLEVEL +define CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default 8 export always comment "Error messages up to this level can be printed" @@ -481,29 +481,29 @@ define CONFIG_SERIAL_POST export always comment "Enable SERIAL POST codes" end -define NO_POST +define CONFIG_NO_POST default none export used comment "Disable POST codes" end -define TTYS0_BASE +define CONFIG_TTYS0_BASE default 0x3f8 format "0x%x" export always comment "Base address for 8250 uart for the serial console" end -define TTYS0_BAUD +define CONFIG_TTYS0_BAUD default 115200 export always comment "Default baud rate for serial console" end -define TTYS0_DIV +define CONFIG_TTYS0_DIV default none format "%d" export used comment "Allow UART divisor to be set explicitly" end -define TTYS0_LCS +define CONFIG_TTYS0_LCS default 0x3 format "0x%x" export always @@ -515,7 +515,7 @@ define CONFIG_USE_PRINTK_IN_CAR export always comment "use printk instead of print in CAR stage code" end -define ASSEMBLER_DEBUG +define CONFIG_ASSEMBLER_DEBUG default 0 export always comment "Create disassembly files for debugging" @@ -525,35 +525,35 @@ end # Mainboard options ############################################### -define MAINBOARD +define CONFIG_MAINBOARD default "Mainboard_not_set" export always comment "Mainboard name" end -define MAINBOARD_PART_NUMBER +define CONFIG_MAINBOARD_PART_NUMBER default "Part_number_not_set" export always format "\"%s\"" comment "Part number of mainboard" end -define MAINBOARD_VENDOR +define CONFIG_MAINBOARD_VENDOR default "Vendor_not_set" export always format "\"%s\"" comment "Vendor of mainboard" end -define MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +define CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID default 0 export always comment "PCI Vendor ID of mainboard manufacturer" end -define MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +define CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID default 0 format "0x%x" export always comment "PCI susbsystem device id assigned my mainboard manufacturer" end -define MAINBOARD_POWER_ON_AFTER_POWER_FAIL +define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL default none export used comment "Default power on after power fail setting" @@ -597,27 +597,27 @@ define CONFIG_AP_IN_SIPI_WAIT export always comment "Should application processors go to SIPI wait state after initialization? (Required for Intel Core Duo)" end -define HAVE_MP_TABLE +define CONFIG_HAVE_MP_TABLE default none export used comment "Define to build an MP table" end -define SERIAL_CPU_INIT +define CONFIG_SERIAL_CPU_INIT default 1 export always comment "Serialize CPU init" end -define APIC_ID_OFFSET +define CONFIG_APIC_ID_OFFSET default 0 export always comment "We need to share this value between cache_as_ram_auto.c and northbridge.c" end -define ENABLE_APIC_EXT_ID +define CONFIG_ENABLE_APIC_EXT_ID default 0 export always comment "Enable APIC ext id mode 8 bit" end -define LIFT_BSP_APIC_ID +define CONFIG_LIFT_BSP_APIC_ID default 0 export always comment "decide if we lift bsp apic id while ap apic id" @@ -642,7 +642,7 @@ define CONFIG_ROM_PAYLOAD comment "Boot image is located in ROM" end define CONFIG_ROM_PAYLOAD_START - default {0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1} + default {0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1} format "0x%x" export always comment "ROM stream start location" @@ -692,19 +692,19 @@ define CONFIG_CBFS export always comment "The new CBFS file system" end -define AUTOBOOT_DELAY +define CONFIG_AUTOBOOT_DELAY default 2 export always comment "Delay (in seconds) before autobooting" end -define AUTOBOOT_CMDLINE +define CONFIG_AUTOBOOT_CMDLINE default "hdc1:/vmlinuz root=/dev/hdc3 console=tty0 console=ttyS0,115200" export always format "\"%s\"" comment "Default command line when autobooting" end -define USE_WATCHDOG_ON_BOOT +define CONFIG_USE_WATCHDOG_ON_BOOT default 0 export always comment "Use the watchdog on booting" @@ -744,17 +744,17 @@ end # IRQ options ############################################### -define HAVE_PIRQ_TABLE +define CONFIG_HAVE_PIRQ_TABLE default none export used comment "Define if we have a PIRQ table" end -define PIRQ_ROUTE +define CONFIG_PIRQ_ROUTE default 0 export always comment "Define if we have a PIRQ table and want routing IRQs" end -define IRQ_SLOT_COUNT +define CONFIG_IRQ_SLOT_COUNT default none export used comment "Number of IRQ slots" @@ -779,17 +779,17 @@ define CONFIG_IDE export always comment "Define to include IDE support" end -define IDE_BOOT_DRIVE +define CONFIG_IDE_BOOT_DRIVE default 0 export always comment "Disk number of boot drive" end -define IDE_SWAB +define CONFIG_IDE_SWAB default none export used comment "Swap bytes when reading from IDE device" end -define IDE_OFFSET +define CONFIG_IDE_OFFSET default 0 export always comment "Sector at which to start searching for boot image" @@ -799,49 +799,49 @@ end # Options for memory mapped I/O ############################################### -define PCI_IO_CFG_EXT +define CONFIG_PCI_IO_CFG_EXT default 0 export always comment "allow 4K register space via io CFG port" end -define PCIC0_CFGADDR +define CONFIG_PCIC0_CFGADDR default none format "0x%x" export used comment "Address of PCI Configuration Address Register" end -define PCIC0_CFGDATA +define CONFIG_PCIC0_CFGDATA default none format "0x%x" export used comment "Address of PCI Configuration Data Register" end -define ISA_IO_BASE +define CONFIG_ISA_IO_BASE default none format "0x%x" export used comment "Base address of PCI/ISA I/O address range" end -define ISA_MEM_BASE +define CONFIG_ISA_MEM_BASE default none format "0x%x" export used comment "Base address of PCI/ISA memory address range" end -define PNP_CFGADDR +define CONFIG_PNP_CFGADDR default none format "0x%x" export used comment "PNP Configuration Address Register offset" end -define PNP_CFGDATA +define CONFIG_PNP_CFGDATA default none format "0x%x" export used comment "PNP Configuration Data Register offset" end -define _IO_BASE +define CONFIG_IO_BASE default none format "0x%x" export used @@ -852,7 +852,7 @@ end # Options for embedded systems ############################################### -define EMBEDDED_RAM_SIZE +define CONFIG_EMBEDDED_RAM_SIZE default none export used comment "Embedded boards generally have fixed RAM size" @@ -868,27 +868,27 @@ define CONFIG_GDB_STUB comment "Compile in gdb stub support?" end -define HAVE_INIT_TIMER +define CONFIG_HAVE_INIT_TIMER default 0 export always comment "Have a init_timer function" end -define HAVE_HARD_RESET +define CONFIG_HAVE_HARD_RESET default none export used comment "Have hard reset" end -define HAVE_SMI_HANDLER +define CONFIG_HAVE_SMI_HANDLER default 0 export always comment "Set, if the board needs an SMI handler" end -define MEMORY_HOLE +define CONFIG_MEMORY_HOLE default none export used comment "Set to deal with memory hole" end -define MAX_REBOOT_CNT +define CONFIG_MAX_REBOOT_CNT default 3 export always comment "Set maximum reboots" @@ -898,7 +898,7 @@ end # Misc device options ############################################### -define HAVE_FANCTL +define CONFIG_HAVE_FANCTL default 0 export used comment "Include board specific FAN control initialization" @@ -908,7 +908,7 @@ define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 export used comment "Use timer2 to callibrate the x86 time stamp counter" end -define INTEL_PPRO_MTRR +define CONFIG_INTEL_PPRO_MTRR default none export used comment "" @@ -923,93 +923,93 @@ define CONFIG_UDELAY_IO export used comment "Implement udelay with x86 io registers" end -define FAKE_SPDROM +define CONFIG_FAKE_SPDROM default 0 export always comment "Use this to fake spd rom values" end -define HAVE_ACPI_TABLES +define CONFIG_HAVE_ACPI_TABLES default 0 export always comment "Define to build ACPI tables" end -define HAVE_ACPI_RESUME +define CONFIG_HAVE_ACPI_RESUME default 0 export always comment "Define to build ACPI with resume support" end -define ACPI_SSDTX_NUM +define CONFIG_ACPI_SSDTX_NUM default 0 export always comment "extra ssdt num for PCI Device" end -define AGP_APERTURE_SIZE +define CONFIG_AGP_APERTURE_SIZE default none export used format "0x%x" comment "AGP graphics virtual memory aperture size" end -define HT_CHAIN_UNITID_BASE +define CONFIG_HT_CHAIN_UNITID_BASE default 1 export always comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0" end -define HT_CHAIN_END_UNITID_BASE +define CONFIG_HT_CHAIN_END_UNITID_BASE default 0x20 export always - comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than HT_CHAIN_UNITID_BASE, it could be 0" + comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than CONFIG_HT_CHAIN_UNITID_BASE, it could be 0" end -define SB_HT_CHAIN_UNITID_OFFSET_ONLY +define CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY default 1 export always comment "this will decided if only offset SB hypertransport chain" end -define SB_HT_CHAIN_ON_BUS0 +define CONFIG_SB_HT_CHAIN_ON_BUS0 default 0 export always comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0" end -define PCI_BUS_SEGN_BITS +define CONFIG_PCI_BUS_SEGN_BITS default 0 export always comment "It could be 0, 1, 2, 3 and 4 only" end -define MMCONF_SUPPORT +define CONFIG_MMCONF_SUPPORT default 0 export always comment "enable mmconfig for pci conf" end -define MMCONF_SUPPORT_DEFAULT +define CONFIG_MMCONF_SUPPORT_DEFAULT default 0 export always comment "enable mmconfig for pci conf" end -define MMCONF_BASE_ADDRESS +define CONFIG_MMCONF_BASE_ADDRESS default none format "0x%x" export used comment "enable mmconfig base address" end -define HW_MEM_HOLE_SIZEK +define CONFIG_HW_MEM_HOLE_SIZEK default 0 export always comment "Opteron E0 later memory hole size in K, 0 mean disable" end -define HW_MEM_HOLE_SIZE_AUTO_INC +define CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC default 0 export always comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek" @@ -1021,62 +1021,62 @@ define CONFIG_VAR_MTRR_HOLE comment "using hole in MTRR instead of increasing method" end -define K8_HT_FREQ_1G_SUPPORT +define CONFIG_K8_HT_FREQ_1G_SUPPORT default 0 export always comment "Optern E0 later could support 1G HT, but still depends MB design" end -define K8_REV_F_SUPPORT +define CONFIG_K8_REV_F_SUPPORT default 0 export always comment "Opteron Rev F (DDR2) support" end -define CBB +define CONFIG_CBB default 0 export always comment "Opteron cpu bus num base" end -define CDB +define CONFIG_CDB default 0x18 export always comment "Opteron cpu device num base" end -define HT3_SUPPORT +define CONFIG_HT3_SUPPORT default 0 export always comment "Hypertransport 3 support, include ac HT and unganged sublink feature" end -define EXT_RT_TBL_SUPPORT +define CONFIG_EXT_RT_TBL_SUPPORT default 0 export always comment "support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8" end -define EXT_CONF_SUPPORT +define CONFIG_EXT_CONF_SUPPORT default 0 export always comment "support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4" end -define DIMM_SUPPORT +define CONFIG_DIMM_SUPPORT default 0x0108 format "0x%x" export always comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg" end -define CPU_SOCKET_TYPE +define CONFIG_CPU_SOCKET_TYPE default 0x10 export always comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3" end -define CPU_ADDR_BITS +define CONFIG_CPU_ADDR_BITS default 36 export always comment "CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48" @@ -1137,14 +1137,14 @@ define CONFIG_AMDMCT comment "use AMD MCT to init RAM instead of native code" end -define AMD_UCODE_PATCH_FILE +define CONFIG_AMD_UCODE_PATCH_FILE default none export used format "\"%s\"" comment "name of the microcode patch file" end -define K8_MEM_BANK_B_ONLY +define CONFIG_K8_MEM_BANK_B_ONLY default 0 export always comment "use AMD K8's memory bank B only to make a 64bit memory system and memory bank A is free, such as Filbert." @@ -1162,19 +1162,19 @@ define CONFIG_GFXUMA comment "GFX UMA" end -define HAVE_MAINBOARD_RESOURCES +define CONFIG_HAVE_MAINBOARD_RESOURCES default 0 export always comment "Enable if the mainboard/chipset requires extra entries in the memory map" end -define HAVE_LOW_TABLES +define CONFIG_HAVE_LOW_TABLES default 1 export always comment "Enable if ACPI, PIRQ, MP tables are supposed to live in the low megabyte" end -define HAVE_HIGH_TABLES +define CONFIG_HAVE_HIGH_TABLES default 0 export always comment "Enable if ACPI, PIRQ, MP tables are supposed to live at top of memory" diff --git a/src/config/coreboot_apc.ld b/src/config/coreboot_apc.ld index 9bca028ca1..d7820aafe1 100644 --- a/src/config/coreboot_apc.ld +++ b/src/config/coreboot_apc.ld @@ -1,7 +1,7 @@ /* * Memory map: * - * DCACHE_RAM_BASE + * CONFIG_DCACHE_RAM_BASE * : data segment * : bss segment * : heap @@ -28,7 +28,7 @@ ENTRY(_start) SECTIONS { - . = DCACHE_RAM_BASE; + . = CONFIG_DCACHE_RAM_BASE; /* * First we place the code and read only data (typically const declared). * This get placed in rom. @@ -90,7 +90,7 @@ SECTIONS _ram_seg = _text; _eram_seg = _eheap; - _bogus = ASSERT( ( _eram_seg <= ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big"); + _bogus = ASSERT( ( _eram_seg <= ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big"); /DISCARD/ : { *(.comment) diff --git a/src/config/coreboot_ram.ld b/src/config/coreboot_ram.ld index 4b41adb30d..2934b2e6e2 100644 --- a/src/config/coreboot_ram.ld +++ b/src/config/coreboot_ram.ld @@ -1,7 +1,7 @@ /* * Memory map: * - * _RAMBASE + * CONFIG_RAMBASE * : data segment * : bss segment * : heap @@ -27,7 +27,7 @@ ENTRY(_start) SECTIONS { - . = _RAMBASE; + . = CONFIG_RAMBASE; /* * First we place the code and read only data (typically const declared). * This get placed in rom. @@ -99,18 +99,18 @@ SECTIONS } _ebss = .; _end = .; - . = ALIGN(STACK_SIZE); + . = ALIGN(CONFIG_STACK_SIZE); _stack = .; .stack . : { /* Reserve a stack for each possible cpu */ /* the stack for ap will be put after pgtbl in 1M to CONFIG_LB_MEM_TOPK range when VGA and ROM_RUN and CONFIG_LB_MEM_TOPK>1024*/ - . = ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(_RAMBASE<0x100000)&&(CONFIG_LB_MEM_TOPK>(0x100000>>10)) ) ? STACK_SIZE : (CONFIG_MAX_CPUS*STACK_SIZE); + . = ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(CONFIG_RAMBASE<0x100000)&&(CONFIG_LB_MEM_TOPK>(0x100000>>10)) ) ? CONFIG_STACK_SIZE : (CONFIG_MAX_CPUS*CONFIG_STACK_SIZE); } _estack = .; _heap = .; .heap . : { - /* Reserve HEAP_SIZE bytes for the heap */ - . = HEAP_SIZE ; + /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ + . = CONFIG_HEAP_SIZE ; . = ALIGN(4); } _eheap = .; @@ -122,7 +122,7 @@ SECTIONS _bogus = ASSERT( ( (_eram_seg>>10) < (CONFIG_LB_MEM_TOPK)) , "please increase CONFIG_LB_MEM_TOPK"); - _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_LB_MEM_TOPK and if still fail, try to set _RAMBASE more than 1M"); + _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_LB_MEM_TOPK and if still fail, try to set CONFIG_RAMBASE more than 1M"); /DISCARD/ : { *(.comment) diff --git a/src/config/failovercalculation.lb b/src/config/failovercalculation.lb index d3047a84bc..7626289e2d 100644 --- a/src/config/failovercalculation.lb +++ b/src/config/failovercalculation.lb @@ -2,20 +2,20 @@ ## Compute the location and size of where this firmware image ## (coreboot plus bootloader) will live in the boot rom chip. ## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) +if CONFIG_USE_FAILOVER_IMAGE + default CONFIG_ROM_SECTION_SIZE = CONFIG_FAILOVER_SIZE + default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FAILOVER_SIZE ) else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) + if CONFIG_USE_FALLBACK_IMAGE + default CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE + default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE ) else if CONFIG_CBFS - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) + default CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE + default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE ) else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 + default CONFIG_ROM_SECTION_SIZE = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE ) + default CONFIG_ROM_SECTION_OFFSET = 0 end end end @@ -24,29 +24,29 @@ end ## Compute the start location and size size of ## The coreboot bootloader. ## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default CONFIG_PAYLOAD_SIZE = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) ## ## Compute where this copy of coreboot will start in the boot rom ## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) +default CONFIG_ROMBASE = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE ) ## ## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## -## XIP_ROM_SIZE must be a power of 2 and is set in mainboard Config.lb -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## CONFIG_XIP_ROM_SIZE must be a power of 2 and is set in mainboard Config.lb +## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE ## -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) +if CONFIG_USE_FAILOVER_IMAGE + default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE) else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) + if CONFIG_USE_FALLBACK_IMAGE + default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE + CONFIG_FAILOVER_SIZE) else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) + default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE) end end diff --git a/src/config/nofailovercalculation.lb b/src/config/nofailovercalculation.lb index b23de14418..82132f4acb 100644 --- a/src/config/nofailovercalculation.lb +++ b/src/config/nofailovercalculation.lb @@ -2,16 +2,16 @@ ## Compute the location and size of where this firmware image ## (coreboot plus bootloader) will live in the boot rom chip. ## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +if CONFIG_USE_FALLBACK_IMAGE + default CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE + default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE ) else if CONFIG_CBFS - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FALLBACK_SIZE ) + default CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE + default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE ) else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 + default CONFIG_ROM_SECTION_SIZE = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE ) + default CONFIG_ROM_SECTION_OFFSET = 0 end end @@ -19,19 +19,19 @@ end ## Compute the start location and size size of ## The coreboot bootloader. ## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default CONFIG_PAYLOAD_SIZE = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) ## ## Compute where this copy of coreboot will start in the boot rom ## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) +default CONFIG_ROMBASE = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE ) ## ## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## -## XIP_ROM_SIZE must be a power of 2 and is set in mainboard Config.lb -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## CONFIG_XIP_ROM_SIZE must be a power of 2 and is set in mainboard Config.lb +## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE ## -default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE ) +default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE ) diff --git a/src/console/console.c b/src/console/console.c index af790de217..78823afdb5 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -15,7 +15,7 @@ void console_init(void) { struct console_driver *driver; if(get_option(&console_loglevel, "debug_level")) - console_loglevel=DEFAULT_CONSOLE_LOGLEVEL; + console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL; for(driver = console_drivers; driver < econsole_drivers; driver++) { if (!driver->init) @@ -83,7 +83,7 @@ int console_tst_byte(void) */ void post_code(uint8_t value) { -#if !defined(NO_POST) || NO_POST==0 +#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0 #if CONFIG_SERIAL_POST==1 printk_emerg("POST: 0x%02x\n", value); #endif diff --git a/src/console/printk.c b/src/console/printk.c index 01a52afc4c..0485a001da 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -17,10 +17,10 @@ /* Keep together for sysctl support */ -int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; +int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; int default_message_loglevel = DEFAULT_MESSAGE_LOGLEVEL; int minimum_console_loglevel = MINIMUM_CONSOLE_LOGLEVEL; -int default_console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; +int default_console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; void display(char*); extern int vtxprintf(void (*)(unsigned char), const char *, va_list); diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index 37364e710d..fd71ff7dc2 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -3,54 +3,54 @@ #include <pc80/mc146818rtc.h> /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#ifndef TTYS0_DIV -#if ((115200%TTYS0_BAUD) != 0) +#ifndef CONFIG_TTYS0_DIV +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) #endif /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS static void ttyS0_init(void) { static const unsigned char div[8]={1,2,3,6,12,24,48,96}; int b_index=0; - unsigned int divisor=TTYS0_DIV; + unsigned int divisor=CONFIG_TTYS0_DIV; if(get_option(&b_index,"baud_rate")==0) { divisor=div[b_index]; } - uart8250_init(TTYS0_BASE, divisor, TTYS0_LCS); + uart8250_init(CONFIG_TTYS0_BASE, divisor, CONFIG_TTYS0_LCS); } static void ttyS0_tx_byte(unsigned char data) { - uart8250_tx_byte(TTYS0_BASE, data); + uart8250_tx_byte(CONFIG_TTYS0_BASE, data); } static unsigned char ttyS0_rx_byte(void) { - return uart8250_rx_byte(TTYS0_BASE); + return uart8250_rx_byte(CONFIG_TTYS0_BASE); } static int ttyS0_tst_byte(void) { - return uart8250_can_rx_byte(TTYS0_BASE); + return uart8250_can_rx_byte(CONFIG_TTYS0_BASE); } static const struct console_driver uart8250_console __console = { diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 94990a66f7..50b78d0c92 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -18,13 +18,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define CacheSize DCACHE_RAM_SIZE +#define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) /* leave some space for global variable to pass to RAM stage */ -#define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE +#define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -/* for CAR_FAM10 */ +/* for CONFIG_CAR_FAM10 */ #define CacheSizeAPStack 0x400 /* 1K */ #define MSR_FAM10 0xC001102A @@ -72,7 +72,7 @@ cache_as_ram_setup: cvtsd2si %xmm3, %ebx /* hope we can skip the double set for normal part */ -#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) /* check if cpu_init_detected */ movl $MTRRdefType_MSR, %ecx @@ -248,10 +248,10 @@ clear_fixed_var_mtrr_out: xorl %edx, %edx movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax wrmsr -#endif /* USE_FAILOVER_IMAGE == 1*/ +#endif /* CONFIG_USE_FAILOVER_IMAGE == 1*/ -#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 0)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 0)) +#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0)) /* disable cache */ movl %cr0, %eax orl $(1 << 30),%eax @@ -259,25 +259,25 @@ clear_fixed_var_mtrr_out: #endif -#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) +#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* enable write base caching so we can do execute in place * on the flash rom. */ movl $0x202, %ecx xorl %edx, %edx - movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax wrmsr movl $0x203, %ecx - movl $0xff, %edx /* (1 << (CPU_ADDR_BITS - 32)) - 1 for K8 (CPU_ADDR_BITS = 40) */ + movl $0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */ jmp_if_k8(wbcache_post_fam10_setup) - movl $0xffff, %edx /* (1 << (CPU_ADDR_BITS - 32)) - 1 for FAM10 (CPU_ADDR_BITS = 48) */ + movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */ wbcache_post_fam10_setup: - movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr -#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ -#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) /* Set the default memory type and enable fixed and variable MTRRs */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx @@ -313,7 +313,7 @@ fam10_end_part1: movb $0xA2, %al outb %al, $0x80 -#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) /* Read the range with lodsl*/ cld movl $CacheBase, %esi @@ -325,7 +325,7 @@ fam10_end_part1: xorl %eax, %eax rep stosl -#endif /*USE_FAILOVER_IMAGE == 1*/ +#endif /*CONFIG_USE_FAILOVER_IMAGE == 1*/ /* set up the stack pointer */ movl $(CacheBase + CacheSize - GlobalVarSize), %eax diff --git a/src/cpu/amd/car/clear_init_ram.c b/src/cpu/amd/car/clear_init_ram.c index 8b97129ec6..0b50480142 100644 --- a/src/cpu/amd/car/clear_init_ram.c +++ b/src/cpu/amd/car/clear_init_ram.c @@ -7,11 +7,11 @@ static void __attribute__((noinline)) clear_init_ram(void) // will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already // so noline clear_init_ram -#if HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME == 1 /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ - clear_memory( _RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - _RAMBASE - DCACHE_RAM_SIZE); + clear_memory( CONFIG_RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); #else - clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE)); + clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_SIZE)); #endif } diff --git a/src/cpu/amd/car/copy_and_run.c b/src/cpu/amd/car/copy_and_run.c index 437b91d4ac..f495f6dbba 100644 --- a/src/cpu/amd/car/copy_and_run.c +++ b/src/cpu/amd/car/copy_and_run.c @@ -8,7 +8,7 @@ void cbfs_and_run_core(char*, unsigned ebp); static void copy_and_run(void) { -# if USE_FALLBACK_IMAGE == 1 +# if CONFIG_USE_FALLBACK_IMAGE == 1 cbfs_and_run_core("fallback/coreboot_ram", 0); # else cbfs_and_run_core("normal/coreboot_ram", 0); @@ -19,7 +19,7 @@ static void copy_and_run(void) static void copy_and_run_ap_code_in_car(unsigned ret_addr) { -# if USE_FALLBACK_IMAGE == 1 +# if CONFIG_USE_FALLBACK_IMAGE == 1 cbfs_and_run_core("fallback/coreboot_apc", ret_addr); # else cbfs_and_run_core("normal/coreboot_apc", ret_addr); diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 0f5f831270..a5113474d3 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -16,7 +16,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void) "xorl %edx, %edx\n\t" "xorl %eax, %eax\n\t" "wrmsr\n\t" -#if DCACHE_RAM_SIZE > 0x8000 +#if CONFIG_DCACHE_RAM_SIZE > 0x8000 "movl $0x268, %ecx\n\t" /* fix4k_c0000*/ "wrmsr\n\t" #endif diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 89366e0e33..9e988f02be 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -64,7 +64,7 @@ static void post_cache_as_ram(void) set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_LB_MEM_TOPK) */ -// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x8000, DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x7c00); +// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00); print_debug("Copying data from cache to RAM -- switching to use RAM as stack... "); /* from here don't store more data in CAR */ @@ -76,14 +76,14 @@ static void post_cache_as_ram(void) ); #endif - memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE), (void *)DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline + memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline // dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00); __asm__ volatile ( - /* set new esp */ /* before _RAMBASE */ + /* set new esp */ /* before CONFIG_RAMBASE */ "subl %0, %%ebp\n\t" "subl %0, %%esp\n\t" - ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) ) + ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) ) ); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp #if 0 __asm__ volatile ( @@ -102,18 +102,18 @@ static void post_cache_as_ram(void) disable_cache_as_ram_bsp(); print_debug("Clearing initial memory region: "); - clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10)) + clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10)) print_debug("Done\r\n"); // dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00); -#ifndef MEM_TRAIN_SEQ -#define MEM_TRAIN_SEQ 0 +#ifndef CONFIG_MEM_TRAIN_SEQ +#define CONFIG_MEM_TRAIN_SEQ 0 #endif set_sysinfo_in_ram(1); // So other core0 could start to train mem -#if MEM_TRAIN_SEQ == 1 -// struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); +#if CONFIG_MEM_TRAIN_SEQ == 1 +// struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // wait for ap memory to trained // wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c index 899b859d4f..8401818fb6 100644 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ b/src/cpu/amd/dualcore/amd_sibling.c @@ -110,7 +110,7 @@ unsigned get_apicid_base(unsigned ioapic_num) if((apicid_base+ioapic_num-1)>0xf) { // We need to enable APIC EXT ID - printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in auto.c so you can spare 16 id for ioapic\r\n"); + printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in auto.c so you can spare 16 id for ioapic\r\n"); enable_apic_ext_id(nodes); } diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c index 5a61fac699..331c75909a 100644 --- a/src/cpu/amd/dualcore/dualcore.c +++ b/src/cpu/amd/dualcore/dualcore.c @@ -19,7 +19,7 @@ static inline unsigned get_core_num_in_bsp(unsigned nodeid) #if SET_NB_CFG_54 == 1 static inline uint8_t set_apicid_cpuid_lo(void) { -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set #endif @@ -56,7 +56,7 @@ static inline void start_other_cores(void) unsigned nodes; unsigned nodeid; - if (HAVE_OPTION_TABLE && + if (CONFIG_HAVE_OPTION_TABLE && read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { return; // disable dual_core } @@ -70,7 +70,7 @@ static inline void start_other_cores(void) } } -#if USE_DCACHE_RAM == 0 +#if CONFIG_USE_DCACHE_RAM == 0 static void do_k8_init_and_stop_secondaries(void) { struct node_core_id id; @@ -106,22 +106,22 @@ static void do_k8_init_and_stop_secondaries(void) pci_write_config32(dev_f0, 0x68, val); /* Set the lapicid */ - #if (ENABLE_APIC_EXT_ID == 1) + #if (CONFIG_ENABLE_APIC_EXT_ID == 1) unsigned initial_apicid = get_initial_apicid(); - #if LIFT_BSP_APIC_ID == 0 + #if CONFIG_LIFT_BSP_APIC_ID == 0 if( initial_apicid != 0 ) // other than bsp #endif { /* use initial apic id to lift it */ uint32_t dword = lapic_read(LAPIC_ID); dword &= ~(0xff<<24); - dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff)<<24); + dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff)<<24); lapic_write(LAPIC_ID, dword); } - #if LIFT_BSP_APIC_ID == 1 - bsp_apicid += APIC_ID_OFFSET; + #if CONFIG_LIFT_BSP_APIC_ID == 1 + bsp_apicid += CONFIG_APIC_ID_OFFSET; #endif #endif diff --git a/src/cpu/amd/model_10xxx/Config.lb b/src/cpu/amd/model_10xxx/Config.lb index 47303be0e8..884f1e84f4 100644 --- a/src/cpu/amd/model_10xxx/Config.lb +++ b/src/cpu/amd/model_10xxx/Config.lb @@ -17,13 +17,13 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -uses HAVE_INIT_TIMER -uses HAVE_MOVNTI -uses CPU_ADDR_BITS +uses CONFIG_HAVE_INIT_TIMER +uses CONFIG_HAVE_MOVNTI +uses CONFIG_CPU_ADDR_BITS -default HAVE_INIT_TIMER=1 -default HAVE_MOVNTI=1 -default CPU_ADDR_BITS=48 +default CONFIG_HAVE_INIT_TIMER=1 +default CONFIG_HAVE_MOVNTI=1 +default CONFIG_CPU_ADDR_BITS=48 dir /cpu/x86/tsc dir /cpu/x86/fpu dir /cpu/x86/mmx diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 92eb2de0c8..66959839c2 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -19,7 +19,7 @@ #include "defaults.h" -//it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID +//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID #ifndef FAM10_SET_FIDVID #define FAM10_SET_FIDVID 1 #endif @@ -58,13 +58,13 @@ static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid); void cpuSetAMDMSR(void); -#if PCI_IO_CFG_EXT == 1 +#if CONFIG_PCI_IO_CFG_EXT == 1 static void set_EnableCf8ExtCfg(void) { // set the NB_CFG[46]=1; msr_t msr; msr = rdmsr(NB_CFG_MSR); - // EnableCf8ExtCfg: We need that to access PCI_IO_CFG_EXT 4K range + // EnableCf8ExtCfg: We need that to access CONFIG_PCI_IO_CFG_EXT 4K range msr.hi |= (1<<(46-32)); wrmsr(NB_CFG_MSR, msr); } @@ -80,12 +80,12 @@ static void set_EnableCf8ExtCfg(void) { } static void set_pci_mmio_conf_reg(void) { -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT msr_t msr; msr = rdmsr(0xc0010058); msr.lo &= ~(0xfff00000 | (0xf << 2)); // 256 bus per segment, MMIO reg will be 4G , enable MMIO Config space - msr.lo |= ((8+PCI_BUS_SEGN_BITS) << 2) | (1 << 0); + msr.lo |= ((8+CONFIG_PCI_BUS_SEGN_BITS) << 2) | (1 << 0); msr.hi &= ~(0x0000ffff); msr.hi |= (PCI_MMIO_BASE >> (32-8)); wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg @@ -168,11 +168,11 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, for (j = jstart; j <= jend; j++) { ap_apicid = i * (nb_cfg_54 ? (siblings + 1):1) + j * (nb_cfg_54 ? 1:64); - #if (ENABLE_APIC_EXT_ID == 1) && (APIC_ID_OFFSET > 0) - #if LIFT_BSP_APIC_ID == 0 + #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0) + #if CONFIG_LIFT_BSP_APIC_ID == 0 if( (i != 0) || (j != 0)) /* except bsp */ #endif - ap_apicid += APIC_ID_OFFSET; + ap_apicid += CONFIG_APIC_ID_OFFSET; #endif if(ap_apicid == bsp_apicid) continue; @@ -307,8 +307,8 @@ static void STOP_CAR_AND_CPU() } -#ifndef MEM_TRAIN_SEQ -#define MEM_TRAIN_SEQ 0 +#ifndef CONFIG_MEM_TRAIN_SEQ +#define CONFIG_MEM_TRAIN_SEQ 0 #endif #if RAMINIT_SYSINFO == 1 @@ -337,7 +337,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) if(id.coreid == 0) { set_apicid_cpuid_lo(); /* only set it on core0 */ set_EnableCf8ExtCfg(); /* only set it on core0 */ - #if (ENABLE_APIC_EXT_ID == 1) + #if (CONFIG_ENABLE_APIC_EXT_ID == 1) enable_apic_ext_id(id.nodeid); #endif } @@ -345,23 +345,23 @@ static u32 init_cpus(u32 cpu_init_detectedx) enable_lapic(); -#if (ENABLE_APIC_EXT_ID == 1) && (APIC_ID_OFFSET > 0) +#if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0) u32 initial_apicid = get_initial_apicid(); - #if LIFT_BSP_APIC_ID == 0 + #if CONFIG_LIFT_BSP_APIC_ID == 0 if( initial_apicid != 0 ) // other than bsp #endif { /* use initial apic id to lift it */ u32 dword = lapic_read(LAPIC_ID); dword &= ~(0xff << 24); - dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff) << 24); + dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff) << 24); lapic_write(LAPIC_ID, dword); } - #if LIFT_BSP_APIC_ID == 1 - bsp_apicid += APIC_ID_OFFSET; + #if CONFIG_LIFT_BSP_APIC_ID == 1 + bsp_apicid += CONFIG_APIC_ID_OFFSET; #endif #endif @@ -478,8 +478,8 @@ static void start_node(u8 node) /* Enable routing table */ printk_debug("Start node %02x", node); -#if CAR_FAM10 == 1 - /* For CAR_FAM10 support, we need to set Dram base/limit for the new node */ +#if CONFIG_CAR_FAM10 == 1 + /* For CONFIG_CAR_FAM10 support, we need to set Dram base/limit for the new node */ pci_write_config32(NODE_MP(node), 0x44, 0); pci_write_config32(NODE_MP(node), 0x40, 3); #endif diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c index f7f717d110..f996247d8d 100644 --- a/src/cpu/amd/model_10xxx/update_microcode.c +++ b/src/cpu/amd/model_10xxx/update_microcode.c @@ -47,7 +47,7 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = { * 00100F62h (DA-C2) 1062h 0100009Fh */ -#include AMD_UCODE_PATCH_FILE +#include CONFIG_AMD_UCODE_PATCH_FILE #endif /* Dummy terminator */ diff --git a/src/cpu/amd/model_fxx/Config.lb b/src/cpu/amd/model_fxx/Config.lb index 550716bc38..28ba85f8a9 100644 --- a/src/cpu/amd/model_fxx/Config.lb +++ b/src/cpu/amd/model_fxx/Config.lb @@ -1,10 +1,10 @@ -uses HAVE_INIT_TIMER -uses HAVE_MOVNTI -uses CPU_ADDR_BITS +uses CONFIG_HAVE_INIT_TIMER +uses CONFIG_HAVE_MOVNTI +uses CONFIG_CPU_ADDR_BITS -default HAVE_INIT_TIMER=1 -default HAVE_MOVNTI=1 -default CPU_ADDR_BITS=40 +default CONFIG_HAVE_INIT_TIMER=1 +default CONFIG_HAVE_MOVNTI=1 +default CONFIG_CPU_ADDR_BITS=40 dir /cpu/x86/tsc dir /cpu/x86/fpu dir /cpu/x86/mmx diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index f0f7b7fdd2..f079776f25 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -73,7 +73,7 @@ static void enable_fid_change(void) // dword = 0x00070000; /* enable FID/VID change */ pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0x80, dword); -#if HAVE_ACPI_RESUME +#if CONFIG_HAVE_ACPI_RESUME dword = 0x21132113; #else dword = 0x00132113; diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 8b613a624e..435167e94a 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -1,6 +1,6 @@ -//it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID +//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID #ifndef K8_SET_FIDVID - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 #define K8_SET_FIDVID 0 #else // for rev F, need to set FID to max @@ -72,7 +72,7 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t p nodes = get_nodes(); disable_siblings = !CONFIG_LOGICAL_CPUS; -#if CONFIG_LOGICAL_CPUS == 1 && HAVE_OPTION_TABLE == 1 +#if CONFIG_LOGICAL_CPUS == 1 && CONFIG_HAVE_OPTION_TABLE == 1 if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // 0 mean dual core disable_siblings = 1; } @@ -87,7 +87,7 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t p j = ((pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xe8) >> 12) & 3); if(nb_cfg_54) { if(j == 0 ){ // if it is single core, we need to increase siblings for apic calculation - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 e0_later_single_core = is_e0_later_in_bsp(i); // single core #else e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 @@ -119,11 +119,11 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t p ap_apicid = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); - #if (ENABLE_APIC_EXT_ID == 1) - #if LIFT_BSP_APIC_ID == 0 + #if (CONFIG_ENABLE_APIC_EXT_ID == 1) + #if CONFIG_LIFT_BSP_APIC_ID == 0 if( (i!=0) || (j!=0)) /* except bsp */ #endif - ap_apicid += APIC_ID_OFFSET; + ap_apicid += CONFIG_APIC_ID_OFFSET; #endif if(ap_apicid == bsp_apicid) continue; @@ -238,12 +238,12 @@ static void STOP_CAR_AND_CPU(void) stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp .... } -#ifndef MEM_TRAIN_SEQ -#define MEM_TRAIN_SEQ 0 +#ifndef CONFIG_MEM_TRAIN_SEQ +#define CONFIG_MEM_TRAIN_SEQ 0 #endif -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall); #endif @@ -268,7 +268,7 @@ static unsigned init_cpus(unsigned cpu_init_detectedx) /* NB_CFG MSR is shared between cores, so we need make sure core0 is done at first --- use wait_all_core0_started */ if(id.coreid == 0) { set_apicid_cpuid_lo(); /* only set it on core0 */ - #if ENABLE_APIC_EXT_ID == 1 + #if CONFIG_ENABLE_APIC_EXT_ID == 1 enable_apic_ext_id(id.nodeid); #endif } @@ -276,22 +276,22 @@ static unsigned init_cpus(unsigned cpu_init_detectedx) enable_lapic(); // init_timer(); // We need TMICT to pass msg for FID/VID change - #if (ENABLE_APIC_EXT_ID == 1) + #if (CONFIG_ENABLE_APIC_EXT_ID == 1) unsigned initial_apicid = get_initial_apicid(); - #if LIFT_BSP_APIC_ID == 0 + #if CONFIG_LIFT_BSP_APIC_ID == 0 if( initial_apicid != 0 ) // other than bsp #endif { /* use initial apic id to lift it */ uint32_t dword = lapic_read(LAPIC_ID); dword &= ~(0xff<<24); - dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff)<<24); + dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff)<<24); lapic_write(LAPIC_ID, dword); } - #if LIFT_BSP_APIC_ID == 1 - bsp_apicid += APIC_ID_OFFSET; + #if CONFIG_LIFT_BSP_APIC_ID == 1 + bsp_apicid += CONFIG_APIC_ID_OFFSET; #endif #endif @@ -346,7 +346,7 @@ static unsigned init_cpus(unsigned cpu_init_detectedx) } lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu set_init_ram_access(); - #if MEM_TRAIN_SEQ == 1 + #if CONFIG_MEM_TRAIN_SEQ == 1 train_ram_on_node(id.nodeid, id.coreid, sysinfo, STOP_CAR_AND_CPU); #endif diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 3bccfe0d83..d183bf89bc 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -32,15 +32,15 @@ void cpus_ready_for_init(void) { -#if MEM_TRAIN_SEQ == 1 - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); +#if CONFIG_MEM_TRAIN_SEQ == 1 + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // wait for ap memory to trained wait_all_core0_mem_trained(sysinfox); #endif } -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 int is_e0_later_in_bsp(int nodeid) { uint32_t val; @@ -67,7 +67,7 @@ int is_e0_later_in_bsp(int nodeid) } #endif -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; @@ -289,8 +289,8 @@ static void init_ecc_memory(unsigned node_id) startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2; endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000; -#if HW_MEM_HOLE_SIZEK != 0 - #if K8_REV_F_SUPPORT == 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) { #endif @@ -300,7 +300,7 @@ static void init_ecc_memory(unsigned node_id) if(val & 1) { hole_startk = ((val & (0xff<<24)) >> 10); } - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 } #endif #endif @@ -322,7 +322,7 @@ static void init_ecc_memory(unsigned node_id) disable_lapic(); /* Walk through 2M chunks and zero them */ -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* here hole_startk can not be equal to begink, never. Also hole_startk is in 2M boundary, 64M? */ if ( (hole_startk != 0) && ((begink < hole_startk) && (endk>(4*1024*1024)))) { for(basek = begink; basek < hole_startk; @@ -368,7 +368,7 @@ static void init_ecc_memory(unsigned node_id) static inline void k8_errata(void) { msr_t msr; -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 if (is_cpu_pre_c0()) { /* Erratum 63... */ msr = rdmsr(HWCR_MSR); @@ -438,7 +438,7 @@ static inline void k8_errata(void) } #endif -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) #endif { @@ -453,7 +453,7 @@ static inline void k8_errata(void) msr.lo |= 1 << 6; wrmsr(HWCR_MSR, msr); -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 /* Erratum 131... */ msr = rdmsr(NB_CFG_MSR); msr.lo |= 1 << 20; @@ -478,7 +478,7 @@ void model_fxx_init(device_t dev) unsigned siblings; #endif -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 struct cpuinfo_x86 c; get_fms(&c, dev->device); @@ -564,7 +564,7 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 { X86_VENDOR_AMD, 0xf40 }, /* SH-B0 (socket 754) */ { X86_VENDOR_AMD, 0xf50 }, /* SH-B0 (socket 940) */ { X86_VENDOR_AMD, 0xf51 }, /* SH-B3 (socket 940) */ @@ -606,7 +606,7 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x30ff2 }, /* E4 ? */ #endif -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 /* * AMD F0 support. * diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c index e210846479..68a2cea070 100644 --- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c +++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c @@ -52,13 +52,13 @@ $1.0$ static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 #include "microcode_rev_c.h" #include "microcode_rev_d.h" #include "microcode_rev_e.h" #endif -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 // #include "microcode_rev_f.h" #endif /* Dummy terminator */ @@ -70,7 +70,7 @@ static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { static unsigned id_mapping_table[] = { - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 0x0f48, 0x0048, 0x0f58, 0x0048, @@ -93,7 +93,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { 0x20fb1, 0x0210, #endif - #if K8_REV_F_SUPPORT == 1 + #if CONFIG_K8_REV_F_SUPPORT == 1 #endif diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index 6ad1686dad..b68382761f 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -169,7 +169,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) cpuid1 = cpuid(0x80000001); pwr_lmt = ((cpuid1.ebx & 0x1C0) >> 5) | ((cpuid1.ebx & 0x4000) >> 14); for (index = 0; index <= sizeof(TDP) / sizeof(TDP[0]); index++) - if (TDP[index].socket_type == CPU_SOCKET_TYPE && + if (TDP[index].socket_type == CONFIG_CPU_SOCKET_TYPE && TDP[index].cmp_cap == cmp_cap && TDP[index].pwr_lmt == pwr_lmt) { power_limit = TDP[index].power_limit; diff --git a/src/cpu/amd/model_fxx/processor_name.c b/src/cpu/amd/model_fxx/processor_name.c index df187cb1d2..5c87266f23 100644 --- a/src/cpu/amd/model_fxx/processor_name.c +++ b/src/cpu/amd/model_fxx/processor_name.c @@ -41,7 +41,7 @@ * your mainboard will not be posted on the AMD Recommended Motherboard Website */ -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 static char *processor_names[]={ /* 0x00 */ "AMD Engineering Sample", /* 0x01-0x03 */ NULL, NULL, NULL, @@ -163,7 +163,7 @@ int init_processor_name(void) char program_string[48]; unsigned int *program_values = (unsigned int *)program_string; -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 /* Find out which CPU brand it is */ EightBitBrandId = cpuid_ebx(0x00000001) & 0xff; BrandId = cpuid_ebx(0x80000001) & 0xffff; @@ -187,7 +187,7 @@ int init_processor_name(void) processor_name_string = "AMD Processor model unknown"; #endif -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 u32 Socket; u32 CmpCap; u32 PwrLmt; @@ -343,7 +343,7 @@ int init_processor_name(void) for (i=0; i<47; i++) { // 48 -1 if(program_string[i] == program_string[i+1]) { switch (program_string[i]) { -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 case 'X': ModelNumber = 22+ NN; break; case 'Y': ModelNumber = 38 + (2*NN); break; case 'Z': @@ -352,7 +352,7 @@ int init_processor_name(void) case 'V': ModelNumber = 9 + NN; break; #endif -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 case 'R': ModelNumber = NN - 1; break; case 'P': ModelNumber = 26 + NN; break; case 'T': ModelNumber = 15 + (CmpCap * 10) + NN; break; diff --git a/src/cpu/amd/model_gx2/vsmsetup.c b/src/cpu/amd/model_gx2/vsmsetup.c index dc1b680836..3c71cdb408 100644 --- a/src/cpu/amd/model_gx2/vsmsetup.c +++ b/src/cpu/amd/model_gx2/vsmsetup.c @@ -271,7 +271,7 @@ void do_vsmbios(void) //rom = 0xfff80000; //rom = 0xfffc0000; /* the VSA starts at the base of rom - 64 */ - rom = ((unsigned long) 0) - (ROM_SIZE + 64*1024); + rom = ((unsigned long) 0) - (CONFIG_ROM_SIZE + 64*1024); buf = (unsigned char *) 0x60000; olen = unrv2b((uint8_t *)rom, buf, &ilen); diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc index 57bfc1211f..c9e538ad93 100644 --- a/src/cpu/amd/model_lx/cache_as_ram.inc +++ b/src/cpu/amd/model_lx/cache_as_ram.inc @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define LX_STACK_BASE DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */ -#define LX_STACK_END LX_STACK_BASE+(DCACHE_RAM_SIZE-1) +#define LX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */ +#define LX_STACK_END LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1) #define LX_NUM_CACHELINES 0x080 /* there are 128lines per way */ #define LX_CACHELINE_SIZE 0x020 /* there are 32bytes per line */ @@ -82,7 +82,7 @@ DCacheSetup: xorl %esi, %esi xorl %ebp, %ebp - /* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + DCACHE_RAM_SIZE for holding stack */ + /* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */ /* remember, there is NO stack yet... */ /* Tell cache we want to fill WAY 0 starting at the top */ @@ -192,7 +192,7 @@ done_cache_as_ram_main: mov string, %ebx ; \ CALLSP(crt_console_tx_string) -# if defined(TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) +# if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) # define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string) # else # define CONSOLE_DEBUG_TX_STRING(string) @@ -333,26 +333,26 @@ crt_console_tx_string: RETSP 9: /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif /* Data */ -#define TTYS0_RBR (TTYS0_BASE+0x00) +#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00) /* Control */ #define TTYS0_TBR TTYS0_RBR -#define TTYS0_IER (TTYS0_BASE+0x01) -#define TTYS0_IIR (TTYS0_BASE+0x02) +#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01) +#define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02) #define TTYS0_FCR TTYS0_IIR -#define TTYS0_LCR (TTYS0_BASE+0x03) -#define TTYS0_MCR (TTYS0_BASE+0x04) +#define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03) +#define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04) #define TTYS0_DLL TTYS0_RBR #define TTYS0_DLM TTYS0_IER /* Status */ -#define TTYS0_LSR (TTYS0_BASE+0x05) -#define TTYS0_MSR (TTYS0_BASE+0x06) -#define TTYS0_SCR (TTYS0_BASE+0x07) +#define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05) +#define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06) +#define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07) mov %al, %ah 10: mov $TTYS0_LSR, %dx diff --git a/src/cpu/amd/model_lx/syspreinit.c b/src/cpu/amd/model_lx/syspreinit.c index 4df30f4b8a..53cd4aa9c9 100644 --- a/src/cpu/amd/model_lx/syspreinit.c +++ b/src/cpu/amd/model_lx/syspreinit.c @@ -39,7 +39,7 @@ void SystemPreInit(void) { /* they want a jump ... */ -#ifndef USE_DCACHE_RAM +#ifndef CONFIG_USE_DCACHE_RAM __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n"); #endif StartTimer1(); diff --git a/src/cpu/amd/model_lx/vsmsetup.c b/src/cpu/amd/model_lx/vsmsetup.c index 9c47a4f6d9..0a749da90a 100644 --- a/src/cpu/amd/model_lx/vsmsetup.c +++ b/src/cpu/amd/model_lx/vsmsetup.c @@ -292,7 +292,7 @@ void do_vsmbios(void) */ //VSA is cat onto the end after LB builds - rom = ((unsigned long)0) - (ROM_SIZE + 36 * 1024); + rom = ((unsigned long)0) - (CONFIG_ROM_SIZE + 36 * 1024); buf = (unsigned char *)VSA2_BUFFER; olen = unrv2b((uint8_t *) rom, buf, &ilen); printk_debug("buf ilen %d olen%d\n", ilen, olen); diff --git a/src/cpu/amd/mtrr/amd_earlymtrr.c b/src/cpu/amd/mtrr/amd_earlymtrr.c index 948d4ac83b..c633c957f0 100644 --- a/src/cpu/amd/mtrr/amd_earlymtrr.c +++ b/src/cpu/amd/mtrr/amd_earlymtrr.c @@ -41,11 +41,11 @@ static void do_amd_early_mtrr_init(const unsigned long *mtrr_msrs) msr.lo = (((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK); wrmsr(TOP_MEM, msr); -#if defined(XIP_ROM_SIZE) +#if defined(CONFIG_XIP_ROM_SIZE) /* enable write through caching so we can do execute in place * on the flash rom. */ - set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK); + set_var_mtrr(1, CONFIG_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK); #endif /* Set the default memory type and enable fixed and variable MTRRs diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index e8e9273868..3d72fe684e 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -180,7 +180,7 @@ void amd_setup_mtrrs(void) /* FIXME we should probably query the cpu for this * but so far this is all any recent AMD cpu has supported. */ - address_bits = CPU_ADDR_BITS; //K8 could be 40, and GH could be 48 + address_bits = CONFIG_CPU_ADDR_BITS; //K8 could be 40, and GH could be 48 /* Now that I have mapped what is memory and what is not * Setup the mtrrs so we can cache the memory. diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index 4d4e11648f..999c51807c 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -114,7 +114,7 @@ u32 get_apicid_base(u32 ioapic_num) if((apicid_base+ioapic_num-1)>0xf) { // We need to enable APIC EXT ID - printk_spew("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n"); + printk_spew("if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n"); enable_apic_ext_id(sysconf.nodes); } diff --git a/src/cpu/amd/socket_AM2/Config.lb b/src/cpu/amd/socket_AM2/Config.lb index de3c04608f..095643bd91 100644 --- a/src/cpu/amd/socket_AM2/Config.lb +++ b/src/cpu/amd/socket_AM2/Config.lb @@ -1,15 +1,15 @@ -uses K8_REV_F_SUPPORT -uses K8_HT_FREQ_1G_SUPPORT -uses DIMM_SUPPORT -uses CPU_SOCKET_TYPE +uses CONFIG_K8_REV_F_SUPPORT +uses CONFIG_K8_HT_FREQ_1G_SUPPORT +uses CONFIG_DIMM_SUPPORT +uses CONFIG_CPU_SOCKET_TYPE config chip.h -default K8_REV_F_SUPPORT=1 +default CONFIG_K8_REV_F_SUPPORT=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 -default DIMM_SUPPORT=0x0004 #DDR2 unbuffered -default CPU_SOCKET_TYPE=0x11 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_DIMM_SUPPORT=0x0004 #DDR2 unbuffered +default CONFIG_CPU_SOCKET_TYPE=0x11 object socket_AM2.o diff --git a/src/cpu/amd/socket_F/Config.lb b/src/cpu/amd/socket_F/Config.lb index 42afda14b8..72f2a1b4cb 100644 --- a/src/cpu/amd/socket_F/Config.lb +++ b/src/cpu/amd/socket_F/Config.lb @@ -1,15 +1,15 @@ -uses K8_REV_F_SUPPORT -uses K8_HT_FREQ_1G_SUPPORT -uses DIMM_SUPPORT -uses CPU_SOCKET_TYPE +uses CONFIG_K8_REV_F_SUPPORT +uses CONFIG_K8_HT_FREQ_1G_SUPPORT +uses CONFIG_DIMM_SUPPORT +uses CONFIG_CPU_SOCKET_TYPE config chip.h -default K8_REV_F_SUPPORT=1 +default CONFIG_K8_REV_F_SUPPORT=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 -default DIMM_SUPPORT=0x0104 #DDR2 and REG -default CPU_SOCKET_TYPE=0x10 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_DIMM_SUPPORT=0x0104 #DDR2 and REG +default CONFIG_CPU_SOCKET_TYPE=0x10 object socket_F.o diff --git a/src/cpu/amd/socket_F_1207/Config.lb b/src/cpu/amd/socket_F_1207/Config.lb index 5777e356d4..5c0147af7e 100644 --- a/src/cpu/amd/socket_F_1207/Config.lb +++ b/src/cpu/amd/socket_F_1207/Config.lb @@ -17,37 +17,37 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -uses PCI_IO_CFG_EXT -uses MMCONF_SUPPORT -uses HT3_SUPPORT -uses EXT_RT_TBL_SUPPORT -uses EXT_CONF_SUPPORT -uses DIMM_SUPPORT -uses CPU_SOCKET_TYPE -uses CBB -uses CDB -uses PCI_BUS_SEGN_BITS -uses CAR_FAM10 +uses CONFIG_PCI_IO_CFG_EXT +uses CONFIG_MMCONF_SUPPORT +uses CONFIG_HT3_SUPPORT +uses CONFIG_EXT_RT_TBL_SUPPORT +uses CONFIG_EXT_CONF_SUPPORT +uses CONFIG_DIMM_SUPPORT +uses CONFIG_CPU_SOCKET_TYPE +uses CONFIG_CBB +uses CONFIG_CDB +uses CONFIG_PCI_BUS_SEGN_BITS +uses CONFIG_CAR_FAM10 config chip.h -default PCI_IO_CFG_EXT=1 +default CONFIG_PCI_IO_CFG_EXT=1 -default HT3_SUPPORT=1 -default EXT_RT_TBL_SUPPORT=0 -default EXT_CONF_SUPPORT=0 -default DIMM_SUPPORT=0x0104 #DDR2 and REG -default CPU_SOCKET_TYPE=0x10 +default CONFIG_HT3_SUPPORT=1 +default CONFIG_EXT_RT_TBL_SUPPORT=0 +default CONFIG_EXT_CONF_SUPPORT=0 +default CONFIG_DIMM_SUPPORT=0x0104 #DDR2 and REG +default CONFIG_CPU_SOCKET_TYPE=0x10 -default CAR_FAM10=1 +default CONFIG_CAR_FAM10=1 -if EXT_RT_TBL_SUPPORT - default CBB=0xff - default CDB=0 +if CONFIG_EXT_RT_TBL_SUPPORT + default CONFIG_CBB=0xff + default CONFIG_CDB=0 end -#default MMCONF_SUPPORT=1 -#default MMCONF_SUPPORT_DEFAULT=1 +#default CONFIG_MMCONF_SUPPORT=1 +#default CONFIG_MMCONF_SUPPORT_DEFAULT=1 object socket_F_1207.o diff --git a/src/cpu/amd/socket_S1G1/Config.lb b/src/cpu/amd/socket_S1G1/Config.lb index 5cdc3bffab..6aa6b5a45b 100644 --- a/src/cpu/amd/socket_S1G1/Config.lb +++ b/src/cpu/amd/socket_S1G1/Config.lb @@ -1,15 +1,15 @@ -uses K8_REV_F_SUPPORT -uses K8_HT_FREQ_1G_SUPPORT -uses DIMM_SUPPORT -uses CPU_SOCKET_TYPE +uses CONFIG_K8_REV_F_SUPPORT +uses CONFIG_K8_HT_FREQ_1G_SUPPORT +uses CONFIG_DIMM_SUPPORT +uses CONFIG_CPU_SOCKET_TYPE config chip.h -default K8_REV_F_SUPPORT=1 +default CONFIG_K8_REV_F_SUPPORT=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 -default DIMM_SUPPORT=0x0204 #DDR2 and REG, S1G1 -default CPU_SOCKET_TYPE=0x12 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_DIMM_SUPPORT=0x0204 #DDR2 and REG, S1G1 +default CONFIG_CPU_SOCKET_TYPE=0x12 object socket_S1G1.o diff --git a/src/cpu/emulation/qemu-x86/northbridge.c b/src/cpu/emulation/qemu-x86/northbridge.c index 34745a0f57..993bffb4b8 100644 --- a/src/cpu/emulation/qemu-x86/northbridge.c +++ b/src/cpu/emulation/qemu-x86/northbridge.c @@ -65,7 +65,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -118,7 +118,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/cpu/intel/model_6ex/Config.lb b/src/cpu/intel/model_6ex/Config.lb index a9c4537372..79ff9b1eec 100644 --- a/src/cpu/intel/model_6ex/Config.lb +++ b/src/cpu/intel/model_6ex/Config.lb @@ -1,5 +1,5 @@ -uses HAVE_MOVNTI -default HAVE_MOVNTI=1 +uses CONFIG_HAVE_MOVNTI +default CONFIG_HAVE_MOVNTI=1 dir /cpu/x86/tsc dir /cpu/x86/mtrr diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 20967eae55..ee175affed 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE -#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE #define post_code(x) intel_chip_post_macro(x) #include <cpu/x86/mtrr.h> @@ -29,7 +29,7 @@ movl %eax, %ebp cache_as_ram: -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 post_code(0x20) @@ -101,18 +101,18 @@ clear_mtrrs: orl $(1 << 30), %eax movl %eax, %cr0 -#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) +#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx - movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx - movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr -#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ /* enable cache */ movl %cr0, %eax diff --git a/src/cpu/intel/model_6ex/cache_as_ram_disable.c b/src/cpu/intel/model_6ex/cache_as_ram_disable.c index 981aac1399..ce508676e5 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram_disable.c +++ b/src/cpu/intel/model_6ex/cache_as_ram_disable.c @@ -27,7 +27,7 @@ void stage1_main(unsigned long bist) { unsigned int cpu_reset = 0; -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 /* Is this a deliberate reset by the bios */ if (bios_reset_detected() && last_boot_normal()) { goto normal_image; @@ -87,10 +87,10 @@ cpu_reset_x: } __asm__ volatile ( - /* set new esp */ /* before _RAMBASE */ + /* set new esp */ /* before CONFIG_RAMBASE */ "subl %0, %%ebp\n\t" "subl %0, %%esp\n\t" - ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE ) + ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE ) ); { diff --git a/src/cpu/intel/model_6fx/Config.lb b/src/cpu/intel/model_6fx/Config.lb index 74f8be6168..7cbd118b99 100644 --- a/src/cpu/intel/model_6fx/Config.lb +++ b/src/cpu/intel/model_6fx/Config.lb @@ -1,5 +1,5 @@ -uses HAVE_MOVNTI -default HAVE_MOVNTI=1 +uses CONFIG_HAVE_MOVNTI +default CONFIG_HAVE_MOVNTI=1 dir /cpu/x86/tsc dir /cpu/x86/mtrr diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index d04274046d..5ce01cbd04 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE -#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE #define post_code(x) intel_chip_post_macro(x) #include <cpu/x86/mtrr.h> @@ -29,7 +29,7 @@ movl %eax, %ebp cache_as_ram: -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 post_code(0x20) @@ -108,18 +108,18 @@ clear_mtrrs: orl $(1 << 30), %eax movl %eax, %cr0 -#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) +#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx - movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx - movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr -#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ /* enable cache */ movl %cr0, %eax diff --git a/src/cpu/intel/model_6fx/cache_as_ram_disable.c b/src/cpu/intel/model_6fx/cache_as_ram_disable.c index 981aac1399..ce508676e5 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram_disable.c +++ b/src/cpu/intel/model_6fx/cache_as_ram_disable.c @@ -27,7 +27,7 @@ void stage1_main(unsigned long bist) { unsigned int cpu_reset = 0; -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 /* Is this a deliberate reset by the bios */ if (bios_reset_detected() && last_boot_normal()) { goto normal_image; @@ -87,10 +87,10 @@ cpu_reset_x: } __asm__ volatile ( - /* set new esp */ /* before _RAMBASE */ + /* set new esp */ /* before CONFIG_RAMBASE */ "subl %0, %%ebp\n\t" "subl %0, %%esp\n\t" - ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE ) + ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE ) ); { diff --git a/src/cpu/intel/model_f0x/Config.lb b/src/cpu/intel/model_f0x/Config.lb index 6afad2ad40..da24e075ba 100644 --- a/src/cpu/intel/model_f0x/Config.lb +++ b/src/cpu/intel/model_f0x/Config.lb @@ -1,5 +1,5 @@ -uses HAVE_MOVNTI -default HAVE_MOVNTI=1 +uses CONFIG_HAVE_MOVNTI +default CONFIG_HAVE_MOVNTI=1 dir /cpu/x86/tsc dir /cpu/x86/mtrr dir /cpu/x86/fpu diff --git a/src/cpu/intel/model_f1x/Config.lb b/src/cpu/intel/model_f1x/Config.lb index b6ae5085e1..4c52a8777e 100644 --- a/src/cpu/intel/model_f1x/Config.lb +++ b/src/cpu/intel/model_f1x/Config.lb @@ -1,5 +1,5 @@ -uses HAVE_MOVNTI -default HAVE_MOVNTI=1 +uses CONFIG_HAVE_MOVNTI +default CONFIG_HAVE_MOVNTI=1 dir /cpu/x86/tsc dir /cpu/x86/mtrr dir /cpu/x86/fpu diff --git a/src/cpu/intel/model_f2x/Config.lb b/src/cpu/intel/model_f2x/Config.lb index 314205f716..e4c64583a3 100644 --- a/src/cpu/intel/model_f2x/Config.lb +++ b/src/cpu/intel/model_f2x/Config.lb @@ -1,5 +1,5 @@ -uses HAVE_MOVNTI -default HAVE_MOVNTI=1 +uses CONFIG_HAVE_MOVNTI +default CONFIG_HAVE_MOVNTI=1 dir /cpu/x86/tsc dir /cpu/x86/mtrr dir /cpu/x86/fpu diff --git a/src/cpu/intel/model_f3x/Config.lb b/src/cpu/intel/model_f3x/Config.lb index 0f80cd853b..8c9f1048c1 100644 --- a/src/cpu/intel/model_f3x/Config.lb +++ b/src/cpu/intel/model_f3x/Config.lb @@ -1,5 +1,5 @@ -uses HAVE_MOVNTI -default HAVE_MOVNTI=1 +uses CONFIG_HAVE_MOVNTI +default CONFIG_HAVE_MOVNTI=1 dir /cpu/x86/tsc dir /cpu/x86/mtrr dir /cpu/x86/fpu diff --git a/src/cpu/intel/model_f4x/Config.lb b/src/cpu/intel/model_f4x/Config.lb index cef79889e5..b6a5d79df9 100644 --- a/src/cpu/intel/model_f4x/Config.lb +++ b/src/cpu/intel/model_f4x/Config.lb @@ -1,5 +1,5 @@ -uses HAVE_MOVNTI -default HAVE_MOVNTI=1 +uses CONFIG_HAVE_MOVNTI +default CONFIG_HAVE_MOVNTI=1 dir /cpu/x86/tsc dir /cpu/x86/mtrr dir /cpu/x86/fpu diff --git a/src/cpu/ppc/mpc74xx/Config.lb b/src/cpu/ppc/mpc74xx/Config.lb index ee65e41f3b..86ce6faa44 100644 --- a/src/cpu/ppc/mpc74xx/Config.lb +++ b/src/cpu/ppc/mpc74xx/Config.lb @@ -1,19 +1,19 @@ ## ## CPU initialization ## -uses _RAMBASE -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_RAMBASE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE ## ## Use cache ram for initial setup ## -default USE_DCACHE_RAM=1 +default CONFIG_USE_DCACHE_RAM=1 ## Set dcache ram above coreboot image -default DCACHE_RAM_BASE=_RAMBASE+0x100000 +default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000 ## Dcache size is 32Kb -default DCACHE_RAM_SIZE=0x8000 +default CONFIG_DCACHE_RAM_SIZE=0x8000 initinclude "FAMILY_INIT" cpu/ppc/mpc74xx/mpc74xx.inc object cache.S diff --git a/src/cpu/ppc/mpc74xx/mpc74xx.inc b/src/cpu/ppc/mpc74xx/mpc74xx.inc index ba2c0018d5..0a3bfe8a09 100644 --- a/src/cpu/ppc/mpc74xx/mpc74xx.inc +++ b/src/cpu/ppc/mpc74xx/mpc74xx.inc @@ -30,7 +30,7 @@ * - enable L1 I/D caches, otherwise performance will be slow * - set up DBATs for the following regions: * - RAM (generally 0x00000000 -> 0x7fffffff) - * - ROM (_ROMBASE -> _ROMBASE + ROM_SIZE) + * - ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE + CONFIG_ROM_SIZE) * - I/O (generally 0xfc000000 -> 0xfdffffff) * - the main purpose for setting up the DBATs is so the I/O region * can be marked cache inhibited/write through @@ -147,7 +147,7 @@ * IBATS * * IBAT0 covers RAM (0 -> 256Mb) - * IBAT1 covers ROM (_ROMBASE -> _ROMBASE+ROM_SIZE) + * IBAT1 covers ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE+CONFIG_ROM_SIZE) */ lis r2, 0@h ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER @@ -156,8 +156,8 @@ mtibatl 0, r2 isync - lis r2, _ROMBASE@h -#if ROM_SIZE > 1048576 + lis r2, CONFIG_ROMBASE@h +#if CONFIG_ROM_SIZE > 1048576 ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER #else ori r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER diff --git a/src/cpu/ppc/ppc4xx/Config.lb b/src/cpu/ppc/ppc4xx/Config.lb index f739495325..0b6f6233bb 100644 --- a/src/cpu/ppc/ppc4xx/Config.lb +++ b/src/cpu/ppc/ppc4xx/Config.lb @@ -1,19 +1,19 @@ ## ## CPU initialization ## -uses _RAMBASE -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_RAMBASE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE ## ## PPC4XX always uses cache ram for initial setup ## -default USE_DCACHE_RAM=1 +default CONFIG_USE_DCACHE_RAM=1 ## Set dcache ram above coreboot image -default DCACHE_RAM_BASE=_RAMBASE+0x100000 +default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000 ## Dcache size is 16Kb -default DCACHE_RAM_SIZE=16384 +default CONFIG_DCACHE_RAM_SIZE=16384 initinclude "FAMILY_INIT" cpu/ppc/ppc4xx/ppc4xx.inc initobject cache.S diff --git a/src/cpu/ppc/ppc4xx/cache.S b/src/cpu/ppc/ppc4xx/cache.S index 3f69b949d2..501be9a174 100644 --- a/src/cpu/ppc/ppc4xx/cache.S +++ b/src/cpu/ppc/ppc4xx/cache.S @@ -57,7 +57,7 @@ invalidate_icache: invalidate_dcache: li r6,0x0000 /* clear GPR 6 */ /* Do loop for # of dcache congruence classes. */ - li r7,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2) + li r7,(CONFIG_DCACHE_RAM_SIZE / CACHELINE_SIZE / 2) /* NOTE: dccci invalidates both */ mtctr r7 /* ways in the D cache */ 1: @@ -79,8 +79,8 @@ flush_dcache: mtdccr r10 /* do loop for # of congruence classes. */ - li r10,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2) - li r11,(DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */ + li r10,(CONFIG_DCACHE_RAM_SIZE / CACHELINE_SIZE / 2) + li r11,(CONFIG_DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */ mtctr r10 li r10,(0xE000-0x10000) /* start at 0xFFFFE000 */ add r11,r10,r11 /* add to get to other side of cache line */ diff --git a/src/cpu/ppc/ppc4xx/pci_domain.c b/src/cpu/ppc/ppc4xx/pci_domain.c index f53446dc88..b0da1f0263 100644 --- a/src/cpu/ppc/ppc4xx/pci_domain.c +++ b/src/cpu/ppc/ppc4xx/pci_domain.c @@ -47,7 +47,7 @@ static void pci_domain_set_resources(device_t dev) { int idx = 3; /* who knows? */ - ram_resource(dev, idx, 0, EMBEDDED_RAM_SIZE>>10); + ram_resource(dev, idx, 0, CONFIG_EMBEDDED_RAM_SIZE>>10); assign_resources(&dev->link[0]); } diff --git a/src/cpu/ppc/ppc4xx/ppc4xx.inc b/src/cpu/ppc/ppc4xx/ppc4xx.inc index e3943d130f..b5833ea4bc 100644 --- a/src/cpu/ppc/ppc4xx/ppc4xx.inc +++ b/src/cpu/ppc/ppc4xx/ppc4xx.inc @@ -94,15 +94,15 @@ isync /* - * Enable dcache region containing DCACHE_RAM_BASE + * Enable dcache region containing CONFIG_DCACHE_RAM_BASE * On reset all regions are set to write-back, so we * just leave them alone. * - * dccr = (1 << (0x1F - (DCACHE_RAM_BASE >> 27)) + * dccr = (1 << (0x1F - (CONFIG_DCACHE_RAM_BASE >> 27)) */ - lis r4, DCACHE_RAM_BASE@ha - ori r4, r4, DCACHE_RAM_BASE@l + lis r4, CONFIG_DCACHE_RAM_BASE@ha + ori r4, r4, CONFIG_DCACHE_RAM_BASE@l srwi r4, r4, 27 subfic r4, r4, 31 li r0, 1 diff --git a/src/cpu/ppc/ppc4xx/sdram.c b/src/cpu/ppc/ppc4xx/sdram.c index 5068f9071f..f7a508b4fd 100644 --- a/src/cpu/ppc/ppc4xx/sdram.c +++ b/src/cpu/ppc/ppc4xx/sdram.c @@ -98,17 +98,17 @@ void memory_init(void) /* TODO: work out why this trashes cache ram */ //mtsdram0(mem_mcopt1, 0x00000000); -#if EMBEDDED_RAM_SIZE==128*1024*1024 +#if CONFIG_EMBEDDED_RAM_SIZE==128*1024*1024 /* TODO */ -#elif EMBEDDED_RAM_SIZE==64*1024*1024 +#elif CONFIG_EMBEDDED_RAM_SIZE==64*1024*1024 set_sdram0(mem_sdtr1, TR); set_sdram0(mem_mb0cf, B0CR); set_sdram0(mem_rtr, RTR); set_sdram0(mem_ecccf, ECCCF); set_sdram0(mem_pmit, PMIT); -#elif EMBEDDED_RAM_SIZE==32*1024*1024 +#elif CONFIG_EMBEDDED_RAM_SIZE==32*1024*1024 /* TODO */ -#elif EMBEDDED_RAM_SIZE==16*1024*1024 +#elif CONFIG_EMBEDDED_RAM_SIZE==16*1024*1024 /* TODO */ #endif diff --git a/src/cpu/ppc/ppc7xx/Config.lb b/src/cpu/ppc/ppc7xx/Config.lb index 521045b1bc..a04a777a06 100644 --- a/src/cpu/ppc/ppc7xx/Config.lb +++ b/src/cpu/ppc/ppc7xx/Config.lb @@ -1,19 +1,19 @@ ## ## CPU initialization ## -uses _RAMBASE -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_RAMBASE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE ## ## PPC7XX always uses cache ram for initial setup ## -default USE_DCACHE_RAM=1 +default CONFIG_USE_DCACHE_RAM=1 ## Set dcache ram above coreboot image -default DCACHE_RAM_BASE=_RAMBASE+0x100000 +default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000 ## Dcache size is 16Kb -default DCACHE_RAM_SIZE=16384 +default CONFIG_DCACHE_RAM_SIZE=16384 initinclude "FAMILY_INIT" cpu/ppc/ppc7xx/ppc7xx.inc diff --git a/src/cpu/ppc/ppc7xx/ppc7xx.inc b/src/cpu/ppc/ppc7xx/ppc7xx.inc index bd599f324e..4f8ab86da3 100644 --- a/src/cpu/ppc/ppc7xx/ppc7xx.inc +++ b/src/cpu/ppc/ppc7xx/ppc7xx.inc @@ -30,7 +30,7 @@ * - enable L1 I/D caches, otherwise performance will be slow * - set up DBATs for the following regions: * - RAM (generally 0x00000000 -> 0x7fffffff) - * - ROM (_ROMBASE -> _ROMBASE + ROM_SIZE) + * - ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE + CONFIG_ROM_SIZE) * - I/O (generally 0xfc000000 -> 0xfdffffff) * - the main purpose for setting up the DBATs is so the I/O region * can be marked cache inhibited/write through @@ -113,7 +113,7 @@ * IBATS * * IBAT0 covers RAM (0 -> 256Mb) - * IBAT1 covers ROM (_ROMBASE -> _ROMBASE+ROM_SIZE) + * IBAT1 covers ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE+CONFIG_ROM_SIZE) */ lis r2, 0@h ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER @@ -122,8 +122,8 @@ mtibatl 0, r2 isync - lis r2, _ROMBASE@h -#if ROM_SIZE > 1048576 + lis r2, CONFIG_ROMBASE@h +#if CONFIG_ROM_SIZE > 1048576 ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER #else ori r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER @@ -161,9 +161,9 @@ * Initialize data cache blocks * (assumes cache block size of 32 bytes) */ - lis r1, DCACHE_RAM_BASE@h - ori r1, r1, DCACHE_RAM_BASE@l - li r3, (DCACHE_RAM_SIZE / 32) + lis r1, CONFIG_DCACHE_RAM_BASE@h + ori r1, r1, CONFIG_DCACHE_RAM_BASE@l + li r3, (CONFIG_DCACHE_RAM_SIZE / 32) mtctr r3 0: dcbz r0, r1 addi r1, r1, 32 diff --git a/src/cpu/ppc/ppc970/Config.lb b/src/cpu/ppc/ppc970/Config.lb index 60da7f2b71..4eebe71bb7 100644 --- a/src/cpu/ppc/ppc970/Config.lb +++ b/src/cpu/ppc/ppc970/Config.lb @@ -1,15 +1,15 @@ ## ## CPU initialization ## -uses _RAMBASE -uses USE_DCACHE_RAM +uses CONFIG_RAMBASE +uses CONFIG_USE_DCACHE_RAM ## ## Assumes RAM already initialiazed ## This is true for the Apache board, but may ## not be for other 970 systems. ## -default USE_DCACHE_RAM=0 +default CONFIG_USE_DCACHE_RAM=0 initinclude "FAMILY_INIT" cpu/ppc/ppc970/ppc970.inc diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 3bd4046649..693bce36dd 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -25,8 +25,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define CacheSize DCACHE_RAM_SIZE -#define CacheBase DCACHE_RAM_BASE +#define CacheSize CONFIG_DCACHE_RAM_SIZE +#define CacheBase CONFIG_DCACHE_RAM_BASE #include <cpu/x86/mtrr.h> @@ -82,13 +82,13 @@ clear_fixed_var_mtrr_out: /* MTRRPhysBase */ movl $0x202, %ecx xorl %edx, %edx - movl $(XIP_ROM_BASE|MTRR_TYPE_WRBACK),%eax + movl $(CONFIG_XIP_ROM_BASE|MTRR_TYPE_WRBACK),%eax wrmsr /* MTRRPhysMask */ movl $0x203, %ecx movl $0x0000000f,%edx - movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr @@ -119,9 +119,9 @@ clear_fixed_var_mtrr_out: xorl $0x5c5c5c5c,%eax rep stosl - movl XIP_ROM_BASE, %esi + movl CONFIG_XIP_ROM_BASE, %esi movl %esi, %edi - movl $(XIP_ROM_SIZE>>2), %ecx + movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx rep lodsl /* The key point of this CAR code is C7 cache does not turn into diff --git a/src/cpu/via/car/cache_as_ram_post.c b/src/cpu/via/car/cache_as_ram_post.c index 9058727bc6..3c5c5e486b 100644 --- a/src/cpu/via/car/cache_as_ram_post.c +++ b/src/cpu/via/car/cache_as_ram_post.c @@ -78,16 +78,16 @@ and in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable.*/ "movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax\n\t" "wrmsr\n\t" - /*jasonzhao@viatech.com.cn add this 2008-11-27, cache XIP_ROM_BASE-SIZE to speedup the coreboot code*/ + /*jasonzhao@viatech.com.cn add this 2008-11-27, cache CONFIG_XIP_ROM_BASE-SIZE to speedup the coreboot code*/ "movl $0x206, %ecx\n\t" "xorl %edx, %edx\n\t" - "movl $XIP_ROM_BASE,%eax\n\t" + "movl $CONFIG_XIP_ROM_BASE,%eax\n\t" "orl $(0 | 6), %eax\n\t" "wrmsr\n\t" "movl $0x207, %ecx\n\t" "xorl %edx, %edx\n\t" - "movl $XIP_ROM_SIZE,%eax\n\t" + "movl $CONFIG_XIP_ROM_SIZE,%eax\n\t" "decl %eax\n\t" "notl %eax\n\t" "orl $(0 | 0x800), %eax\n\t" diff --git a/src/cpu/x86/16bit/reset16.lds b/src/cpu/x86/16bit/reset16.lds index b451deb133..929740bd4c 100644 --- a/src/cpu/x86/16bit/reset16.lds +++ b/src/cpu/x86/16bit/reset16.lds @@ -5,7 +5,7 @@ SECTIONS { /* Trigger an error if I have an unuseable start address */ - _bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please decrease ROM_IMAGE_SIZE"); + _bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please decrease CONFIG_ROM_IMAGE_SIZE"); _ROMTOP = 0xfffffff0; . = _ROMTOP; .reset . : { diff --git a/src/cpu/x86/32bit/reset32.lds b/src/cpu/x86/32bit/reset32.lds index fa6db86b1a..1afb215c41 100644 --- a/src/cpu/x86/32bit/reset32.lds +++ b/src/cpu/x86/32bit/reset32.lds @@ -4,7 +4,7 @@ */ SECTIONS { - _ROMTOP = _ROMBASE + ROM_IMAGE_SIZE - 0x10; + _ROMTOP = CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10; . = _ROMTOP; .reset (.): { *(.reset) diff --git a/src/cpu/x86/car/cache_as_ram.inc b/src/cpu/x86/car/cache_as_ram.inc index 87ad13d718..4f1ae86af0 100644 --- a/src/cpu/x86/car/cache_as_ram.inc +++ b/src/cpu/x86/car/cache_as_ram.inc @@ -27,7 +27,7 @@ /* disable HyperThreading is done by eswar*/ /* other's is the same as AMD except remove amd specific msr */ -#define CacheSize DCACHE_RAM_SIZE +#define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) #include <cpu/x86/mtrr.h> @@ -37,7 +37,7 @@ CacheAsRam: /* hope we can skip the double set for normal part */ -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 // Check whether the processor has HT capability movl $01, %eax @@ -197,29 +197,29 @@ clear_fixed_var_mtrr_out: orl $(0x1<<30),%eax movl %eax, %cr0 -#endif /* USE_FALLBACK_IMAGE == 1*/ +#endif /* CONFIG_USE_FALLBACK_IMAGE == 1*/ -#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) +#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* enable write base caching so we can do execute in place * on the flash rom. */ movl $0x202, %ecx xorl %edx, %edx - movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax wrmsr movl $0x203, %ecx movl $0x0000000f, %edx - movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr -#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ /* enable cache */ movl %cr0, %eax andl $0x9fffffff,%eax movl %eax, %cr0 -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 /* Read the range with lodsl*/ movl $CacheBase, %esi @@ -277,7 +277,7 @@ clear_fixed_var_mtrr_out: .xout1x: #endif -#endif /*USE_FALLBACK_IMAGE == 1*/ +#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/ movl $(CacheBase+CacheSize-4), %eax @@ -314,7 +314,7 @@ var_mtrr_msr: .long 0x20C, 0x20D, 0x20E, 0x20F .long 0x000 /* NULL, end of table */ -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 .align 0x1000 .code16 .global LogicalAP_SIPI @@ -344,5 +344,5 @@ Halt_LogicalAP: hlt jmp Halt_LogicalAP .code32 -#endif /*USE_FALLBACK_IMAGE == 1*/ +#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/ .CacheAsRam_out: diff --git a/src/cpu/x86/car/cache_as_ram_post.c b/src/cpu/x86/car/cache_as_ram_post.c index a0b6b17851..f78fb03675 100644 --- a/src/cpu/x86/car/cache_as_ram_post.c +++ b/src/cpu/x86/car/cache_as_ram_post.c @@ -16,7 +16,7 @@ "xorl %edx, %edx\n\t" "xorl %eax, %eax\n\t" "wrmsr\n\t" -#if DCACHE_RAM_SIZE > 0x8000 +#if CONFIG_DCACHE_RAM_SIZE > 0x8000 "movl $0x268, %ecx\n\t" /* fix4k_c0000*/ "wrmsr\n\t" #endif diff --git a/src/cpu/x86/car/copy_and_run.c b/src/cpu/x86/car/copy_and_run.c index 30b3b7a2f5..7ff63c5e0c 100644 --- a/src/cpu/x86/car/copy_and_run.c +++ b/src/cpu/x86/car/copy_and_run.c @@ -10,7 +10,7 @@ static void copy_and_run(unsigned cpu_reset) if (cpu_reset == 1) cpu_reset = -1; else cpu_reset = 0; -# if USE_FALLBACK_IMAGE == 1 +# if CONFIG_USE_FALLBACK_IMAGE == 1 cbfs_and_run_core("fallback/coreboot_ram", cpu_reset); # else cbfs_and_run_core("normal/coreboot_ram", cpu_reset); diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index a7949f0b9c..4f910d0caf 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -1,6 +1,6 @@ /* 2005.12 yhlu add coreboot_ram cross the vga font buffer handling - 2005.12 yhlu add _RAMBASE above 1M support for SMP + 2005.12 yhlu add CONFIG_RAMBASE above 1M support for SMP 2008.05 stepan add support for going back to sipi wait state */ @@ -17,7 +17,7 @@ #if CONFIG_SMP == 1 -#if _RAMBASE >= 0x100000 +#if CONFIG_RAMBASE >= 0x100000 /* This is a lot more paranoid now, since Linux can NOT handle * being told there is a CPU when none exists. So any errors * will return 0, meaning no CPU. @@ -31,7 +31,7 @@ static unsigned long get_valid_start_eip(unsigned long orig_start_eip) } #endif -#if HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME == 1 char *lowmem_backup; char *lowmem_backup_ptr; int lowmem_backup_size; @@ -39,7 +39,7 @@ int lowmem_backup_size; static void copy_secondary_start_to_1m_below(void) { -#if _RAMBASE >= 0x100000 +#if CONFIG_RAMBASE >= 0x100000 extern char _secondary_start[]; extern char _secondary_start_end[]; unsigned long code_size; @@ -51,7 +51,7 @@ static void copy_secondary_start_to_1m_below(void) start_eip = get_valid_start_eip((unsigned long)_secondary_start); code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start; -#if HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME == 1 /* need to save it for RAM resume */ lowmem_backup_size = code_size; lowmem_backup = malloc(code_size); @@ -137,7 +137,7 @@ static int lapic_start_cpu(unsigned long apicid) return 0; } -#if _RAMBASE >= 0x100000 +#if CONFIG_RAMBASE >= 0x100000 start_eip = get_valid_start_eip((unsigned long)_secondary_start); #else start_eip = (unsigned long)_secondary_start; @@ -246,14 +246,14 @@ int start_cpu(device_t cpu) index = ++last_cpu_index; /* Find end of the new processors stack */ -#if (CONFIG_LB_MEM_TOPK>1024) && (_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1)) +#if (CONFIG_LB_MEM_TOPK>1024) && (CONFIG_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1)) if(index<1) { // only keep bsp on low - stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info); + stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); } else { // for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu - stack_end = 0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS - (STACK_SIZE*index); -#if (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10) - #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS)\n" + stack_end = 0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS - (CONFIG_STACK_SIZE*index); +#if (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10) + #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS)\n" #endif if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) { printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %luK\n", stack_end>>10); @@ -262,7 +262,7 @@ int start_cpu(device_t cpu) stack_end -= sizeof(struct cpu_info); } #else - stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info); + stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); #endif @@ -363,13 +363,13 @@ void stop_this_cpu(void) void secondary_cpu_init(void) { atomic_inc(&active_cpus); -#if SERIAL_CPU_INIT == 1 +#if CONFIG_SERIAL_CPU_INIT == 1 #if CONFIG_MAX_CPUS>2 spin_lock(&start_cpu_lock); #endif #endif cpu_initialize(); -#if SERIAL_CPU_INIT == 1 +#if CONFIG_SERIAL_CPU_INIT == 1 #if CONFIG_MAX_CPUS>2 spin_unlock(&start_cpu_lock); #endif @@ -389,7 +389,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) if (cpu->path.type != DEVICE_PATH_APIC) { continue; } - #if SERIAL_CPU_INIT == 0 + #if CONFIG_SERIAL_CPU_INIT == 0 if(cpu==bsp_cpu) { continue; } @@ -408,7 +408,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) printk_err("CPU 0x%02x would not start!\n", cpu->path.apic.apic_id); } -#if SERIAL_CPU_INIT == 1 +#if CONFIG_SERIAL_CPU_INIT == 1 #if CONFIG_MAX_CPUS>2 udelay(10); #endif @@ -448,13 +448,13 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) #define initialize_other_cpus(root) do {} while(0) #endif /* CONFIG_SMP */ -#if WAIT_BEFORE_CPUS_INIT==0 +#if CONFIG_WAIT_BEFORE_CPUS_INIT==0 #define cpus_ready_for_init() do {} while(0) #else void cpus_ready_for_init(void); #endif -#if HAVE_SMI_HANDLER +#if CONFIG_HAVE_SMI_HANDLER void smm_init(void); #endif @@ -486,14 +486,14 @@ void initialize_cpus(struct bus *cpu_bus) copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init #endif -#if HAVE_SMI_HANDLER +#if CONFIG_HAVE_SMI_HANDLER smm_init(); #endif cpus_ready_for_init(); #if CONFIG_SMP == 1 - #if SERIAL_CPU_INIT == 0 + #if CONFIG_SERIAL_CPU_INIT == 0 /* start all aps at first, so we can init ECC all together */ start_other_cpus(cpu_bus, info->cpu); #endif @@ -503,7 +503,7 @@ void initialize_cpus(struct bus *cpu_bus) cpu_initialize(); #if CONFIG_SMP == 1 - #if SERIAL_CPU_INIT == 1 + #if CONFIG_SERIAL_CPU_INIT == 1 start_other_cpus(cpu_bus, info->cpu); #endif diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index d035efef96..cff99b8964 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -4,22 +4,22 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> -/* Validate XIP_ROM_SIZE and XIP_ROM_BASE */ -#if defined(XIP_ROM_SIZE) && !defined(XIP_ROM_BASE) -# error "XIP_ROM_SIZE without XIP_ROM_BASE" +/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */ +#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE) +# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE" #endif -#if defined(XIP_ROM_BASE) && !defined(XIP_ROM_SIZE) -# error "XIP_ROM_BASE without XIP_ROM_SIZE" +#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE) +# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE" #endif #if !defined(CONFIG_LB_MEM_TOPK) # error "CONFIG_LB_MEM_TOPK not defined" #endif -#if defined(XIP_ROM_SIZE) && ((XIP_ROM_SIZE & (XIP_ROM_SIZE -1)) != 0) -# error "XIP_ROM_SIZE is not a power of 2" +#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0) +# error "CONFIG_XIP_ROM_SIZE is not a power of 2" #endif -#if defined(XIP_ROM_SIZE) && ((XIP_ROM_BASE % XIP_ROM_SIZE) != 0) -# error "XIP_ROM_BASE is not a multiple of XIP_ROM_SIZE" +#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0) +# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE" #endif #if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0 @@ -48,7 +48,7 @@ static void set_var_mtrr( basem.hi = 0; wrmsr(MTRRphysBase_MSR(reg), basem); maskm.lo = ~(size - 1) | 0x800; - maskm.hi = (1<<(CPU_ADDR_BITS-32))-1; + maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1; wrmsr(MTRRphysMask_MSR(reg), maskm); } @@ -59,9 +59,9 @@ static void set_var_mtrr_x( /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ msr_t basem, maskm; basem.lo = (base_lo & 0xfffff000) | type; - basem.hi = base_hi & ((1<<(CPU_ADDR_BITS-32))-1); + basem.hi = base_hi & ((1<<(CONFIG_CPU_ADDR_BITS-32))-1); wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.hi = (1<<(CPU_ADDR_BITS-32))-1; + maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1; if(size_lo) { maskm.lo = ~(size_lo - 1) | 0x800; } else { @@ -99,11 +99,11 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs) wrmsr(msr_nr, msr); } -#if defined(XIP_ROM_SIZE) +#if defined(CONFIG_XIP_ROM_SIZE) /* enable write through caching so we can do execute in place * on the flash rom. */ - set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK); + set_var_mtrr(1, CONFIG_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK); #endif /* Set the default memory type and enable fixed and variable MTRRs diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 7c1699a382..95c2ad726c 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -54,7 +54,7 @@ void *map_2M_page(unsigned long page) struct pde pdp[512]; } __attribute__ ((packed)); -#if (CONFIG_LB_MEM_TOPK>1024) && (_RAMBASE<0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1)) +#if (CONFIG_LB_MEM_TOPK>1024) && (CONFIG_RAMBASE<0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1)) /* pgtbl is too big, so use last one 1M before CONFIG_LB_MEM_TOP, otherwise for 8 way dual core with vga support will push stack and heap cross 0xa0000, and that region need to be used as vga font buffer. Please make sure set CONFIG_LB_MEM_TOPK=2048 in MB Config diff --git a/src/cpu/x86/smm/Config.lb b/src/cpu/x86/smm/Config.lb index 652cb2de7f..355693ba96 100644 --- a/src/cpu/x86/smm/Config.lb +++ b/src/cpu/x86/smm/Config.lb @@ -18,9 +18,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_SMI_HANDLER +uses CONFIG_HAVE_SMI_HANDLER -if HAVE_SMI_HANDLER +if CONFIG_HAVE_SMI_HANDLER object smmrelocate.S smmobject smmhandler.S @@ -34,8 +34,8 @@ if HAVE_SMI_HANDLER makerule smm depends "smm.o $(TOP)/src/cpu/x86/smm/smm.ld ldoptions" action "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o smm.elf -T $(TOP)/src/cpu/x86/smm/smm.ld smm.o" - action "$(CROSS_COMPILE)nm -n smm.elf | sort > smm.map" - action "$(OBJCOPY) -O binary smm.elf smm" + action "$(CONFIG_CROSS_COMPILE)nm -n smm.elf | sort > smm.map" + action "$(CONFIG_OBJCOPY) -O binary smm.elf smm" end makerule smm_bin.c diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 858cf59bdf..96eb589556 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -89,7 +89,7 @@ static inline __attribute__((always_inline)) unsigned long nodeid(void) static int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } static void uart_wait_to_tx_byte(void) @@ -100,14 +100,14 @@ static void uart_wait_to_tx_byte(void) static void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } static void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -169,7 +169,7 @@ void smi_handler(u32 smm_revision) node=nodeid(); #ifdef DEBUG_SMI - console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; + console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; #else console_loglevel = 1; #endif diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 2a7bfc23c7..136f5630a1 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -140,7 +140,7 @@ smm_relocate: /* End of hardware specific section. */ #ifdef DEBUG_SMM_RELOCATION /* print [SMM-x] so we can determine if CPUx went to SMM */ - movw $TTYS0_BASE, %dx + movw $CONFIG_TTYS0_BASE, %dx mov $'[', %al outb %al, %dx mov $'S', %al diff --git a/src/cpu/x86/tsc/Config.lb b/src/cpu/x86/tsc/Config.lb index 72905eb5bb..21aa9a4f0f 100644 --- a/src/cpu/x86/tsc/Config.lb +++ b/src/cpu/x86/tsc/Config.lb @@ -1,9 +1,9 @@ uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0 if CONFIG_UDELAY_TSC - default HAVE_INIT_TIMER=1 + default CONFIG_HAVE_INIT_TIMER=1 object delay_tsc.o end diff --git a/src/devices/device_util.c b/src/devices/device_util.c index aa23a2b34c..c5a2f6406f 100644 --- a/src/devices/device_util.c +++ b/src/devices/device_util.c @@ -163,7 +163,7 @@ const char *dev_path(device_t dev) memcpy(buffer, "Root Device", 12); break; case DEVICE_PATH_PCI: -#if PCI_BUS_SEGN_BITS +#if CONFIG_PCI_BUS_SEGN_BITS sprintf(buffer, "PCI: %04x:%02x:%02x.%01x", dev->bus->secondary>>8, dev->bus->secondary & 0xff, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); @@ -461,7 +461,7 @@ void report_resource_stored(device_t dev, struct resource *resource, const char end = resource_end(resource); buf[0] = '\0'; if (resource->flags & IORESOURCE_PCI_BRIDGE) { -#if PCI_BUS_SEGN_BITS +#if CONFIG_PCI_BUS_SEGN_BITS sprintf(buf, "bus %04x:%02x ", dev->bus->secondary>>8, dev->link[0].secondary & 0xff); #else sprintf(buf, "bus %02x ", dev->link[0].secondary); @@ -662,7 +662,7 @@ void show_one_resource(int debug_level, struct device *dev, buf[0] = '\0'; /* if (resource->flags & IORESOURCE_BRIDGE) { -#if PCI_BUS_SEGN_BITS +#if CONFIG_PCI_BUS_SEGN_BITS sprintf(buf, "bus %04x:%02x ", dev->bus->secondary >> 8, dev->link[0].secondary & 0xff); #else diff --git a/src/devices/hypertransport.c b/src/devices/hypertransport.c index 81706166aa..5fb35ce88f 100644 --- a/src/devices/hypertransport.c +++ b/src/devices/hypertransport.c @@ -103,8 +103,8 @@ static unsigned ht_read_freq_cap(device_t dev, unsigned pos) } /* AMD K8 Unsupported 1Ghz? */ if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) { -#if K8_HT_FREQ_1G_SUPPORT == 1 - #if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1 + #if CONFIG_K8_REV_F_SUPPORT == 0 if (is_cpu_pre_e0()) { // only e0 later suupport 1GHz HT freq_cap &= ~(1 << HT_FREQ_1000Mhz); } @@ -326,14 +326,14 @@ static void ht_collapse_early_enumeration(struct bus *bus, unsigned offset_uniti } while((ctrl & (1 << 5)) == 0); //actually, only for one HT device HT chain, and unitid is 0 -#if HT_CHAIN_UNITID_BASE == 0 +#if CONFIG_HT_CHAIN_UNITID_BASE == 0 if(offset_unitid) { return; } #endif /* Check if is already collapsed */ - if((!offset_unitid)|| (offset_unitid && (!((HT_CHAIN_END_UNITID_BASE == 0) && (HT_CHAIN_END_UNITID_BASE <HT_CHAIN_UNITID_BASE))))) { + if((!offset_unitid)|| (offset_unitid && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE <CONFIG_HT_CHAIN_UNITID_BASE))))) { struct device dummy; uint32_t id; dummy.bus = bus; @@ -381,17 +381,17 @@ static void ht_collapse_early_enumeration(struct bus *bus, unsigned offset_uniti unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unitid_base, unsigned offset_unitid) { - //even HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link + //even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link unsigned next_unitid, last_unitid; device_t old_devices, dev, func; - unsigned min_unitid = (offset_unitid) ? HT_CHAIN_UNITID_BASE:1; + unsigned min_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE:1; struct ht_link prev; device_t last_func = 0; int ht_dev_num = 0; unsigned max_unitid; -#if HT_CHAIN_END_UNITID_BASE != 0x20 - //let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE unsigned real_last_unitid; uint8_t real_last_pos; device_t real_last_dev; @@ -483,11 +483,11 @@ unsigned int hypertransport_scan_chain(struct bus *bus, flags &= ~0x1f; /* mask out base Unit ID */ count = (flags >> 5) & 0x1f; /* get unit count */ -#if HT_CHAIN_END_UNITID_BASE != 0x20 +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if(offset_unitid) { if(next_unitid > (max_devfn>>3)) { // max_devfn will be (0x17<<3)|7 or (0x1f<<3)|7 if(!end_used) { - next_unitid = HT_CHAIN_END_UNITID_BASE; + next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; } else { goto end_of_chain; @@ -519,7 +519,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, ht_unitid_base[ht_dev_num] = next_unitid; ht_dev_num++; -#if HT_CHAIN_END_UNITID_BASE != 0x20 +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if (offset_unitid) { real_last_pos = pos; real_last_unitid = next_unitid; @@ -550,25 +550,25 @@ unsigned int hypertransport_scan_chain(struct bus *bus, } #endif -#if HT_CHAIN_END_UNITID_BASE != 0x20 - if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used) { +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { uint16_t flags; int i; device_t last_func = 0; flags = pci_read_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; - flags |= HT_CHAIN_END_UNITID_BASE & 0x1f; + flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; pci_write_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS, flags); for(func = real_last_dev; func; func = func->sibling) { - func->path.pci.devfn -= ((real_last_unitid - HT_CHAIN_END_UNITID_BASE) << 3); + func->path.pci.devfn -= ((real_last_unitid - CONFIG_HT_CHAIN_END_UNITID_BASE) << 3); last_func = func; } - ht_unitid_base[ht_dev_num-1] = HT_CHAIN_END_UNITID_BASE; // update last one + ht_unitid_base[ht_dev_num-1] = CONFIG_HT_CHAIN_END_UNITID_BASE; // update last one printk_debug(" unitid: %04x --> %04x\n", - real_last_unitid, HT_CHAIN_END_UNITID_BASE); + real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE); } #endif diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index 322463466d..2531bfdd5c 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -598,11 +598,11 @@ void pci_dev_enable_resources(struct device *dev) if (dev->on_mainboard && ops && ops->set_subsystem) { printk_debug("%s subsystem <- %02x/%02x\n", dev_path(dev), - MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, - MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); + CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, + CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); ops->set_subsystem(dev, - MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, - MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); + CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, + CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); } command = pci_read_config16(dev, PCI_COMMAND); command |= dev->command; @@ -1034,7 +1034,7 @@ unsigned int pci_scan_bus(struct bus *bus, device_t old_devices; device_t child; -#if PCI_BUS_SEGN_BITS +#if CONFIG_PCI_BUS_SEGN_BITS printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n", bus->secondary >> 8, bus->secondary & 0xff); #else printk_debug("PCI: pci_scan_bus for bus %02x\n", bus->secondary); diff --git a/src/devices/pci_ops.c b/src/devices/pci_ops.c index ed984f89bd..ed07564f61 100644 --- a/src/devices/pci_ops.c +++ b/src/devices/pci_ops.c @@ -86,7 +86,7 @@ void pci_write_config32(device_t dev, unsigned where, uint32_t val) ops_pci_bus(pbus)->write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT uint8_t pci_mmio_read_config8(device_t dev, unsigned where) { struct bus *pbus = get_pbus(dev); diff --git a/src/drivers/generic/debug/debug_dev.c b/src/drivers/generic/debug/debug_dev.c index 94ff870fee..77c30edbf9 100644 --- a/src/drivers/generic/debug/debug_dev.c +++ b/src/drivers/generic/debug/debug_dev.c @@ -238,7 +238,7 @@ static void debug_init(device_t dev) switch(dev->path.pnp.device) { case 0: parent = dev->bus->dev; - printk_debug("DEBUG: %s", dev_path(parent)); + printk_debug("CONFIG_DEBUG: %s", dev_path(parent)); if(parent->chip_ops && parent->chip_ops->name) { printk_debug(": %s\n", parent->chip_ops->name); } else { diff --git a/src/drivers/i2c/adm1026/adm1026.c b/src/drivers/i2c/adm1026/adm1026.c index 9869100823..5f9e4bd9c0 100644 --- a/src/drivers/i2c/adm1026/adm1026.c +++ b/src/drivers/i2c/adm1026/adm1026.c @@ -17,7 +17,7 @@ #define CFG1_THERM_HOT 0x10 #define CFT1_DAC_AFC 0x20 #define CFG1_PWM_AFC 0x40 -#define CFG1_RESET 0x80 +#define CFG1CONFIG_RESET 0x80 #define ADM1026_REG_CONFIG2 0x01 #define ADM1026_REG_CONFIG3 0x07 @@ -40,7 +40,7 @@ static void adm1026_enable_monitoring(device_t dev) int result; result = smbus_read_byte(dev, ADM1026_REG_CONFIG1); - result = (result | CFG1_MONITOR) & ~(CFG1_INT_CLEAR | CFG1_RESET); + result = (result | CFG1_MONITOR) & ~(CFG1_INT_CLEAR | CFG1CONFIG_RESET); result = smbus_write_byte(dev, ADM1026_REG_CONFIG1, result); result = smbus_read_byte(dev, ADM1026_REG_CONFIG1); diff --git a/src/drivers/pci/onboard/onboard.c b/src/drivers/pci/onboard/onboard.c index 17e0a1335a..58e6816f23 100644 --- a/src/drivers/pci/onboard/onboard.c +++ b/src/drivers/pci/onboard/onboard.c @@ -23,7 +23,7 @@ * 2. Reduce the size of your normal (or fallback) image, by adding the * following lines to your target Config.lb, after romimage "normal" * # 48K for SCSI FW or ATI ROM - * option ROM_SIZE = 512*1024-48*1024 + * option CONFIG_ROM_SIZE = 512*1024-48*1024 * 3. Create your vgabios.bin, for example using awardeco and put it in the * directory of your target Config.lb. You can also read an option rom from * a running system, but this is unreliable, as some option roms are changed diff --git a/src/include/assert.h b/src/include/assert.h index 4692ed0744..d34d557e06 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -23,7 +23,7 @@ // ROMCC doesn't support __FILE__ or __LINE__ :^{ -#if DEBUG +#if CONFIG_DEBUG #ifdef __ROMCC__ #define ASSERT(x) { if (!(x)) die("ASSERT failure!\r\n"); } #else @@ -35,7 +35,7 @@ } \ } #endif // __ROMCC__ -#else // !DEBUG +#else // !CONFIG_DEBUG #define ASSERT(x) { } #endif diff --git a/src/include/console/console.h b/src/include/console/console.h index ae2810c7b1..b4e8e0911b 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -39,39 +39,39 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, #define printk_debug(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg) #define printk_spew(fmt, arg...) do_printk(BIOS_SPEW ,fmt, ##arg) -#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_EMERG +#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_EMERG #undef printk_emerg #define printk_emerg(fmt, arg...) do {} while(0) #endif -#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ALERT +#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ALERT #undef printk_alert #define printk_alert(fmt, arg...) do {} while(0) #endif -#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_CRIT +#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_CRIT #undef printk_crit #define printk_crit(fmt, arg...) do {} while(0) #endif -#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ERR +#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ERR #undef printk_err #define printk_err(fmt, arg...) do {} while(0) #endif -#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_WARNING +#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_WARNING #undef printk_warning #define printk_warning(fmt, arg...) do {} while(0) #endif -#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_NOTICE +#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_NOTICE #undef printk_notice #define printk_notice(fmt, arg...) do {} while(0) #endif -#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_INFO +#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_INFO #undef printk_info #define printk_info(fmt, arg...) do {} while(0) #endif -#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_DEBUG +#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_DEBUG #undef printk_debug #define printk_debug(fmt, arg...) do {} while(0) #endif -#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_SPEW +#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_SPEW #undef printk_spew #define printk_spew(fmt, arg...) do {} while(0) #endif diff --git a/src/include/console/loglevel.h b/src/include/console/loglevel.h index 8978dbec15..a765df2b64 100644 --- a/src/include/console/loglevel.h +++ b/src/include/console/loglevel.h @@ -3,19 +3,19 @@ /* Safe for inclusion in assembly */ -#ifndef MAXIMUM_CONSOLE_LOGLEVEL -#define MAXIMUM_CONSOLE_LOGLEVEL 8 +#ifndef CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +#define CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 8 #endif -#ifndef DEFAULT_CONSOLE_LOGLEVEL -#define DEFAULT_CONSOLE_LOGLEVEL 8 /* anything MORE serious than BIOS_SPEW */ +#ifndef CONFIG_DEFAULT_CONSOLE_LOGLEVEL +#define CONFIG_DEFAULT_CONSOLE_LOGLEVEL 8 /* anything MORE serious than BIOS_SPEW */ #endif #ifndef ASM_CONSOLE_LOGLEVEL -#if (DEFAULT_CONSOLE_LOGLEVEL <= MAXIMUM_CONSOLE_LOGLEVEL) -#define ASM_CONSOLE_LOGLEVEL DEFAULT_CONSOLE_LOGLEVEL +#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL <= CONFIG_MAXIMUM_CONSOLE_LOGLEVEL) +#define ASM_CONSOLE_LOGLEVEL CONFIG_DEFAULT_CONSOLE_LOGLEVEL #else -#define ASM_CONSOLE_LOGLEVEL MAXIMUM_CONSOLE_LOGLEVEL +#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL #endif #endif diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h index ca6d69d7a0..c36f35304b 100644 --- a/src/include/cpu/amd/model_fxx_rev.h +++ b/src/include/cpu/amd/model_fxx_rev.h @@ -1,6 +1,6 @@ #include <arch/cpu.h> -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 static inline int is_cpu_rev_a0(void) { return (cpuid_eax(1) & 0xfffef) == 0x0f00; @@ -77,7 +77,7 @@ int is_e0_later_in_bsp(int nodeid); //defined model_fxx_init.c #endif -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 //AMD_F0_SUPPORT static inline int is_cpu_pre_f0(void) { diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index ae58fed050..da7e6c5d17 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -12,7 +12,7 @@ void pci_write_config8(device_t dev, unsigned where, uint8_t val); void pci_write_config16(device_t dev, unsigned where, uint16_t val); void pci_write_config32(device_t dev, unsigned where, uint32_t val); -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT uint8_t pci_mmio_read_config8(device_t dev, unsigned where); uint16_t pci_mmio_read_config16(device_t dev, unsigned where); uint32_t pci_mmio_read_config32(device_t dev, unsigned where); diff --git a/src/include/part/fallback_boot.h b/src/include/part/fallback_boot.h index 17db5c6d9f..be4e3989bd 100644 --- a/src/include/part/fallback_boot.h +++ b/src/include/part/fallback_boot.h @@ -3,7 +3,7 @@ #ifndef ASSEMBLY -#if HAVE_FALLBACK_BOOT == 1 +#if CONFIG_HAVE_FALLBACK_BOOT == 1 void set_boot_successful(void); #else #define set_boot_successful() diff --git a/src/include/part/hard_reset.h b/src/include/part/hard_reset.h index fd1bf62c44..cbfc747d1e 100644 --- a/src/include/part/hard_reset.h +++ b/src/include/part/hard_reset.h @@ -1,7 +1,7 @@ #ifndef PART_HARD_RESET_H #define PART_HARD_RESET_H -#if HAVE_HARD_RESET == 1 +#if CONFIG_HAVE_HARD_RESET == 1 void hard_reset(void); #else #define hard_reset() do {} while(0) diff --git a/src/include/part/init_timer.h b/src/include/part/init_timer.h index d8b372dc38..61142964a2 100644 --- a/src/include/part/init_timer.h +++ b/src/include/part/init_timer.h @@ -1,7 +1,7 @@ #ifndef PART_INIT_TIMER_H #define PART_DELAY_H -#if HAVE_INIT_TIMER == 1 +#if CONFIG_HAVE_INIT_TIMER == 1 void init_timer(void); #else #define init_timer() do{} while(0) diff --git a/src/include/part/watchdog.h b/src/include/part/watchdog.h index 4374f3060d..26b537dbe9 100644 --- a/src/include/part/watchdog.h +++ b/src/include/part/watchdog.h @@ -1,7 +1,7 @@ #ifndef PART_WATCHDOG_H #define PART_WATCHDOG_H -#if USE_WATCHDOG_ON_BOOT == 1 +#if CONFIG_USE_WATCHDOG_ON_BOOT == 1 void watchdog_off(void); #else #define watchdog_off() diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index e7e13c85b7..d510bd2d22 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -82,19 +82,19 @@ #define PC_CKS_LOC 46 /* Linux bios checksum is built only over bytes 49..125 */ -#ifndef LB_CKS_RANGE_START -#define LB_CKS_RANGE_START 49 +#ifndef CONFIG_LB_CKS_RANGE_START +#define CONFIG_LB_CKS_RANGE_START 49 #endif -#ifndef LB_CKS_RANGE_END -#define LB_CKS_RANGE_END 125 +#ifndef CONFIG_LB_CKS_RANGE_END +#define CONFIG_LB_CKS_RANGE_END 125 #endif -#ifndef LB_CKS_LOC -#define LB_CKS_LOC 126 +#ifndef CONFIG_LB_CKS_LOC +#define CONFIG_LB_CKS_LOC 126 #endif #if !defined(ASSEMBLY) void rtc_init(int invalid); -#if USE_OPTION_TABLE == 1 +#if CONFIG_USE_OPTION_TABLE == 1 int get_option(void *dest, char *name); #else static inline int get_option(void *dest, char *name) { return -2; } diff --git a/src/include/x86emu/fpu_regs.h b/src/include/x86emu/fpu_regs.h index 67a82d8a05..dbdb67b618 100644 --- a/src/include/x86emu/fpu_regs.h +++ b/src/include/x86emu/fpu_regs.h @@ -40,8 +40,8 @@ #define __X86EMU_FPU_REGS_H -#if defined(DEBUG) && (DEBUG == 0) -#undef DEBUG +#if defined(CONFIG_DEBUG) && (DEBUG == 0) +#undef CONFIG_DEBUG #endif #ifdef X86_FPU_SUPPORT @@ -107,7 +107,7 @@ struct x86_fpu_registers { #endif /* X86_FPU_SUPPORT */ -#ifdef DEBUG +#ifdef CONFIG_DEBUG # define DECODE_PRINTINSTR32(t,mod,rh,rl) \ DECODE_PRINTF(t[(mod<<3)+(rh)]); # define DECODE_PRINTINSTR256(t,mod,rh,rl) \ diff --git a/src/include/x86emu/regs.h b/src/include/x86emu/regs.h index 8f89b22c53..86fabeabda 100644 --- a/src/include/x86emu/regs.h +++ b/src/include/x86emu/regs.h @@ -40,8 +40,8 @@ #ifndef __X86EMU_REGS_H #define __X86EMU_REGS_H -#if defined(DEBUG) && (DEBUG == 0) -#undef DEBUG +#if defined(CONFIG_DEBUG) && (CONFIG_DEBUG == 0) +#undef CONFIG_DEBUG #endif /*---------------------- Macros and type definitions ----------------------*/ @@ -283,7 +283,7 @@ typedef struct { u32 mode; volatile int intr; /* mask of pending interrupts */ volatile int debug; -#ifdef DEBUG +#ifdef CONFIG_DEBUG int check; u16 saved_ip; u16 saved_cs; diff --git a/src/include/x86emu/x86emu.h b/src/include/x86emu/x86emu.h index e5614ea183..bd01f20cc4 100644 --- a/src/include/x86emu/x86emu.h +++ b/src/include/x86emu/x86emu.h @@ -42,8 +42,8 @@ #ifndef __X86EMU_X86EMU_H #define __X86EMU_X86EMU_H -#if defined(DEBUG) && (DEBUG == 0) -#undef DEBUG +#if defined(CONFIG_DEBUG) && (CONFIG_DEBUG == 0) +#undef CONFIG_DEBUG #endif /* FIXME: undefine printk for the moment */ @@ -165,7 +165,7 @@ void X86EMU_prepareForInt(int num); void X86EMU_exec(void); void X86EMU_halt_sys(void); -#ifdef DEBUG +#ifdef CONFIG_DEBUG #define HALT_SYS() \ printk("halt_sys: file %s, line %d\n", __FILE__, __LINE__); \ X86EMU_halt_sys(); diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c index 9e892dd680..59476fdf2a 100644 --- a/src/lib/fallback_boot.c +++ b/src/lib/fallback_boot.c @@ -5,7 +5,7 @@ #include <arch/io.h> -#if HAVE_FALLBACK_BOOT == 1 +#if CONFIG_HAVE_FALLBACK_BOOT == 1 void set_boot_successful(void) { /* Remember I succesfully booted by setting diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index b9abc9e219..79eb1c51c1 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -80,7 +80,7 @@ void init_uart8250(unsigned base_port, struct uart8250 *uart) int lcs; divisor = 115200/(uart->baud ? uart->baud: 1); lcs = 3; - if (base_port == TTYS0_BASE) { + if (base_port == CONFIG_TTYS0_BASE) { /* Don't reinitialize the console serial port, * This is espeically nasty in SMP. */ diff --git a/src/lib/version.c b/src/lib/version.c index 404f50d730..2c84c4ae86 100644 --- a/src/lib/version.c +++ b/src/lib/version.c @@ -1,10 +1,10 @@ #include <version.h> -#ifndef MAINBOARD_VENDOR -#error MAINBOARD_VENDOR not defined +#ifndef CONFIG_MAINBOARD_VENDOR +#error CONFIG_MAINBOARD_VENDOR not defined #endif -#ifndef MAINBOARD_PART_NUMBER -#error MAINBOARD_PART_NUMBER not defined +#ifndef CONFIG_MAINBOARD_PART_NUMBER +#error CONFIG_MAINBOARD_PART_NUMBER not defined #endif #ifndef COREBOOT_VERSION @@ -39,8 +39,8 @@ #define COREBOOT_EXTRA_VERSION "" #endif -const char mainboard_vendor[] = MAINBOARD_VENDOR; -const char mainboard_part_number[] = MAINBOARD_PART_NUMBER; +const char mainboard_vendor[] = CONFIG_MAINBOARD_VENDOR; +const char mainboard_part_number[] = CONFIG_MAINBOARD_PART_NUMBER; const char coreboot_version[] = COREBOOT_VERSION; const char coreboot_extra_version[] = COREBOOT_EXTRA_VERSION; diff --git a/src/lib/xmodem.c b/src/lib/xmodem.c index aca6e49d58..8321151ce0 100644 --- a/src/lib/xmodem.c +++ b/src/lib/xmodem.c @@ -26,17 +26,17 @@ extern unsigned char uart8250_rx_byte(unsigned); static int _inbyte(int msec) { - while (!uart8250_can_rx_byte(TTYS0_BASE)) { + while (!uart8250_can_rx_byte(CONFIG_TTYS0_BASE)) { udelay(1000); if (msec-- <= 0) return -1; } - return uart8250_rx_byte(TTYS0_BASE); + return uart8250_rx_byte(CONFIG_TTYS0_BASE); } static void _outbyte(unsigned char c) { - uart8250_tx_byte(TTYS0_BASE, c); + uart8250_tx_byte(CONFIG_TTYS0_BASE, c); } static unsigned short crc16_ccitt(const unsigned char *buf, int sz) diff --git a/src/mainboard/a-trend/atc-6220/Config.lb b/src/mainboard/a-trend/atc-6220/Config.lb index 843728dc20..7d9b82ba1a 100644 --- a/src/mainboard/a-trend/atc-6220/Config.lb +++ b/src/mainboard/a-trend/atc-6220/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/a-trend/atc-6220/Options.lb b/src/mainboard/a-trend/atc-6220/Options.lb index 2641e766df..4d927e1fb8 100644 --- a/src/mainboard/a-trend/atc-6220/Options.lb +++ b/src/mainboard/a-trend/atc-6220/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/a-trend/atc-6220/auto.c b/src/mainboard/a-trend/atc-6220/auto.c index 2e60b1c526..1b5891e519 100644 --- a/src/mainboard/a-trend/atc-6220/auto.c +++ b/src/mainboard/a-trend/atc-6220/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/a-trend/atc-6220/irq_tables.c b/src/mainboard/a-trend/atc-6220/irq_tables.c index e13fb52e43..8415fb12c3 100644 --- a/src/mainboard/a-trend/atc-6220/irq_tables.c +++ b/src/mainboard/a-trend/atc-6220/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x07 << 3) | 0x0, /* Interrupt router device */ 0x600, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/a-trend/atc-6240/Config.lb b/src/mainboard/a-trend/atc-6240/Config.lb index f3e10c8ce8..dd7ee2df9b 100644 --- a/src/mainboard/a-trend/atc-6240/Config.lb +++ b/src/mainboard/a-trend/atc-6240/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/a-trend/atc-6240/Options.lb b/src/mainboard/a-trend/atc-6240/Options.lb index 31c70358f5..feb32318c7 100644 --- a/src/mainboard/a-trend/atc-6240/Options.lb +++ b/src/mainboard/a-trend/atc-6240/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/a-trend/atc-6240/auto.c b/src/mainboard/a-trend/atc-6240/auto.c index eaa8407583..782e307d99 100644 --- a/src/mainboard/a-trend/atc-6240/auto.c +++ b/src/mainboard/a-trend/atc-6240/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/a-trend/atc-6240/irq_tables.c b/src/mainboard/a-trend/atc-6240/irq_tables.c index 0e4c167866..63b276f4fe 100644 --- a/src/mainboard/a-trend/atc-6240/irq_tables.c +++ b/src/mainboard/a-trend/atc-6240/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x07 << 3) | 0x0, /* Interrupt router device */ 0xc20, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/abit/be6-ii_v2_0/Config.lb b/src/mainboard/abit/be6-ii_v2_0/Config.lb index 97c403ce81..d8c1ce3f94 100644 --- a/src/mainboard/abit/be6-ii_v2_0/Config.lb +++ b/src/mainboard/abit/be6-ii_v2_0/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/abit/be6-ii_v2_0/Options.lb b/src/mainboard/abit/be6-ii_v2_0/Options.lb index 986b770bbc..55255c120e 100644 --- a/src/mainboard/abit/be6-ii_v2_0/Options.lb +++ b/src/mainboard/abit/be6-ii_v2_0/Options.lb @@ -18,83 +18,83 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 # Override this in targets/*/Config.lb. -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 # Override this in targets/*/Config.lb. +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. -default MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. default CONFIG_CONSOLE_VGA = 1 # Override this in targets/*/Config.lb. default CONFIG_PCI_ROM_RUN = 1 # Override this in targets/*/Config.lb. diff --git a/src/mainboard/abit/be6-ii_v2_0/auto.c b/src/mainboard/abit/be6-ii_v2_0/auto.c index dd43c07a84..fe9bce8423 100644 --- a/src/mainboard/abit/be6-ii_v2_0/auto.c +++ b/src/mainboard/abit/be6-ii_v2_0/auto.c @@ -57,7 +57,7 @@ static void main(unsigned long bist) early_mtrr_init(); /* FIXME: It's a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/abit/be6-ii_v2_0/irq_tables.c b/src/mainboard/abit/be6-ii_v2_0/irq_tables.c index 88aaf9c885..c33e0331f7 100644 --- a/src/mainboard/abit/be6-ii_v2_0/irq_tables.c +++ b/src/mainboard/abit/be6-ii_v2_0/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x07 << 3) | 0x0, /* Interrupt router device */ 0x1c20, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/advantech/pcm-5820/Config.lb b/src/mainboard/advantech/pcm-5820/Config.lb index 8906f6e191..3437d74b3f 100644 --- a/src/mainboard/advantech/pcm-5820/Config.lb +++ b/src/mainboard/advantech/pcm-5820/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/advantech/pcm-5820/Options.lb b/src/mainboard/advantech/pcm-5820/Options.lb index 8e8d078aaa..43bbd6b3dd 100644 --- a/src/mainboard/advantech/pcm-5820/Options.lb +++ b/src/mainboard/advantech/pcm-5820/Options.lb @@ -18,45 +18,45 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 @@ -64,7 +64,7 @@ uses CONFIG_VIDEO_MB uses CONFIG_SPLASH_GRAPHIC uses CONFIG_GX1_VIDEO uses CONFIG_GX1_VIDEOMODE -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE ## Enable VGA with a splash screen (only 640x480 to run on most monitors). ## We want to support up to 1024x768@16 so we need 2MiB video memory. @@ -74,34 +74,34 @@ default CONFIG_GX1_VIDEOMODE = 0 default CONFIG_SPLASH_GRAPHIC = 1 default CONFIG_VIDEO_MB = 2 -default ROM_SIZE = 256 * 1024 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default PIRQ_ROUTE = 1 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_PIRQ_ROUTE = 1 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_OPTION_TABLE = 0 -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_OPTION_TABLE = 0 +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc " -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc " +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 # # CBFS diff --git a/src/mainboard/advantech/pcm-5820/auto.c b/src/mainboard/advantech/pcm-5820/auto.c index bcb65c245d..20dff7eedb 100644 --- a/src/mainboard/advantech/pcm-5820/auto.c +++ b/src/mainboard/advantech/pcm-5820/auto.c @@ -36,7 +36,7 @@ static void main(unsigned long bist) { - w83977f_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/advantech/pcm-5820/irq_tables.c b/src/mainboard/advantech/pcm-5820/irq_tables.c index 573ecd7d44..d176ecbf26 100644 --- a/src/mainboard/advantech/pcm-5820/irq_tables.c +++ b/src/mainboard/advantech/pcm-5820/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x12 << 3) | 0x0, /* Interrupt router device */ 0xc00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/amd/db800/Config.lb b/src/mainboard/amd/db800/Config.lb index 90525f32b0..c82c664a7c 100644 --- a/src/mainboard/amd/db800/Config.lb +++ b/src/mainboard/amd/db800/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,14 +14,14 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -37,7 +37,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds # mainboardinit ./failover.inc end diff --git a/src/mainboard/amd/db800/Options.lb b/src/mainboard/amd/db800/Options.lb index 33d1d15295..06a0e386ce 100644 --- a/src/mainboard/amd/db800/Options.lb +++ b/src/mainboard/amd/db800/Options.lb @@ -1,59 +1,59 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -65,17 +65,17 @@ default CONFIG_PCI_ROM_RUN=0 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -85,58 +85,58 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=4 -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=4 +default CONFIG_PIRQ_ROUTE=1 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 default CONFIG_USE_PRINTK_IN_CAR=1 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -146,21 +146,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -172,13 +172,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/amd/db800/cache_as_ram_auto.c b/src/mainboard/amd/db800/cache_as_ram_auto.c index c0554f1f9e..0ea76445aa 100644 --- a/src/mainboard/amd/db800/cache_as_ram_auto.c +++ b/src/mainboard/amd/db800/cache_as_ram_auto.c @@ -113,7 +113,7 @@ void cache_as_ram_main(void) /* Note: must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); uart_init(); console_init(); diff --git a/src/mainboard/amd/db800/irq_tables.c b/src/mainboard/amd/db800/irq_tables.c index f9a6312fa8..c2c154ecda 100644 --- a/src/mainboard/amd/db800/irq_tables.c +++ b/src/mainboard/amd/db800/irq_tables.c @@ -44,7 +44,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -54,7 +54,7 @@ const struct irq_routing_table intel_irq_routing_table = { {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ + /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ diff --git a/src/mainboard/amd/dbm690t/Config.lb b/src/mainboard/amd/dbm690t/Config.lb index 0735c03a32..9a3b6d93ad 100644 --- a/src/mainboard/amd/dbm690t/Config.lb +++ b/src/mainboard/amd/dbm690t/Config.lb @@ -19,8 +19,8 @@ ## ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -33,18 +33,18 @@ driver mainboard.o #dir /drivers/si/3114 -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object get_bus_conf.o object irq_tables.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o object fadt.o makerule dsdt.c - depends "$(MAINBOARD)/acpi/*.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl" + depends "$(CONFIG_MAINBOARD)/acpi/*.asl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o @@ -55,15 +55,15 @@ end if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -87,7 +87,7 @@ ldscript /cpu/x86/16bit/entry16.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -111,7 +111,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/amd/dbm690t/Options.lb b/src/mainboard/amd/dbm690t/Options.lb index be32edf8a1..8835d2997d 100644 --- a/src/mainboard/amd/dbm690t/Options.lb +++ b/src/mainboard/amd/dbm690t/Options.lb @@ -19,133 +19,133 @@ ## ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_USE_PRINTK_IN_CAR uses CONFIG_VIDEO_MB uses CONFIG_GFXUMA -uses HAVE_MAINBOARD_RESOURCES +uses CONFIG_HAVE_MAINBOARD_RESOURCES ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -158,7 +158,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -166,23 +166,23 @@ default CONFIG_PCI_ROM_RUN=1 # BTDC: Only one HT device on Herring. #HT Unit ID offset -#default HT_CHAIN_UNITID_BASE=0x6 -default HT_CHAIN_UNITID_BASE=0x0 +#default CONFIG_HT_CHAIN_UNITID_BASE=0x6 +default CONFIG_HT_CHAIN_UNITID_BASE=0x0 #real SB Unit ID -default HT_CHAIN_END_UNITID_BASE=0x1 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1 #make the SB HT chain on bus 0 -default SB_HT_CHAIN_ON_BUS0=1 +default CONFIG_SB_HT_CHAIN_ON_BUS0=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x8000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x8000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 ## @@ -193,39 +193,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="dbm690t" -default MAINBOARD_VENDOR="amd" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 +default CONFIG_MAINBOARD_PART_NUMBER="dbm690t" +default CONFIG_MAINBOARD_VENDOR="amd" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 ## ## coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -239,8 +239,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -258,21 +258,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -284,21 +284,21 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" default CONFIG_VIDEO_MB=1 default CONFIG_GFXUMA=1 -default HAVE_MAINBOARD_RESOURCES=1 +default CONFIG_HAVE_MAINBOARD_RESOURCES=1 ### End Options.lb # diff --git a/src/mainboard/amd/dbm690t/acpi_tables.c b/src/mainboard/amd/dbm690t/acpi_tables.c index 9aaede4b8d..3829a7a082 100644 --- a/src/mainboard/amd/dbm690t/acpi_tables.c +++ b/src/mainboard/amd/dbm690t/acpi_tables.c @@ -59,7 +59,7 @@ static void dump_mem(u32 start, u32 end) extern u8 AmlCode[]; -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 extern u8 AmlCode_ssdt2[]; extern u8 AmlCode_ssdt3[]; extern u8 AmlCode_ssdt4[]; @@ -201,7 +201,7 @@ unsigned long write_acpi_tables(unsigned long start) current += ssdt->length; acpi_add_table(rsdt, ssdt); -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */ diff --git a/src/mainboard/amd/dbm690t/cache_as_ram_auto.c b/src/mainboard/amd/dbm690t/cache_as_ram_auto.c index 29cdfb37f7..75ff96c338 100644 --- a/src/mainboard/amd/dbm690t/cache_as_ram_auto.c +++ b/src/mainboard/amd/dbm690t/cache_as_ram_auto.c @@ -100,7 +100,7 @@ static inline int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_fxx/fidvid.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "northbridge/amd/amdk8/early_ht.c" @@ -139,14 +139,14 @@ normal_image: fallback_image: post_code(0x25); } -#endif /* USE_FALLBACK_IMAGE == 1 */ +#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -159,7 +159,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; - struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); if (bist == 0) { @@ -170,7 +170,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) sb600_lpc_init(); /* it8712f_enable_serial does not use its 1st parameter. */ - it8712f_enable_serial(0, TTYS0_BASE); + it8712f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c index 4f5bec3273..daaf4d2daa 100644 --- a/src/mainboard/amd/dbm690t/mptable.c +++ b/src/mainboard/amd/dbm690t/mptable.c @@ -142,7 +142,7 @@ void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if HAVE_ACPI_TABLES == 0 +#if CONFIG_HAVE_ACPI_TABLES == 0 #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else diff --git a/src/mainboard/amd/norwich/Config.lb b/src/mainboard/amd/norwich/Config.lb index 7a6ff1e54f..a92120e7c9 100644 --- a/src/mainboard/amd/norwich/Config.lb +++ b/src/mainboard/amd/norwich/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,7 +14,7 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end @@ -22,8 +22,8 @@ end #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -39,7 +39,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -61,7 +61,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds # mainboardinit ./failover.inc end diff --git a/src/mainboard/amd/norwich/Options.lb b/src/mainboard/amd/norwich/Options.lb index 634f848c5f..fc71fdb24c 100644 --- a/src/mainboard/amd/norwich/Options.lb +++ b/src/mainboard/amd/norwich/Options.lb @@ -1,59 +1,59 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -65,17 +65,17 @@ default CONFIG_PCI_ROM_RUN=0 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -85,58 +85,58 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=6 -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=6 +default CONFIG_PIRQ_ROUTE=1 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 default CONFIG_USE_PRINTK_IN_CAR=1 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -146,21 +146,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -172,13 +172,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/amd/norwich/irq_tables.c b/src/mainboard/amd/norwich/irq_tables.c index 5e408b7241..5279bcd27e 100644 --- a/src/mainboard/amd/norwich/irq_tables.c +++ b/src/mainboard/amd/norwich/irq_tables.c @@ -44,7 +44,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -54,7 +54,7 @@ const struct irq_routing_table intel_irq_routing_table = { {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ + /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ diff --git a/src/mainboard/amd/pistachio/Config.lb b/src/mainboard/amd/pistachio/Config.lb index 90d840316c..33079a2607 100644 --- a/src/mainboard/amd/pistachio/Config.lb +++ b/src/mainboard/amd/pistachio/Config.lb @@ -19,8 +19,8 @@ ## ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -33,18 +33,18 @@ driver mainboard.o #dir /drivers/si/3114 -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object get_bus_conf.o object irq_tables.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o object fadt.o makerule dsdt.c - depends "$(MAINBOARD)/acpi/*.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl" + depends "$(CONFIG_MAINBOARD)/acpi/*.asl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o @@ -55,15 +55,15 @@ end if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -87,7 +87,7 @@ ldscript /cpu/x86/16bit/entry16.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -111,7 +111,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/amd/pistachio/Options.lb b/src/mainboard/amd/pistachio/Options.lb index 29e7802e25..321c4d292d 100644 --- a/src/mainboard/amd/pistachio/Options.lb +++ b/src/mainboard/amd/pistachio/Options.lb @@ -19,133 +19,133 @@ ## ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_USE_PRINTK_IN_CAR uses CONFIG_VIDEO_MB uses CONFIG_GFXUMA -uses HAVE_MAINBOARD_RESOURCES +uses CONFIG_HAVE_MAINBOARD_RESOURCES ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -158,7 +158,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -166,23 +166,23 @@ default CONFIG_PCI_ROM_RUN=1 # BTDC: Only one HT device on Herring. #HT Unit ID offset -#default HT_CHAIN_UNITID_BASE=0x6 -default HT_CHAIN_UNITID_BASE=0x0 +#default CONFIG_HT_CHAIN_UNITID_BASE=0x6 +default CONFIG_HT_CHAIN_UNITID_BASE=0x0 #real SB Unit ID -default HT_CHAIN_END_UNITID_BASE=0x1 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1 #make the SB HT chain on bus 0 -default SB_HT_CHAIN_ON_BUS0=1 +default CONFIG_SB_HT_CHAIN_ON_BUS0=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x8000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x8000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 ## @@ -193,39 +193,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="pistachio" -default MAINBOARD_VENDOR="amd" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 +default CONFIG_MAINBOARD_PART_NUMBER="pistachio" +default CONFIG_MAINBOARD_VENDOR="amd" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 ## ## coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -239,8 +239,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -258,21 +258,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -284,21 +284,21 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" default CONFIG_VIDEO_MB=1 default CONFIG_GFXUMA=1 -default HAVE_MAINBOARD_RESOURCES=1 +default CONFIG_HAVE_MAINBOARD_RESOURCES=1 ### End Options.lb # diff --git a/src/mainboard/amd/pistachio/acpi_tables.c b/src/mainboard/amd/pistachio/acpi_tables.c index 541f6e48f6..e985d4552a 100644 --- a/src/mainboard/amd/pistachio/acpi_tables.c +++ b/src/mainboard/amd/pistachio/acpi_tables.c @@ -59,7 +59,7 @@ static void dump_mem(u32 start, u32 end) extern u8 AmlCode[]; -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 extern u8 AmlCode_ssdt2[]; extern u8 AmlCode_ssdt3[]; extern u8 AmlCode_ssdt4[]; @@ -201,7 +201,7 @@ unsigned long write_acpi_tables(unsigned long start) current += ssdt->length; acpi_add_table(rsdt, ssdt); -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */ diff --git a/src/mainboard/amd/pistachio/cache_as_ram_auto.c b/src/mainboard/amd/pistachio/cache_as_ram_auto.c index ade2024355..bbe96ce978 100644 --- a/src/mainboard/amd/pistachio/cache_as_ram_auto.c +++ b/src/mainboard/amd/pistachio/cache_as_ram_auto.c @@ -94,7 +94,7 @@ static inline int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_fxx/fidvid.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "northbridge/amd/amdk8/early_ht.c" @@ -133,14 +133,14 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) fallback_image: post_code(0x02); } -#endif /* USE_FALLBACK_IMAGE == 1 */ +#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -154,8 +154,8 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) msr_t msr; struct cpuid_result cpuid1; struct sys_info *sysinfo = - (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - - DCACHE_RAM_GLOBAL_VAR_SIZE); + (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - + CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c index f0f77ef37c..23b38ca846 100644 --- a/src/mainboard/amd/pistachio/mptable.c +++ b/src/mainboard/amd/pistachio/mptable.c @@ -142,7 +142,7 @@ void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if HAVE_ACPI_TABLES == 0 +#if CONFIG_HAVE_ACPI_TABLES == 0 #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else diff --git a/src/mainboard/amd/rumba/Config.lb b/src/mainboard/amd/rumba/Config.lb index 426b7a62c7..466703fcc3 100644 --- a/src/mainboard/amd/rumba/Config.lb +++ b/src/mainboard/amd/rumba/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,29 +14,29 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -50,7 +50,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -72,7 +72,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/amd/rumba/Options.lb b/src/mainboard/amd/rumba/Options.lb index 70c05bfa56..eff01c1087 100644 --- a/src/mainboard/amd/rumba/Options.lb +++ b/src/mainboard/amd/rumba/Options.lb @@ -1,50 +1,50 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -53,17 +53,17 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -73,49 +73,49 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=2 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=2 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -125,21 +125,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -151,13 +151,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c index b3a9b839ee..e1326ff622 100644 --- a/src/mainboard/amd/rumba/auto.c +++ b/src/mainboard/amd/rumba/auto.c @@ -127,7 +127,7 @@ static void main(unsigned long bist) SystemPreInit(); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/amd/serengeti_cheetah/Config.lb b/src/mainboard/amd/serengeti_cheetah/Config.lb index 85d61720bc..80d6318792 100644 --- a/src/mainboard/amd/serengeti_cheetah/Config.lb +++ b/src/mainboard/amd/serengeti_cheetah/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -15,25 +15,25 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end -#if HAVE_ACPI_TABLES +#if CONFIG_HAVE_ACPI_TABLES # object acpi_tables.o # object fadt.o -# if SB_HT_CHAIN_ON_BUS0 +# if CONFIG_SB_HT_CHAIN_ON_BUS0 # object dsdt_bus0.o # else # object dsdt.o # end # object ssdt.o -# if ACPI_SSDTX_NUM -# if SB_HT_CHAIN_ON_BUS0 +# if CONFIG_ACPI_SSDTX_NUM +# if CONFIG_SB_HT_CHAIN_ON_BUS0 # object ssdt2_bus0.o # else # object ssdt2.o @@ -41,36 +41,36 @@ end # end #end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o object fadt.o makerule dsdt.c - depends "$(MAINBOARD)/dx/dsdt_lb.dsl" - action "iasl -p $(CURDIR)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl" + depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" + action "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" action "mv dsdt_lb.hex dsdt.c" end object ./dsdt.o #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb - if ACPI_SSDTX_NUM + if CONFIG_ACPI_SSDTX_NUM makerule ssdt2.c - depends "$(MAINBOARD)/dx/pci2.asl" - action "iasl -p $(CURDIR)/pci2 -tc $(MAINBOARD)/dx/pci2.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci2.asl" + action "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" action "mv pci2.hex ssdt2.c" end object ./ssdt2.o makerule ssdt3.c - depends "$(MAINBOARD)/dx/pci3.asl" - action "iasl -p $(CURDIR)/pci3 -tc $(MAINBOARD)/dx/pci3.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci3.asl" + action "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex" action "mv pci3.hex ssdt3.c" end object ./ssdt3.o makerule ssdt4.c - depends "$(MAINBOARD)/dx/pci4.asl" - action "iasl -p $(CURDIR)/pci4 -tc $(MAINBOARD)/dx/pci4.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci4.asl" + action "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex" action "mv pci4.hex ssdt4.c" end @@ -81,26 +81,26 @@ end if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -110,13 +110,13 @@ end ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -134,8 +134,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -143,7 +143,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -168,12 +168,12 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/amd/serengeti_cheetah/Options.lb b/src/mainboard/amd/serengeti_cheetah/Options.lb index 697e9119a2..68d3f10b2f 100644 --- a/src/mainboard/amd/serengeti_cheetah/Options.lb +++ b/src/mainboard/amd/serengeti_cheetah/Options.lb @@ -1,85 +1,85 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -87,9 +87,9 @@ uses CONFIG_LB_MEM_TOPK uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -98,20 +98,20 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE=0x3f000 #FAILOVER: 4K -default FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -119,42 +119,42 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## extra SSDT num -default ACPI_SSDTX_NUM=1 +default CONFIG_ACPI_SSDTX_NUM=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -165,41 +165,41 @@ default CONFIG_MAX_CPUS=8 default CONFIG_MAX_PHYSICAL_CPUS=4 default CONFIG_LOGICAL_CPUS=1 -default SERIAL_CPU_INIT=0 +default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x8 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x8 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 #HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0xa +default CONFIG_HT_CHAIN_UNITID_BASE=0xa #real SB Unit ID, default is 0x20, mean dont touch it at last -default HT_CHAIN_END_UNITID_BASE=0x6 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -207,10 +207,10 @@ default SB_HT_CHAIN_ON_BUS0=2 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 @@ -218,8 +218,8 @@ default CONFIG_USE_INIT=0 ## for rev F training on AP purpose ## default CONFIG_AP_CODE_IN_CAR=1 -default MEM_TRAIN_SEQ=1 -default WAIT_BEFORE_CPUS_INIT=1 +default CONFIG_MEM_TRAIN_SEQ=1 +default CONFIG_WAIT_BEFORE_CPUS_INIT=1 ## ## Build code to setup a generic IOAPIC @@ -229,37 +229,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="serengeti_cheetah" -default MAINBOARD_VENDOR="AMD" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 +default CONFIG_MAINBOARD_PART_NUMBER="serengeti_cheetah" +default CONFIG_MAINBOARD_VENDOR="AMD" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -273,8 +273,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -290,21 +290,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -316,17 +316,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c index d671907687..04e52364de 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c @@ -39,7 +39,7 @@ static void dump_mem(unsigned start, unsigned end) #endif extern unsigned char AmlCode[]; -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 extern unsigned char AmlCode_ssdt2[]; extern unsigned char AmlCode_ssdt3[]; extern unsigned char AmlCode_ssdt4[]; @@ -263,7 +263,7 @@ unsigned long write_acpi_tables(unsigned long start) current += ssdt->length; acpi_add_table(rsdt, ssdt); -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table diff --git a/src/mainboard/amd/serengeti_cheetah/apc_auto.c b/src/mainboard/amd/serengeti_cheetah/apc_auto.c index 584309508e..5a173e006b 100644 --- a/src/mainboard/amd/serengeti_cheetah/apc_auto.c +++ b/src/mainboard/amd/serengeti_cheetah/apc_auto.c @@ -74,8 +74,8 @@ static inline unsigned get_nodes(void) void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c b/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c index 95a3395abe..fb1be8dd28 100644 --- a/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c +++ b/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c @@ -19,7 +19,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -45,7 +45,7 @@ static void post_code(uint8_t value) { #endif } #endif -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include <cpu/amd/model_fxx_rev.h> @@ -59,7 +59,7 @@ static void post_code(uint8_t value) { #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" #include "lib/delay.c" @@ -156,7 +156,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/fidvid.c" #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -201,7 +201,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -215,21 +215,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -253,7 +253,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; int i; unsigned bsp_apicid = 0; @@ -265,11 +265,11 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); -// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); +// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -284,7 +284,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c index f1b374ae95..cd580f1232 100644 --- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c @@ -109,7 +109,7 @@ void get_bus_conf(void) dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); if (dev) { m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); m->bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); @@ -132,7 +132,7 @@ void get_bus_conf(void) dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0)); if (dev) { m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); m->bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb index 405ebcf4ff..456ad0ecfd 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb @@ -17,8 +17,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -33,51 +33,51 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o object fadt.o makerule dsdt.c - depends "$(MAINBOARD)/dx/dsdt_lb.dsl" - action "iasl -p $(CURDIR)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl" + depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" + action "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" action "mv dsdt_lb.hex dsdt.c" end object ./dsdt.o #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb - if ACPI_SSDTX_NUM + if CONFIG_ACPI_SSDTX_NUM makerule ssdt2.c - depends "$(MAINBOARD)/dx/pci2.asl" - action "iasl -p $(CURDIR)/pci2 -tc $(MAINBOARD)/dx/pci2.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci2.asl" + action "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" action "mv pci2.hex ssdt2.c" end object ./ssdt2.o makerule ssdt3.c - depends "$(MAINBOARD)/dx/pci3.asl" - action "iasl -p $(CURDIR)/pci3 -tc $(MAINBOARD)/dx/pci3.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci3.asl" + action "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex" action "mv pci3.hex ssdt3.c" end object ./ssdt3.o makerule ssdt4.c - depends "$(MAINBOARD)/dx/pci4.asl" - action "iasl -p $(CURDIR)/pci4 -tc $(MAINBOARD)/dx/pci4.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci4.asl" + action "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex" action "mv pci4.hex ssdt4.c" end object ./ssdt4.o makerule ssdt5.c - depends "$(MAINBOARD)/dx/pci5.asl" - action "iasl -p $(CURDIR)/pci5 -tc $(MAINBOARD)/dx/pci5.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci5.asl" + action "iasl -p $(CURDIR)/pci5 -tc $(CONFIG_MAINBOARD)/dx/pci5.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex" action "mv pci5.hex ssdt5.c" end @@ -88,27 +88,27 @@ end if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -118,13 +118,13 @@ end ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -142,8 +142,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -151,7 +151,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -177,12 +177,12 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb index c62fbe273e..cd5f586ca7 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb @@ -17,126 +17,126 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM uses CONFIG_LB_MEM_TOPK -uses PCI_BUS_SEGN_BITS +uses CONFIG_PCI_BUS_SEGN_BITS uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_AMDMCT uses CONFIG_USE_PRINTK_IN_CAR -uses CAR_FAM10 -uses AMD_UCODE_PATCH_FILE +uses CONFIG_CAR_FAM10 +uses CONFIG_AMD_UCODE_PATCH_FILE ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1024*1024 +default CONFIG_ROM_SIZE=1024*1024 ## ## #FALLBACK_SIZE_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 1024K - 8K -default FALLBACK_SIZE=0xFE000 +default CONFIG_FALLBACK_SIZE=0xFE000 #FAILOVER: 8k -default FAILOVER_SIZE=0x02000 +default CONFIG_FAILOVER_SIZE=0x02000 #more 1M for pgtbl #if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time. @@ -145,42 +145,42 @@ default CONFIG_LB_MEM_TOPK=16384 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## extra SSDT num -default ACPI_SSDTX_NUM=31 +default CONFIG_ACPI_SSDTX_NUM=31 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -190,58 +190,58 @@ default CONFIG_MAX_PHYSICAL_CPUS=8 default CONFIG_MAX_CPUS=6 * CONFIG_MAX_PHYSICAL_CPUS default CONFIG_LOGICAL_CPUS=1 -#default SERIAL_CPU_INIT=0 +#default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=1 -default APIC_ID_OFFSET=0x00 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=1 +default CONFIG_APIC_ID_OFFSET=0x00 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 #HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0xa +default CONFIG_HT_CHAIN_UNITID_BASE=0xa #real SB Unit ID, default is 0x20, mean dont touch it at last -default HT_CHAIN_END_UNITID_BASE=0x6 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 #it only be 0, 1, 2, 3, 4 and default is 0 -#default PCI_BUS_SEGN_BITS=3 +#default CONFIG_PCI_BUS_SEGN_BITS=3 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc4000 -default DCACHE_RAM_SIZE=0x0c000 -#default DCACHE_RAM_GLOBAL_VAR_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc4000 +default CONFIG_DCACHE_RAM_SIZE=0x0c000 +#default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000 default CONFIG_USE_INIT=0 #default CONFIG_AP_CODE_IN_CAR=1 -default MEM_TRAIN_SEQ=2 -default WAIT_BEFORE_CPUS_INIT=0 +default CONFIG_MEM_TRAIN_SEQ=2 +default CONFIG_WAIT_BEFORE_CPUS_INIT=0 default CONFIG_AMDMCT = 1 @@ -253,10 +253,10 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="Cheetah Fam10" -default MAINBOARD_VENDOR="AMD" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 +default CONFIG_MAINBOARD_PART_NUMBER="Cheetah Fam10" +default CONFIG_MAINBOARD_VENDOR="AMD" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ## ## Set microcode patch file name @@ -266,34 +266,34 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ## Barcelona rev DR-B2, B3: "mc_patch_01000095.h" ## Shanghai rev DA-C2: "mc_patch_0100009f.h" ## -default AMD_UCODE_PATCH_FILE="mc_patch_01000095.h" +default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000095.h" ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 768k heap ## -default HEAP_SIZE=0xc0000 +default CONFIG_HEAP_SIZE=0xc0000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00200000 +default CONFIG_RAMBASE=0x00200000 ## ## Load the payload from the ROM @@ -307,8 +307,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -325,21 +325,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -351,17 +351,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index ed53938a63..8239a115bf 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -49,7 +49,7 @@ static void dump_mem(u32 start, u32 end) extern u8 AmlCode[]; extern u8 AmlCode_ssdt[]; -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 extern u8 AmlCode_ssdt2[]; extern u8 AmlCode_ssdt3[]; extern u8 AmlCode_ssdt4[]; @@ -276,7 +276,7 @@ unsigned long write_acpi_tables(unsigned long start) printk_debug("ACPI: * SSDT for PState at %lx\n", current); current = acpi_add_ssdt_pstates(rsdt, current); -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different possition? We may have to copy, change HCIN, and recalculate the checknum and add_table */ diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c b/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c index 49dadd799a..fbb8c14388 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c @@ -50,9 +50,9 @@ #include "lib/delay.c" #if NODE_NUMS == 64 - #define NODE_PCI(x,fn) ((x<32)?PCI_DEV(CBB,CDB+x,fn):PCI_DEV(CBB-1, CDB+x-32, fn)) + #define NODE_PCI(x,fn) ((x<32)?PCI_DEV(CONFIG_CBB,CONFIG_CDB+x,fn):PCI_DEV(CONFIG_CBB-1, CONFIG_CDB+x-32, fn)) #else - #define NODE_PCI(x, fn) PCI_DEV(CBB,CDB+x,fn) + #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,CONFIG_CDB+x,fn) #endif //#include "cpu/x86/lapic/boot_cpu.c" @@ -73,8 +73,8 @@ void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c b/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c index 38196b262e..4e484553f7 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c @@ -60,7 +60,7 @@ static void post_code(u8 value) { outb(value, 0x80); } -#if (USE_FAILOVER_IMAGE == 0) +#if (CONFIG_USE_FAILOVER_IMAGE == 0) #include "arch/i386/lib/console.c" #include "pc80/serial.c" #include "ram/ramtest.c" @@ -80,7 +80,7 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, #include "cpu/x86/bist.h" -#if (USE_FAILOVER_IMAGE == 0) +#if (CONFIG_USE_FAILOVER_IMAGE == 0) #include "northbridge/amd/amdfam10/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" @@ -142,10 +142,10 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" -#endif /* (USE_FAILOVER_IMAGE == 0) */ +#endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */ -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -190,7 +190,7 @@ normal_image: ); fallback_image: - #if HAVE_FAILOVER_BOOT==1 + #if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -198,22 +198,22 @@ fallback_image: #endif ; } -#endif /* ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) */ +#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) */ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -//FIXME: I think that there is a hole here with the real_main() logic realmain is inside a USE_FAILOVER_IMAGE=0. -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +//FIXME: I think that there is a hole here with the real_main() logic realmain is inside a CONFIG_USE_FAILOVER_IMAGE=0. +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -221,7 +221,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } -#if (USE_FAILOVER_IMAGE==0) +#if (CONFIG_USE_FAILOVER_IMAGE==0) #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" @@ -229,7 +229,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); u32 bsp_apicid = 0; u32 val; msr_t msr; @@ -243,12 +243,12 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); printk_debug("\n"); -// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); +// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -380,4 +380,4 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) } -#endif /* USE_FAILOVER_IMAGE==0 */ +#endif /* CONFIG_USE_FAILOVER_IMAGE==0 */ diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c index d1d1ff8e32..de8eacde6b 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c @@ -116,11 +116,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) } -#if CBB - write_pirq_info(pirq_info, CBB, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +#if CONFIG_CBB + write_pirq_info(pirq_info, CONFIG_CBB, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; if(sysconf.nodes>32) { - write_pirq_info(pirq_info, CBB-1, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + write_pirq_info(pirq_info, CONFIG_CBB-1, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; } #endif diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c index 04698d7369..25093fd8b1 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c @@ -49,14 +49,14 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CBB, CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR_FAM10 - PCI_ADDR(CBB, CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CBB, CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CBB, CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CBB, CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CBB, CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CBB, CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CBB, CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CBB, CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CAR_FAM10 - PCI_ADDR(CBB, CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ static void setup_mb_resource_map(void) * This field defines the upp adddress bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CBB, CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CBB, CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CBB, CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CBB, CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CBB, CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CBB, CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CBB, CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CBB, CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CBB, CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CBB, CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, }; int max; diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb index d25ea1608b..89174f1a2a 100644 --- a/src/mainboard/arima/hdama/Config.lb +++ b/src/mainboard/arima/hdama/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## @@ -13,21 +13,21 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -37,7 +37,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -55,7 +55,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -79,7 +79,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/arima/hdama/Options.lb b/src/mainboard/arima/hdama/Options.lb index 24fff9b1ac..6f83531541 100644 --- a/src/mainboard/arima/hdama/Options.lb +++ b/src/mainboard/arima/hdama/Options.lb @@ -1,61 +1,61 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_LOGICAL_CPUS -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -69,48 +69,48 @@ uses CONFIG_USE_PRINTK_IN_CAR default CONFIG_LOGICAL_CPUS=1 ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=9 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -128,9 +128,9 @@ default CONFIG_IOAPIC=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 #VGA @@ -140,38 +140,38 @@ default CONFIG_PCI_ROM_RUN=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="HDAMA" -default MAINBOARD_VENDOR="ARIMA" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 +default CONFIG_MAINBOARD_PART_NUMBER="HDAMA" +default CONFIG_MAINBOARD_VENDOR="ARIMA" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -185,8 +185,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -203,21 +203,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -229,17 +229,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/arima/hdama/cache_as_ram_auto.c b/src/mainboard/arima/hdama/cache_as_ram_auto.c index fe19502543..a9a8a79333 100644 --- a/src/mainboard/arima/hdama/cache_as_ram_auto.c +++ b/src/mainboard/arima/hdama/cache_as_ram_auto.c @@ -96,7 +96,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -148,7 +148,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -186,7 +186,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) init_cpus(cpu_init_detectedx); } - pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/arima/hdama/irq_tables.c b/src/mainboard/arima/hdama/irq_tables.c index add22b4e03..2ca98066d0 100644 --- a/src/mainboard/arima/hdama/irq_tables.c +++ b/src/mainboard/arima/hdama/irq_tables.c @@ -18,7 +18,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT table entries */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT table entries */ IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/artecgroup/dbe61/Config.lb b/src/mainboard/artecgroup/dbe61/Config.lb index e00c21f5f3..41c77e0243 100644 --- a/src/mainboard/artecgroup/dbe61/Config.lb +++ b/src/mainboard/artecgroup/dbe61/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,13 +14,13 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -36,7 +36,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -58,7 +58,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds # mainboardinit ./failover.inc end diff --git a/src/mainboard/artecgroup/dbe61/Options.lb b/src/mainboard/artecgroup/dbe61/Options.lb index 8ac10de49e..3fa9ae27ce 100644 --- a/src/mainboard/artecgroup/dbe61/Options.lb +++ b/src/mainboard/artecgroup/dbe61/Options.lb @@ -1,59 +1,59 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -65,17 +65,17 @@ default CONFIG_VIDEO_MB=8 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -85,58 +85,58 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=3 -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=3 +default CONFIG_PIRQ_ROUTE=1 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 default CONFIG_USE_PRINTK_IN_CAR=1 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -146,21 +146,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -172,13 +172,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/artecgroup/dbe61/irq_tables.c b/src/mainboard/artecgroup/dbe61/irq_tables.c index b42c4b514e..87931ae3c5 100644 --- a/src/mainboard/artecgroup/dbe61/irq_tables.c +++ b/src/mainboard/artecgroup/dbe61/irq_tables.c @@ -44,7 +44,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -54,7 +54,7 @@ const struct irq_routing_table intel_irq_routing_table = { {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ + /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ diff --git a/src/mainboard/asi/mb_5blgp/Config.lb b/src/mainboard/asi/mb_5blgp/Config.lb index 9f66182167..08010fa236 100644 --- a/src/mainboard/asi/mb_5blgp/Config.lb +++ b/src/mainboard/asi/mb_5blgp/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asi/mb_5blgp/Options.lb b/src/mainboard/asi/mb_5blgp/Options.lb index 870f3b80f9..f5854b3b7f 100644 --- a/src/mainboard/asi/mb_5blgp/Options.lb +++ b/src/mainboard/asi/mb_5blgp/Options.lb @@ -18,45 +18,45 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 @@ -64,7 +64,7 @@ uses CONFIG_VIDEO_MB uses CONFIG_SPLASH_GRAPHIC uses CONFIG_GX1_VIDEO uses CONFIG_GX1_VIDEOMODE -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE ## Enable VGA with a splash screen (only 640x480 to run on most monitors). ## We want to support up to 1024x768@16 so we need 2MiB video memory. @@ -74,34 +74,34 @@ default CONFIG_GX1_VIDEOMODE = 0 default CONFIG_SPLASH_GRAPHIC = 1 default CONFIG_VIDEO_MB = 2 -default ROM_SIZE = 256 * 1024 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default PIRQ_ROUTE = 1 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_PIRQ_ROUTE = 1 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_OPTION_TABLE = 0 -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_OPTION_TABLE = 0 +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc " -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc " +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 # # CBFS diff --git a/src/mainboard/asi/mb_5blgp/auto.c b/src/mainboard/asi/mb_5blgp/auto.c index 962691d8ac..60c8dd7c1a 100644 --- a/src/mainboard/asi/mb_5blgp/auto.c +++ b/src/mainboard/asi/mb_5blgp/auto.c @@ -36,7 +36,7 @@ static void main(unsigned long bist) { - pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asi/mb_5blgp/irq_tables.c b/src/mainboard/asi/mb_5blgp/irq_tables.c index fe39ee86bf..79e9a88332 100644 --- a/src/mainboard/asi/mb_5blgp/irq_tables.c +++ b/src/mainboard/asi/mb_5blgp/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x12 << 3) | 0x0, /* Interrupt router device */ 0x8800, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/asi/mb_5blmp/Config.lb b/src/mainboard/asi/mb_5blmp/Config.lb index 6697a42bfa..f0008f7a65 100644 --- a/src/mainboard/asi/mb_5blmp/Config.lb +++ b/src/mainboard/asi/mb_5blmp/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,7 +14,7 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end @@ -22,22 +22,22 @@ end ## Romcc output ## # makerule ./failover.E -# depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" -# action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +# depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" +# action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" # end # # makerule ./failover.inc -# depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" -# action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +# depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" +# action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" # end makerule ./auto.E - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -51,7 +51,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -73,7 +73,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -# if USE_FALLBACK_IMAGE +# if CONFIG_USE_FALLBACK_IMAGE # ldscript /arch/i386/lib/failover.lds # mainboardinit ./failover.inc # end diff --git a/src/mainboard/asi/mb_5blmp/Options.lb b/src/mainboard/asi/mb_5blmp/Options.lb index c1ea8c4e24..de9cd83c43 100644 --- a/src/mainboard/asi/mb_5blmp/Options.lb +++ b/src/mainboard/asi/mb_5blmp/Options.lb @@ -1,52 +1,52 @@ -uses HAVE_PIRQ_TABLE +uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_CBFS -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESS uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 # uses CONFIG_CONSOLE_VGA # uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256 * 1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256 * 1024 ### ### Build options @@ -55,12 +55,12 @@ default ROM_SIZE = 256 * 1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -70,49 +70,49 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=5 # TODO? -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=5 # TODO? +default CONFIG_PIRQ_ROUTE=1 ## ## Build code to export a CMOS option table ## -# default HAVE_OPTION_TABLE=0 +# default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -# default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +# default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -122,21 +122,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -148,13 +148,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=9 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 # VGA Console # default CONFIG_CONSOLE_VGA=1 diff --git a/src/mainboard/asi/mb_5blmp/auto.c b/src/mainboard/asi/mb_5blmp/auto.c index 8e8b61c717..a98d640acc 100644 --- a/src/mainboard/asi/mb_5blmp/auto.c +++ b/src/mainboard/asi/mb_5blmp/auto.c @@ -38,7 +38,7 @@ static void main(unsigned long bist) { /* Initialize the serial console. */ - pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/asus/a8n_e/Config.lb b/src/mainboard/asus/a8n_e/Config.lb index 065a7ab7cb..72380d9e8a 100644 --- a/src/mainboard/asus/a8n_e/Config.lb +++ b/src/mainboard/asus/a8n_e/Config.lb @@ -21,36 +21,36 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end driver mainboard.o # Needed by irq_tables and mptable and acpi_tables. object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -60,8 +60,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/amd/car/cache_as_ram.lds end -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -69,7 +69,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -81,24 +81,24 @@ end mainboardinit southbridge/nvidia/ck804/id.inc ldscript /southbridge/nvidia/ck804/id.lds # ROMSTRAP table for CK804. -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end end mainboardinit cpu/amd/car/cache_as_ram.inc -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/asus/a8n_e/Options.lb b/src/mainboard/asus/a8n_e/Options.lb index 5f4c65715e..4682869577 100644 --- a/src/mainboard/asus/a8n_e/Options.lb +++ b/src/mainboard/asus/a8n_e/Options.lb @@ -19,153 +19,153 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_CONSOLE_BTEXT -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_MEM_TRAIN_SEQ +uses CONFIG_WAIT_BEFORE_CPUS_INIT +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_LB_MEM_TOPK uses CONFIG_USE_PRINTK_IN_CAR -default ROM_SIZE = 512 * 1024 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 252 * 1024 -default FAILOVER_SIZE = 4 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_FAILOVER_BOOT = 1 -default HAVE_HARD_RESET = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 13 -default HAVE_MP_TABLE = 1 -default HAVE_OPTION_TABLE = 1 +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 252 * 1024 +default CONFIG_FAILOVER_SIZE = 4 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_FAILOVER_BOOT = 1 +default CONFIG_HAVE_HARD_RESET = 1 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 13 +default CONFIG_HAVE_MP_TABLE = 1 +default CONFIG_HAVE_OPTION_TABLE = 1 # Move the default coreboot CMOS range off of AMD RTC registers. -default LB_CKS_RANGE_START = 49 -default LB_CKS_RANGE_END = 122 -default LB_CKS_LOC = 123 +default CONFIG_LB_CKS_RANGE_START = 49 +default CONFIG_LB_CKS_RANGE_END = 122 +default CONFIG_LB_CKS_LOC = 123 # SMP support (only worry about 2 micro processors). default CONFIG_SMP = 1 default CONFIG_MAX_CPUS = 2 default CONFIG_MAX_PHYSICAL_CPUS = 1 default CONFIG_LOGICAL_CPUS = 1 # 1G memory hole. -default HW_MEM_HOLE_SIZEK = 0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 # HT Unit ID offset, default is 1, the typical one. -default HT_CHAIN_UNITID_BASE = 0 +default CONFIG_HT_CHAIN_UNITID_BASE = 0 # Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default HT_CHAIN_END_UNITID_BASE = 0x10 +# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x10 # Make the SB HT chain on bus 0, default is not (0). -default SB_HT_CHAIN_ON_BUS0 = 2 +default CONFIG_SB_HT_CHAIN_ON_BUS0 = 2 # Only offset for SB chain?, default is yes(1). -default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 # default CONFIG_CONSOLE_BTEXT = 1 # BTEXT console default CONFIG_CONSOLE_VGA = 1 # For VGA console default CONFIG_PCI_ROM_RUN = 1 # For VGA console -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xc8000 -default DCACHE_RAM_SIZE = 32 * 1024 -default DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xc8000 +default CONFIG_DCACHE_RAM_SIZE = 32 * 1024 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024 default CONFIG_USE_INIT = 0 default CONFIG_AP_CODE_IN_CAR = 0 -default MEM_TRAIN_SEQ = 2 -default WAIT_BEFORE_CPUS_INIT = 0 -# default ENABLE_APIC_EXT_ID = 0 -# default APIC_ID_OFFSET = 0x10 -# default LIFT_BSP_APIC_ID = 0 +default CONFIG_MEM_TRAIN_SEQ = 2 +default CONFIG_WAIT_BEFORE_CPUS_INIT = 0 +# default CONFIG_ENABLE_APIC_EXT_ID = 0 +# default CONFIG_APIC_ID_OFFSET = 0x10 +# default CONFIG_LIFT_BSP_APIC_ID = 0 # default CONFIG_PCI_64BIT_PREF_MEM = 1 default CONFIG_IOAPIC = 1 -default MAINBOARD_PART_NUMBER = "A8N-E" -default MAINBOARD_VENDOR = "ASUS" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 +default CONFIG_MAINBOARD_PART_NUMBER = "A8N-E" +default CONFIG_MAINBOARD_VENDOR = "ASUS" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 # Only use the option table in a normal image. -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE) -default _RAMBASE = 0x00004000 +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE) +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_GDB_STUB = 0 default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 -default DEFAULT_CONSOLE_LOGLEVEL = 8 -default MAXIMUM_CONSOLE_LOGLEVEL = 8 -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" # # CBFS diff --git a/src/mainboard/asus/a8n_e/cache_as_ram_auto.c b/src/mainboard/asus/a8n_e/cache_as_ram_auto.c index 1e02e6e0be..a45d8d7966 100644 --- a/src/mainboard/asus/a8n_e/cache_as_ram_auto.c +++ b/src/mainboard/asus/a8n_e/cache_as_ram_auto.c @@ -50,7 +50,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" -#if USE_FAILOVER_IMAGE == 0 +#if CONFIG_USE_FAILOVER_IMAGE == 0 /* Used by ck894_early_setup(). */ #define CK804_NUM 1 @@ -99,10 +99,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#endif /* USE_FAILOVER_IMAGE */ +#endif /* CONFIG_USE_FAILOVER_IMAGE */ -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) \ - || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) \ + || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -166,7 +166,7 @@ normal_image: fallback_image: -#if HAVE_FAILOVER_BOOT == 1 +#if CONFIG_HAVE_FAILOVER_BOOT == 1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ @@ -175,27 +175,27 @@ fallback_image: ; } -#endif /* ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) ... */ +#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) ... */ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT == 1 -#if USE_FAILOVER_IMAGE == 1 +#if CONFIG_HAVE_FAILOVER_BOOT == 1 +#if CONFIG_USE_FAILOVER_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE == 0 +#if CONFIG_USE_FAILOVER_IMAGE == 0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { @@ -215,7 +215,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx); it8712f_24mhz_clkin(); - it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE); + it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -266,4 +266,4 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } -#endif /* USE_FAILOVER_IMAGE */ +#endif /* CONFIG_USE_FAILOVER_IMAGE */ diff --git a/src/mainboard/asus/a8v-e_se/Config.lb b/src/mainboard/asus/a8v-e_se/Config.lb index a53b262d16..242c104eac 100644 --- a/src/mainboard/asus/a8v-e_se/Config.lb +++ b/src/mainboard/asus/a8v-e_se/Config.lb @@ -20,42 +20,42 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1 arch i386 end driver mainboard.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o makerule dsdt.c - depends "$(MAINBOARD)/dsdt.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.asl" + depends "$(CONFIG_MAINBOARD)/dsdt.asl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o end -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds mainboardinit southbridge/via/k8t890/romstrap.inc @@ -71,7 +71,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/amd/car/cache_as_ram.lds end -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -81,7 +81,7 @@ end mainboardinit cpu/amd/car/cache_as_ram.inc -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/asus/a8v-e_se/Options.lb b/src/mainboard/asus/a8v-e_se/Options.lb index a471b418b2..75c404dd92 100644 --- a/src/mainboard/asus/a8v-e_se/Options.lb +++ b/src/mainboard/asus/a8v-e_se/Options.lb @@ -17,156 +17,156 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -# uses USE_OPTION_TABLE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +# uses CONFIG_USE_OPTION_TABLE # uses CONFIG_LB_MEM_TOPK -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN # bx_b001- uses K8_HW_MEM_HOLE_SIZEK -uses K8_HT_FREQ_1G_SUPPORT -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_K8_HT_FREQ_1G_SUPPORT +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE # bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY # bx_b005+ -uses SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_ON_BUS0 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_USE_PRINTK_IN_CAR -default ROM_SIZE = 512 * 1024 -default FALLBACK_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_HARD_RESET = 0 -default HAVE_PIRQ_TABLE = 0 -default IRQ_SLOT_COUNT = 11 # FIXME? -default HAVE_MP_TABLE = 1 -default HAVE_OPTION_TABLE = 0 # FIXME +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_FALLBACK_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_HAVE_PIRQ_TABLE = 0 +default CONFIG_IRQ_SLOT_COUNT = 11 # FIXME? +default CONFIG_HAVE_MP_TABLE = 1 +default CONFIG_HAVE_OPTION_TABLE = 0 # FIXME # Move the default coreboot CMOS range off of AMD RTC registers. -default LB_CKS_RANGE_START = 49 -default LB_CKS_RANGE_END = 122 -default LB_CKS_LOC = 123 +default CONFIG_LB_CKS_RANGE_START = 49 +default CONFIG_LB_CKS_RANGE_END = 122 +default CONFIG_LB_CKS_LOC = 123 default CONFIG_SMP = 1 default CONFIG_MAX_CPUS = 2 default CONFIG_MAX_PHYSICAL_CPUS = 1 default CONFIG_LOGICAL_CPUS = 1 -default HAVE_ACPI_TABLES = 1 +default CONFIG_HAVE_ACPI_TABLES = 1 # 1G memory hole # bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000 # Opteron K8 1G HT support -default K8_HT_FREQ_1G_SUPPORT = 1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1 # HT Unit ID offset, default is 1, the typical one. -default HT_CHAIN_UNITID_BASE = 0x0 +default CONFIG_HT_CHAIN_UNITID_BASE = 0x0 # Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default HT_CHAIN_END_UNITID_BASE = 0x0 +# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 # Make the SB HT chain on bus 0, default is not (0). # bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2 # bx_b005+ make the SB HT chain on bus 0. -default SB_HT_CHAIN_ON_BUS0 = 1 +default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1 # Only offset for SB chain?, default is yes(1). -default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 default CONFIG_CONSOLE_VGA = 1 # Needed for VGA. default CONFIG_PCI_ROM_RUN = 1 # Needed for VGA. -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xcc000 -default DCACHE_RAM_SIZE = 0x4000 -default DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xcc000 +default CONFIG_DCACHE_RAM_SIZE = 0x4000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 default CONFIG_USE_INIT = 0 -default ENABLE_APIC_EXT_ID = 0 -default APIC_ID_OFFSET = 0x10 -default LIFT_BSP_APIC_ID = 0 +default CONFIG_ENABLE_APIC_EXT_ID = 0 +default CONFIG_APIC_ID_OFFSET = 0x10 +default CONFIG_LIFT_BSP_APIC_ID = 0 default CONFIG_IOAPIC = 1 -default MAINBOARD_VENDOR = "ASUS" -default MAINBOARD_PART_NUMBER = "A8V-E SE" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -# default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME -default ROM_IMAGE_SIZE = 64 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 256 * 1024 +default CONFIG_MAINBOARD_VENDOR = "ASUS" +default CONFIG_MAINBOARD_PART_NUMBER = "A8V-E SE" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 +# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 256 * 1024 # More 1M for pgtbl. # default CONFIG_LB_MEM_TOPK = 2048 -default _RAMBASE = 0x00004000 -# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_RAMBASE = 0x00004000 +# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_GDB_STUB = 0 default CONFIG_USE_PRINTK_IN_CAR = 1 default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 8 -default MAXIMUM_CONSOLE_LOGLEVEL = 8 -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" # # CBFS # diff --git a/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c b/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c index 0a8ca60a8b..b76d011910 100644 --- a/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c +++ b/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c @@ -178,7 +178,7 @@ void sio_init(void) pnp_exit_ext_func_mode(GPIO_DEV); } -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -187,7 +187,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) unsigned last_boot_normal_x = 1; sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); enable_rom_decode(); @@ -232,7 +232,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -251,11 +251,11 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) unsigned bsp_apicid = 0; int needs_reset = 0; struct sys_info *sysinfo = - (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); char *p; sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); enable_rom_decode(); diff --git a/src/mainboard/asus/m2v-mx_se/Config.lb b/src/mainboard/asus/m2v-mx_se/Config.lb index 76935320f0..c7f7d6e51a 100644 --- a/src/mainboard/asus/m2v-mx_se/Config.lb +++ b/src/mainboard/asus/m2v-mx_se/Config.lb @@ -20,18 +20,18 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o makerule dsdt.c - depends "$(MAINBOARD)/dsdt.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.asl" + depends "$(CONFIG_MAINBOARD)/dsdt.asl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o @@ -39,19 +39,19 @@ end if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds mainboardinit southbridge/via/k8t890/romstrap.inc @@ -67,7 +67,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/amd/car/cache_as_ram.lds end -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ end mainboardinit cpu/amd/car/cache_as_ram.inc -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/asus/m2v-mx_se/Options.lb b/src/mainboard/asus/m2v-mx_se/Options.lb index 8f388d5219..d1a08e2c7f 100644 --- a/src/mainboard/asus/m2v-mx_se/Options.lb +++ b/src/mainboard/asus/m2v-mx_se/Options.lb @@ -17,159 +17,159 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -# uses USE_OPTION_TABLE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +# uses CONFIG_USE_OPTION_TABLE uses CONFIG_LB_MEM_TOPK -uses HAVE_ACPI_TABLES -uses HAVE_MAINBOARD_RESOURCES -uses HAVE_ACPI_RESUME -uses HAVE_LOW_TABLES -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_MAINBOARD_RESOURCES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_HAVE_LOW_TABLES +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN # bx_b001- uses K8_HW_MEM_HOLE_SIZEK -uses K8_HT_FREQ_1G_SUPPORT -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_K8_HT_FREQ_1G_SUPPORT +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE # bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY # bx_b005+ -uses SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_ON_BUS0 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_USE_PRINTK_IN_CAR -default HAVE_FALLBACK_BOOT = 1 -default HAVE_HARD_RESET = 1 -default HAVE_PIRQ_TABLE = 0 -default IRQ_SLOT_COUNT = 11 # FIXME? -default HAVE_MP_TABLE = 0 -default HAVE_OPTION_TABLE = 0 # FIXME +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_HARD_RESET = 1 +default CONFIG_HAVE_PIRQ_TABLE = 0 +default CONFIG_IRQ_SLOT_COUNT = 11 # FIXME? +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_OPTION_TABLE = 0 # FIXME # Move the default coreboot CMOS range off of AMD RTC registers. -default LB_CKS_RANGE_START = 49 -default LB_CKS_RANGE_END = 122 -default LB_CKS_LOC = 123 +default CONFIG_LB_CKS_RANGE_START = 49 +default CONFIG_LB_CKS_RANGE_END = 122 +default CONFIG_LB_CKS_LOC = 123 default CONFIG_SMP = 1 default CONFIG_MAX_CPUS = 2 default CONFIG_MAX_PHYSICAL_CPUS = 1 default CONFIG_LOGICAL_CPUS = 1 -default HAVE_ACPI_TABLES = 1 -default HAVE_MAINBOARD_RESOURCES = 1 -default HAVE_LOW_TABLES = 0 -default HAVE_ACPI_RESUME = 1 +default CONFIG_HAVE_ACPI_TABLES = 1 +default CONFIG_HAVE_MAINBOARD_RESOURCES = 1 +default CONFIG_HAVE_LOW_TABLES = 0 +default CONFIG_HAVE_ACPI_RESUME = 1 # 1G memory hole # bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000 # Opteron K8 1G HT support -default K8_HT_FREQ_1G_SUPPORT = 1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1 # HT Unit ID offset, default is 1, the typical one. -default HT_CHAIN_UNITID_BASE = 0x0 +default CONFIG_HT_CHAIN_UNITID_BASE = 0x0 # Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default HT_CHAIN_END_UNITID_BASE = 0x0 +# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 # Make the SB HT chain on bus 0, default is not (0). # bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2 # bx_b005+ make the SB HT chain on bus 0. -default SB_HT_CHAIN_ON_BUS0 = 1 +default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1 # Only offset for SB chain?, default is yes(1). -default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 default CONFIG_CONSOLE_VGA = 1 # Needed for VGA. default CONFIG_PCI_ROM_RUN = 0 # Needed for VGA. -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xcc000 -default DCACHE_RAM_SIZE = 0x4000 -default DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xcc000 +default CONFIG_DCACHE_RAM_SIZE = 0x4000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 default CONFIG_USE_INIT = 0 -default ENABLE_APIC_EXT_ID = 0 -default APIC_ID_OFFSET = 0x10 -default LIFT_BSP_APIC_ID = 0 +default CONFIG_ENABLE_APIC_EXT_ID = 0 +default CONFIG_APIC_ID_OFFSET = 0x10 +default CONFIG_LIFT_BSP_APIC_ID = 0 default CONFIG_IOAPIC = 1 -default MAINBOARD_VENDOR = "ASUS" -default MAINBOARD_PART_NUMBER = "M2V-MX SE" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -# default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 256 * 1024 +default CONFIG_MAINBOARD_VENDOR = "ASUS" +default CONFIG_MAINBOARD_PART_NUMBER = "M2V-MX SE" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 +# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 256 * 1024 # More 1M for pgtbl. default CONFIG_LB_MEM_TOPK = 32768 # to 1MB -default _RAMBASE = 0x1F00000 -# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_RAMBASE = 0x1F00000 +# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_GDB_STUB = 0 default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" # # CBFS # diff --git a/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c b/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c index 15dcda5ec1..e5d18e1c94 100644 --- a/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c +++ b/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c @@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus); /* If we want to wait for core1 done before DQS training, set it to 0. */ #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -183,12 +183,12 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) unsigned bsp_apicid = 0; int needs_reset = 0; struct sys_info *sysinfo = - (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); char *p; u8 reg; sio_init(); - it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE); + it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); it8712f_enable_3vsbsw(); uart_init(); diff --git a/src/mainboard/asus/m2v-mx_se/mainboard.c b/src/mainboard/asus/m2v-mx_se/mainboard.c index f6bf656e50..c68fe6174b 100644 --- a/src/mainboard/asus/m2v-mx_se/mainboard.c +++ b/src/mainboard/asus/m2v-mx_se/mainboard.c @@ -25,11 +25,11 @@ int add_mainboard_resources(struct lb_memory *mem) { -#if HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME == 1 lb_add_memory_range(mem, LB_MEM_RESERVED, - _RAMBASE, ((CONFIG_LB_MEM_TOPK<<10) - _RAMBASE)); + CONFIG_RAMBASE, ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_RAMBASE)); lb_add_memory_range(mem, LB_MEM_RESERVED, - DCACHE_RAM_BASE, DCACHE_RAM_SIZE); + CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); #endif return 0; } diff --git a/src/mainboard/asus/mew-am/Config.lb b/src/mainboard/asus/mew-am/Config.lb index 76ddff64a8..c6486831df 100644 --- a/src/mainboard/asus/mew-am/Config.lb +++ b/src/mainboard/asus/mew-am/Config.lb @@ -18,40 +18,40 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" # Note: The -mcpu=p2 is important, or else... 'too few registers'. - action "../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + action "../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" # Note: The -mcpu=p2 is important, or else... 'too few registers'. - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -61,7 +61,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/mew-am/Options.lb b/src/mainboard/asus/mew-am/Options.lb index 95be45a13d..c0837b2dda 100644 --- a/src/mainboard/asus/mew-am/Options.lb +++ b/src/mainboard/asus/mew-am/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 512 * 1024 # Override this in targets/*/Config.lb. -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 512 * 1024 # Override this in targets/*/Config.lb. +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. -default MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. default CONFIG_CONSOLE_VGA = 1 # Override this in targets/*/Config.lb. default CONFIG_PCI_ROM_RUN = 1 # Override this in targets/*/Config.lb. diff --git a/src/mainboard/asus/mew-am/auto.c b/src/mainboard/asus/mew-am/auto.c index ea09d6c371..05a163d779 100644 --- a/src/mainboard/asus/mew-am/auto.c +++ b/src/mainboard/asus/mew-am/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE); + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/mew-am/irq_tables.c b/src/mainboard/asus/mew-am/irq_tables.c index 84d738dd2d..e07ee20b96 100644 --- a/src/mainboard/asus/mew-am/irq_tables.c +++ b/src/mainboard/asus/mew-am/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x1f << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/asus/mew-vm/Config.lb b/src/mainboard/asus/mew-vm/Config.lb index 44439707dd..60f4e152b6 100644 --- a/src/mainboard/asus/mew-vm/Config.lb +++ b/src/mainboard/asus/mew-vm/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,29 +14,29 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -50,7 +50,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -72,7 +72,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/mew-vm/Options.lb b/src/mainboard/asus/mew-vm/Options.lb index fa0eedc074..71f854d127 100644 --- a/src/mainboard/asus/mew-vm/Options.lb +++ b/src/mainboard/asus/mew-vm/Options.lb @@ -1,50 +1,50 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_IDE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 512*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 512*1024 ### ### Build options @@ -53,28 +53,28 @@ default ROM_SIZE = 512*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_FALLBACK_BOOT = 1 ## ## no MP table ## -default HAVE_MP_TABLE = 0 +default CONFIG_HAVE_MP_TABLE = 0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET = 0 +default CONFIG_HAVE_HARD_RESET = 0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 11 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 11 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE = 0 +default CONFIG_HAVE_OPTION_TABLE = 0 ## IDE Support default CONFIG_IDE = 1 @@ -83,36 +83,36 @@ default CONFIG_IDE = 1 ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -122,21 +122,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -148,13 +148,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=9 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 default CONFIG_UDELAY_TSC=1 diff --git a/src/mainboard/asus/mew-vm/auto.c b/src/mainboard/asus/mew-vm/auto.c index 721f6116b1..f53083f2a5 100644 --- a/src/mainboard/asus/mew-vm/auto.c +++ b/src/mainboard/asus/mew-vm/auto.c @@ -58,7 +58,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - lpc47b272_enable_serial(SERIAL_DEV, TTYS0_BASE); + lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/asus/p2b-d/Config.lb b/src/mainboard/asus/p2b-d/Config.lb index cb886bf914..a0486cd209 100644 --- a/src/mainboard/asus/p2b-d/Config.lb +++ b/src/mainboard/asus/p2b-d/Config.lb @@ -18,37 +18,37 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -58,7 +58,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/p2b-d/Options.lb b/src/mainboard/asus/p2b-d/Options.lb index 946cc8a017..2409c14956 100644 --- a/src/mainboard/asus/p2b-d/Options.lb +++ b/src/mainboard/asus/p2b-d/Options.lb @@ -18,89 +18,89 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_SMP uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 1 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 1 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 default CONFIG_SMP = 1 default CONFIG_MAX_CPUS = 2 default CONFIG_IOAPIC = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 default CONFIG_CBFS = 0 diff --git a/src/mainboard/asus/p2b-d/auto.c b/src/mainboard/asus/p2b-d/auto.c index f25e34e578..747ba77b35 100644 --- a/src/mainboard/asus/p2b-d/auto.c +++ b/src/mainboard/asus/p2b-d/auto.c @@ -57,7 +57,7 @@ static void main(unsigned long bist) enable_lapic(); /* FIXME? */ } - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-d/irq_tables.c b/src/mainboard/asus/p2b-d/irq_tables.c index e8c6ff197d..05a465cc94 100644 --- a/src/mainboard/asus/p2b-d/irq_tables.c +++ b/src/mainboard/asus/p2b-d/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x04 << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/asus/p2b-ds/Config.lb b/src/mainboard/asus/p2b-ds/Config.lb index 8d83be9ef1..2b6599458a 100644 --- a/src/mainboard/asus/p2b-ds/Config.lb +++ b/src/mainboard/asus/p2b-ds/Config.lb @@ -18,37 +18,37 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -58,7 +58,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/p2b-ds/Options.lb b/src/mainboard/asus/p2b-ds/Options.lb index f907eac3d8..c069939fc5 100644 --- a/src/mainboard/asus/p2b-ds/Options.lb +++ b/src/mainboard/asus/p2b-ds/Options.lb @@ -18,89 +18,89 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_SMP uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 1 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 1 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 default CONFIG_SMP = 1 default CONFIG_MAX_CPUS = 2 default CONFIG_IOAPIC = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/asus/p2b-ds/auto.c b/src/mainboard/asus/p2b-ds/auto.c index 95cfa64765..aaa7ae94e6 100644 --- a/src/mainboard/asus/p2b-ds/auto.c +++ b/src/mainboard/asus/p2b-ds/auto.c @@ -57,7 +57,7 @@ static void main(unsigned long bist) enable_lapic(); /* FIXME? */ } - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-ds/irq_tables.c b/src/mainboard/asus/p2b-ds/irq_tables.c index bc3a64741c..29b6f54885 100644 --- a/src/mainboard/asus/p2b-ds/irq_tables.c +++ b/src/mainboard/asus/p2b-ds/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x04 << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/asus/p2b-f/Config.lb b/src/mainboard/asus/p2b-f/Config.lb index 5bef9da403..f6995beedf 100644 --- a/src/mainboard/asus/p2b-f/Config.lb +++ b/src/mainboard/asus/p2b-f/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/p2b-f/Options.lb b/src/mainboard/asus/p2b-f/Options.lb index 2641e766df..4d927e1fb8 100644 --- a/src/mainboard/asus/p2b-f/Options.lb +++ b/src/mainboard/asus/p2b-f/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/asus/p2b-f/auto.c b/src/mainboard/asus/p2b-f/auto.c index 0c81b7f0d0..191c9ffd4c 100644 --- a/src/mainboard/asus/p2b-f/auto.c +++ b/src/mainboard/asus/p2b-f/auto.c @@ -57,7 +57,7 @@ static void main(unsigned long bist) early_mtrr_init(); /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-f/irq_tables.c b/src/mainboard/asus/p2b-f/irq_tables.c index bbdf7bd9ae..f33c8cab55 100644 --- a/src/mainboard/asus/p2b-f/irq_tables.c +++ b/src/mainboard/asus/p2b-f/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x04 << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/asus/p2b/Config.lb b/src/mainboard/asus/p2b/Config.lb index 2b54440f30..ef04497653 100644 --- a/src/mainboard/asus/p2b/Config.lb +++ b/src/mainboard/asus/p2b/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/p2b/Options.lb b/src/mainboard/asus/p2b/Options.lb index e6bd850cbd..db9fcecb29 100644 --- a/src/mainboard/asus/p2b/Options.lb +++ b/src/mainboard/asus/p2b/Options.lb @@ -18,83 +18,83 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/asus/p2b/auto.c b/src/mainboard/asus/p2b/auto.c index 2e60b1c526..1b5891e519 100644 --- a/src/mainboard/asus/p2b/auto.c +++ b/src/mainboard/asus/p2b/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b/irq_tables.c b/src/mainboard/asus/p2b/irq_tables.c index f957dc878d..e0daa56076 100644 --- a/src/mainboard/asus/p2b/irq_tables.c +++ b/src/mainboard/asus/p2b/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x04 << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/asus/p3b-f/Config.lb b/src/mainboard/asus/p3b-f/Config.lb index 1b752437c4..67b4b39627 100644 --- a/src/mainboard/asus/p3b-f/Config.lb +++ b/src/mainboard/asus/p3b-f/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/asus/p3b-f/Options.lb b/src/mainboard/asus/p3b-f/Options.lb index 2641e766df..4d927e1fb8 100644 --- a/src/mainboard/asus/p3b-f/Options.lb +++ b/src/mainboard/asus/p3b-f/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/asus/p3b-f/auto.c b/src/mainboard/asus/p3b-f/auto.c index b4880d556b..e300bf6794 100644 --- a/src/mainboard/asus/p3b-f/auto.c +++ b/src/mainboard/asus/p3b-f/auto.c @@ -57,7 +57,7 @@ static void main(unsigned long bist) early_mtrr_init(); /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p3b-f/irq_tables.c b/src/mainboard/asus/p3b-f/irq_tables.c index 47ef7f2f70..2cc0565431 100644 --- a/src/mainboard/asus/p3b-f/irq_tables.c +++ b/src/mainboard/asus/p3b-f/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x04 << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/axus/tc320/Config.lb b/src/mainboard/axus/tc320/Config.lb index 68978705ce..54aae5352e 100644 --- a/src/mainboard/axus/tc320/Config.lb +++ b/src/mainboard/axus/tc320/Config.lb @@ -18,36 +18,36 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -57,7 +57,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/axus/tc320/Options.lb b/src/mainboard/axus/tc320/Options.lb index 0003852a59..3fc2088f03 100644 --- a/src/mainboard/axus/tc320/Options.lb +++ b/src/mainboard/axus/tc320/Options.lb @@ -18,45 +18,45 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 @@ -64,7 +64,7 @@ uses CONFIG_VIDEO_MB uses CONFIG_SPLASH_GRAPHIC uses CONFIG_GX1_VIDEO uses CONFIG_GX1_VIDEOMODE -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE ## Enable VGA with a splash screen (only 640x480 to run on most monitors). ## We want to support up to 1024x768@16 so we need 2MiB video memory. @@ -74,34 +74,34 @@ default CONFIG_GX1_VIDEOMODE = 0 default CONFIG_SPLASH_GRAPHIC = 1 default CONFIG_VIDEO_MB = 2 -default ROM_SIZE = 256 * 1024 -default MAINBOARD_VENDOR = "AXUS" -default MAINBOARD_PART_NUMBER = "TC320" -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_MAINBOARD_VENDOR = "AXUS" +default CONFIG_MAINBOARD_PART_NUMBER = "TC320" +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 2 # Soldered NIC, internal USB, no real slots -default PIRQ_ROUTE = 1 -default HAVE_OPTION_TABLE = 0 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 2 # Soldered NIC, internal USB, no real slots +default CONFIG_PIRQ_ROUTE = 1 +default CONFIG_HAVE_OPTION_TABLE = 0 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc " -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc " +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 6 -default MAXIMUM_CONSOLE_LOGLEVEL = 6 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6 # # CBFS diff --git a/src/mainboard/axus/tc320/auto.c b/src/mainboard/axus/tc320/auto.c index 444771958c..ad80e5ce70 100644 --- a/src/mainboard/axus/tc320/auto.c +++ b/src/mainboard/axus/tc320/auto.c @@ -37,7 +37,7 @@ static void main(unsigned long bist) { - pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/axus/tc320/irq_tables.c b/src/mainboard/axus/tc320/irq_tables.c index 8a8ada270a..38e1567942 100644 --- a/src/mainboard/axus/tc320/irq_tables.c +++ b/src/mainboard/axus/tc320/irq_tables.c @@ -66,7 +66,7 @@ const struct irq_routing_table intel_irq_routing_table = { .signature = PIRQ_SIGNATURE, /* PIRQ signature */ .version = PIRQ_VERSION, /* PIRQ version */ - .size = 32 + 16 * IRQ_SLOT_COUNT,/* Max. IRQ_SLOT_COUNT devices */ + .size = 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. CONFIG_IRQ_SLOT_COUNT devices */ .rtr_bus = 0x00, /* Interrupt router bus */ .rtr_devfn = (0x12 << 3) | 0x0, /* Interrupt router device */ .exclusive_irqs = IRQ_DEVOTED_TO_PCI, /* IRQs devoted to PCI */ diff --git a/src/mainboard/azza/pt-6ibd/Config.lb b/src/mainboard/azza/pt-6ibd/Config.lb index 2c62f2ef25..fce9062c01 100644 --- a/src/mainboard/azza/pt-6ibd/Config.lb +++ b/src/mainboard/azza/pt-6ibd/Config.lb @@ -18,37 +18,37 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -58,7 +58,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/azza/pt-6ibd/Options.lb b/src/mainboard/azza/pt-6ibd/Options.lb index 2641e766df..4d927e1fb8 100644 --- a/src/mainboard/azza/pt-6ibd/Options.lb +++ b/src/mainboard/azza/pt-6ibd/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/azza/pt-6ibd/auto.c b/src/mainboard/azza/pt-6ibd/auto.c index 8f64154f9e..24359a1038 100644 --- a/src/mainboard/azza/pt-6ibd/auto.c +++ b/src/mainboard/azza/pt-6ibd/auto.c @@ -57,7 +57,7 @@ static void main(unsigned long bist) early_mtrr_init(); /* FIXME: It's a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/azza/pt-6ibd/irq_tables.c b/src/mainboard/azza/pt-6ibd/irq_tables.c index 5de013f197..f7ec127c0c 100644 --- a/src/mainboard/azza/pt-6ibd/irq_tables.c +++ b/src/mainboard/azza/pt-6ibd/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x07 << 3) | 0x0, /* Interrupt router device */ 0xc00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/bcom/winnet100/Config.lb b/src/mainboard/bcom/winnet100/Config.lb index bbd74bb076..7ea700dcfa 100644 --- a/src/mainboard/bcom/winnet100/Config.lb +++ b/src/mainboard/bcom/winnet100/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/bcom/winnet100/Options.lb b/src/mainboard/bcom/winnet100/Options.lb index 384d78ce0a..2d18d267dd 100644 --- a/src/mainboard/bcom/winnet100/Options.lb +++ b/src/mainboard/bcom/winnet100/Options.lb @@ -18,45 +18,45 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 @@ -64,7 +64,7 @@ uses CONFIG_VIDEO_MB uses CONFIG_SPLASH_GRAPHIC uses CONFIG_GX1_VIDEO uses CONFIG_GX1_VIDEOMODE -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE ## Enable VGA with a splash screen (only 640x480 to run on most monitors). ## We want to support up to 1024x768@16 so we need 2MiB video memory. @@ -74,34 +74,34 @@ default CONFIG_GX1_VIDEOMODE = 0 default CONFIG_SPLASH_GRAPHIC = 1 default CONFIG_VIDEO_MB = 2 -default ROM_SIZE = 256 * 1024 -default MAINBOARD_VENDOR = "BCOM" -default MAINBOARD_PART_NUMBER = "WinNET100" -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_MAINBOARD_VENDOR = "BCOM" +default CONFIG_MAINBOARD_PART_NUMBER = "WinNET100" +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 2 # Soldered NIC, internal USB, no real slots -default PIRQ_ROUTE = 1 -default HAVE_OPTION_TABLE = 0 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 2 # Soldered NIC, internal USB, no real slots +default CONFIG_PIRQ_ROUTE = 1 +default CONFIG_HAVE_OPTION_TABLE = 0 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc " -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc " +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 6 -default MAXIMUM_CONSOLE_LOGLEVEL = 6 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6 # # CBFS diff --git a/src/mainboard/bcom/winnet100/auto.c b/src/mainboard/bcom/winnet100/auto.c index 9880011670..51d847b976 100644 --- a/src/mainboard/bcom/winnet100/auto.c +++ b/src/mainboard/bcom/winnet100/auto.c @@ -38,7 +38,7 @@ static void main(unsigned long bist) { /* Initialize the serial console. */ - pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/bcom/winnet100/irq_tables.c b/src/mainboard/bcom/winnet100/irq_tables.c index 9f711d86d2..b0cbc92fe6 100644 --- a/src/mainboard/bcom/winnet100/irq_tables.c +++ b/src/mainboard/bcom/winnet100/irq_tables.c @@ -64,7 +64,7 @@ const struct irq_routing_table intel_irq_routing_table = { .signature = PIRQ_SIGNATURE, /* PIRQ signature */ .version = PIRQ_VERSION, /* PIRQ version */ - .size = 32 +16 * IRQ_SLOT_COUNT,/* Max. IRQ_SLOT_COUNT devices */ + .size = 32 +16 * CONFIG_IRQ_SLOT_COUNT,/* Max. CONFIG_IRQ_SLOT_COUNT devices */ .rtr_bus = 0x00, /* Interrupt router bus */ .rtr_devfn = (0x12 << 3) | 0x0, /* Interrupt router device */ .exclusive_irqs = IRQ_DEVOTED_TO_PCI, /* IRQs devoted to PCI */ diff --git a/src/mainboard/bcom/winnetp680/Config.lb b/src/mainboard/bcom/winnetp680/Config.lb index 29cf36d932..850f8e1326 100644 --- a/src/mainboard/bcom/winnetp680/Config.lb +++ b/src/mainboard/bcom/winnetp680/Config.lb @@ -19,40 +19,40 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_MP_TABLE object mptable.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_ACPI_TABLES object fadt.o object dsdt.o object acpi_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -62,7 +62,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/bcom/winnetp680/Options.lb b/src/mainboard/bcom/winnetp680/Options.lb index 446cf228b5..a6e1cfae00 100644 --- a/src/mainboard/bcom/winnetp680/Options.lb +++ b/src/mainboard/bcom/winnetp680/Options.lb @@ -19,46 +19,46 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 @@ -68,33 +68,33 @@ uses CONFIG_MAX_PCI_BUSES uses CONFIG_VIDEO_MB uses CONFIG_IOAPIC -default ROM_SIZE = 512 * 1024 +default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_IOAPIC = 0 default CONFIG_VIDEO_MB = 32 default CONFIG_CONSOLE_SERIAL8250 = 1 default CONFIG_PCI_ROM_RUN = 0 default CONFIG_CONSOLE_VGA = 0 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_HARD_RESET = 0 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 10 -default HAVE_ACPI_TABLES = 0 -default HAVE_OPTION_TABLE = 1 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = ROM_SIZE -default USE_FALLBACK_IMAGE = 1 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 10 +default CONFIG_HAVE_ACPI_TABLES = 0 +default CONFIG_HAVE_OPTION_TABLE = 1 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE +default CONFIG_USE_FALLBACK_IMAGE = 1 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector" +default CONFIG_HOSTCC = "gcc" ## ## Set this to the max PCI bus number you would ever use for PCI config I/O. diff --git a/src/mainboard/bcom/winnetp680/auto.c b/src/mainboard/bcom/winnetp680/auto.c index af78949118..01135f8b5c 100644 --- a/src/mainboard/bcom/winnetp680/auto.c +++ b/src/mainboard/bcom/winnetp680/auto.c @@ -99,7 +99,7 @@ static void main(unsigned long bist) w83697hf_set_clksel_48(SERIAL_DEV); - w83697hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/bcom/winnetp680/irq_tables.c b/src/mainboard/bcom/winnetp680/irq_tables.c index fef553e219..9037e344a2 100644 --- a/src/mainboard/bcom/winnetp680/irq_tables.c +++ b/src/mainboard/bcom/winnetp680/irq_tables.c @@ -24,7 +24,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x11 << 3) | 0x0, /* Interrupt router device */ 0x828, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/biostar/m6tba/Config.lb b/src/mainboard/biostar/m6tba/Config.lb index 75c6ae5588..6f3175f217 100644 --- a/src/mainboard/biostar/m6tba/Config.lb +++ b/src/mainboard/biostar/m6tba/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/biostar/m6tba/Options.lb b/src/mainboard/biostar/m6tba/Options.lb index 2641e766df..4d927e1fb8 100644 --- a/src/mainboard/biostar/m6tba/Options.lb +++ b/src/mainboard/biostar/m6tba/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/biostar/m6tba/auto.c b/src/mainboard/biostar/m6tba/auto.c index f68db56156..5a6244900e 100644 --- a/src/mainboard/biostar/m6tba/auto.c +++ b/src/mainboard/biostar/m6tba/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE); + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/biostar/m6tba/irq_tables.c b/src/mainboard/biostar/m6tba/irq_tables.c index ea01effd2b..b491510019 100644 --- a/src/mainboard/biostar/m6tba/irq_tables.c +++ b/src/mainboard/biostar/m6tba/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x07 << 3) | 0x0, /* Interrupt router device */ 0xc00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/broadcom/blast/Config.lb b/src/mainboard/broadcom/blast/Config.lb index 9aae740958..e82bc9cf30 100644 --- a/src/mainboard/broadcom/blast/Config.lb +++ b/src/mainboard/broadcom/blast/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -12,8 +12,8 @@ driver mainboard.o #dir /drivers/si/3114 -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object get_bus_conf.o object irq_tables.o end @@ -23,15 +23,15 @@ end if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -55,7 +55,7 @@ ldscript /cpu/x86/16bit/entry16.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -79,7 +79,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end @@ -209,14 +209,14 @@ chip northbridge/amd/amdk8/root_complex device pci 2.0 on end # USB 0x0223 device pci 2.1 on end # USB device pci 2.2 on end # USB - #when HT_CHAIN_END_UNITID_BASE (0,1) < HT_CHAIN_UNITID_BASE (6,,,,), + #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), chip drivers/pci/onboard device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address - # if HT_CHAIN_END_UNITID_BASE=0, it is 5, if HT_CHAIN_END_UNITID_BASE=1, it is 4 + # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4 register "rom_address" = "0xfff80000" end end - #when HT_CHAIN_END_UNITID_BASE > HT_CHAIN_UNITID_BASE (6, ,,,,) + #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) # chip drivers/pci/onboard # device pci 0.0 on end # fake, will be disabled # end diff --git a/src/mainboard/broadcom/blast/Options.lb b/src/mainboard/broadcom/blast/Options.lb index 752007572c..4f8e7b06d8 100644 --- a/src/mainboard/broadcom/blast/Options.lb +++ b/src/mainboard/broadcom/blast/Options.lb @@ -1,123 +1,123 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -129,27 +129,27 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console #default CONFIG_CONSOLE_VGA=1 #default CONFIG_PCI_ROM_RUN=1 #HT Unit ID offset -default HT_CHAIN_UNITID_BASE=0x6 +default CONFIG_HT_CHAIN_UNITID_BASE=0x6 #real SB Unit ID -default HT_CHAIN_END_UNITID_BASE=0x1 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1 #make the SB HT chain on bus 0 -default SB_HT_CHAIN_ON_BUS0=1 +default CONFIG_SB_HT_CHAIN_ON_BUS0=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## @@ -160,38 +160,38 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="blast" -default MAINBOARD_VENDOR="Broadcom" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 +default CONFIG_MAINBOARD_PART_NUMBER="blast" +default CONFIG_MAINBOARD_VENDOR="Broadcom" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -205,8 +205,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -223,21 +223,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -249,17 +249,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/broadcom/blast/cache_as_ram_auto.c b/src/mainboard/broadcom/blast/cache_as_ram_auto.c index 2a06555b76..f8eb8c8535 100644 --- a/src/mainboard/broadcom/blast/cache_as_ram_auto.c +++ b/src/mainboard/broadcom/blast/cache_as_ram_auto.c @@ -110,7 +110,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "northbridge/amd/amdk8/early_ht.c" @@ -161,14 +161,14 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x25); ; } -#endif /* USE_FALLBACK_IMAGE == 1 */ +#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -197,7 +197,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) } // post_code(0x32); - pc87417_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); // post_code(0x33); uart_init(); diff --git a/src/mainboard/broadcom/blast/get_bus_conf.c b/src/mainboard/broadcom/blast/get_bus_conf.c index b11d940399..b86292b0db 100644 --- a/src/mainboard/broadcom/blast/get_bus_conf.c +++ b/src/mainboard/broadcom/blast/get_bus_conf.c @@ -83,7 +83,7 @@ void get_bus_conf(void) dev = dev_find_slot(bus_bcm5785_1, PCI_DEVFN(0x0d,0)); if(dev) { bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); @@ -99,7 +99,7 @@ void get_bus_conf(void) dev = dev_find_slot(bus_bcm5780[0], PCI_DEVFN(sbdn2 + i - 1,0)); if(dev) { bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb b/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb index 8f440c4cab..8dcd0402cc 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb +++ b/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb b/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb index 2641e766df..4d927e1fb8 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb +++ b/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/auto.c b/src/mainboard/compaq/deskpro_en_sff_p600/auto.c index 032dd6f0d4..424f6f698b 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/auto.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/auto.c @@ -57,7 +57,7 @@ static void main(unsigned long bist) early_mtrr_init(); /* FIXME: Should be PC97307! */ - pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c b/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c index f8bf246d21..7c59595422 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x14 << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/dell/s1850/Config.lb b/src/mainboard/dell/s1850/Config.lb index 0e305e3bf9..90f0181888 100644 --- a/src/mainboard/dell/s1850/Config.lb +++ b/src/mainboard/dell/s1850/Config.lb @@ -1,10 +1,10 @@ ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## @@ -18,30 +18,30 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/dell/s1850/Options.lb b/src/mainboard/dell/s1850/Options.lb index 808fe21018..b6f853242a 100644 --- a/src/mainboard/dell/s1850/Options.lb +++ b/src/mainboard/dell/s1850/Options.lb @@ -1,57 +1,57 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_BTEXT uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY ### @@ -59,14 +59,14 @@ uses OBJCOPY ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1048576 +default CONFIG_ROM_SIZE=1048576 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -78,31 +78,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=16 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=16 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -120,39 +120,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="X6DHR" -default MAINBOARD_VENDOR= "Supermicro" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 +default CONFIG_MAINBOARD_PART_NUMBER="X6DHR" +default CONFIG_MAINBOARD_VENDOR= "Supermicro" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -167,8 +167,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -183,21 +183,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -209,17 +209,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ## ## Don't enable the btext console diff --git a/src/mainboard/dell/s1850/auto.c b/src/mainboard/dell/s1850/auto.c index 627acb4ca5..a80ba60b5b 100644 --- a/src/mainboard/dell/s1850/auto.c +++ b/src/mainboard/dell/s1850/auto.c @@ -103,7 +103,7 @@ static void main(unsigned long bist) outb(0x87,0x2e); outb(0x87,0x2e); pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/digitallogic/adl855pc/Config.lb b/src/mainboard/digitallogic/adl855pc/Config.lb index 91e0b844ec..c6401dd299 100644 --- a/src/mainboard/digitallogic/adl855pc/Config.lb +++ b/src/mainboard/digitallogic/adl855pc/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -13,29 +13,29 @@ arch i386 end ## driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -49,7 +49,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -71,7 +71,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/digitallogic/adl855pc/Options.lb b/src/mainboard/digitallogic/adl855pc/Options.lb index 24cb38cbd8..aed66c00e7 100644 --- a/src/mainboard/digitallogic/adl855pc/Options.lb +++ b/src/mainboard/digitallogic/adl855pc/Options.lb @@ -1,47 +1,47 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD uses CONFIG_UDELAY_IO -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -default DEFAULT_CONSOLE_LOGLEVEL=9 -default MAXIMUM_CONSOLE_LOGLEVEL=9 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 1024*1024 +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 1024*1024 ### ### Build options @@ -50,17 +50,17 @@ default ROM_SIZE = 1024*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## use io based udelay function @@ -70,48 +70,48 @@ default CONFIG_UDELAY_IO=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=5 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=5 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" diff --git a/src/mainboard/digitallogic/adl855pc/auto.c b/src/mainboard/digitallogic/adl855pc/auto.c index 04cf2a359f..61351ba5a9 100644 --- a/src/mainboard/digitallogic/adl855pc/auto.c +++ b/src/mainboard/digitallogic/adl855pc/auto.c @@ -78,7 +78,7 @@ static void main(unsigned long bist) #endif } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/digitallogic/msm586seg/Config.lb b/src/mainboard/digitallogic/msm586seg/Config.lb index 8f649b7964..0c28cc907d 100644 --- a/src/mainboard/digitallogic/msm586seg/Config.lb +++ b/src/mainboard/digitallogic/msm586seg/Config.lb @@ -1,8 +1,8 @@ -default ROM_SIZE = 512 * 1024 -default FALLBACK_SIZE = 0x10000 +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_FALLBACK_SIZE = 0x10000 -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 32 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 32 * 1024 include /config/nofailovercalculation.lb ## @@ -16,29 +16,29 @@ arch i386 end ## driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -52,7 +52,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -74,7 +74,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/digitallogic/msm586seg/Options.lb b/src/mainboard/digitallogic/msm586seg/Options.lb index fc9a2be178..68914e963c 100644 --- a/src/mainboard/digitallogic/msm586seg/Options.lb +++ b/src/mainboard/digitallogic/msm586seg/Options.lb @@ -1,47 +1,47 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_COMPRESS uses CONFIG_ROM_PAYLOAD uses CONFIG_USE_INIT -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_SERIAL8250 -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL # VGA support uses CONFIG_CONSOLE_VGA @@ -51,10 +51,10 @@ uses CONFIG_PCI_ROM_RUN default CONFIG_CONSOLE_SERIAL8250=1 -default DEFAULT_CONSOLE_LOGLEVEL=9 -default MAXIMUM_CONSOLE_LOGLEVEL=9 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -63,63 +63,63 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=7 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=7 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" diff --git a/src/mainboard/digitallogic/msm586seg/mainboard.c b/src/mainboard/digitallogic/msm586seg/mainboard.c index b64a927bd7..b8f2150e78 100644 --- a/src/mainboard/digitallogic/msm586seg/mainboard.c +++ b/src/mainboard/digitallogic/msm586seg/mainboard.c @@ -137,7 +137,7 @@ static void enable_dev(struct device *dev) { /* hack for IDIOTIC need to fix rom_start */ printk_err("Patching rom_start due to sc520 limits\n"); rom_start = 0x2000000 + 0x40000; - rom_end = rom_start + PAYLOAD_SIZE - 1; + rom_end = rom_start + CONFIG_PAYLOAD_SIZE - 1; } diff --git a/src/mainboard/digitallogic/msm800sev/Config.lb b/src/mainboard/digitallogic/msm800sev/Config.lb index 5256f09f54..f07835d7ce 100644 --- a/src/mainboard/digitallogic/msm800sev/Config.lb +++ b/src/mainboard/digitallogic/msm800sev/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,14 +14,14 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -37,7 +37,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds # mainboardinit ./failover.inc end diff --git a/src/mainboard/digitallogic/msm800sev/Options.lb b/src/mainboard/digitallogic/msm800sev/Options.lb index 3eede13583..c18a7c7ff0 100644 --- a/src/mainboard/digitallogic/msm800sev/Options.lb +++ b/src/mainboard/digitallogic/msm800sev/Options.lb @@ -1,59 +1,59 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -65,17 +65,17 @@ default CONFIG_PCI_ROM_RUN=0 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -85,58 +85,58 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=6 -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=6 +default CONFIG_PIRQ_ROUTE=1 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 default CONFIG_USE_PRINTK_IN_CAR=1 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -146,21 +146,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -172,13 +172,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c b/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c index e9dc8aec76..454031e782 100644 --- a/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c +++ b/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c @@ -81,7 +81,7 @@ void cache_as_ram_main(void) * for cs5536 */ cs5536_disable_internal_uart(); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); uart_init(); console_init(); diff --git a/src/mainboard/eaglelion/5bcm/Config.lb b/src/mainboard/eaglelion/5bcm/Config.lb index d8895573b2..d1f02be8c5 100644 --- a/src/mainboard/eaglelion/5bcm/Config.lb +++ b/src/mainboard/eaglelion/5bcm/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,29 +14,29 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -50,7 +50,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -72,7 +72,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/eaglelion/5bcm/Options.lb b/src/mainboard/eaglelion/5bcm/Options.lb index 6c4034120f..ad8fd92677 100644 --- a/src/mainboard/eaglelion/5bcm/Options.lb +++ b/src/mainboard/eaglelion/5bcm/Options.lb @@ -1,52 +1,52 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_VIDEO_MB -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -55,17 +55,17 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -75,50 +75,50 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=2 -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=2 +default CONFIG_PIRQ_ROUTE=1 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -128,21 +128,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -154,13 +154,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 default CONFIG_VIDEO_MB = 0 diff --git a/src/mainboard/eaglelion/5bcm/auto.c b/src/mainboard/eaglelion/5bcm/auto.c index b49039773a..096cebe2f7 100644 --- a/src/mainboard/eaglelion/5bcm/auto.c +++ b/src/mainboard/eaglelion/5bcm/auto.c @@ -23,7 +23,7 @@ static void main(unsigned long bist) { - pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/embeddedplanet/ep405pc/Config.lb b/src/mainboard/embeddedplanet/ep405pc/Config.lb index 551eebca67..4f7f808cec 100644 --- a/src/mainboard/embeddedplanet/ep405pc/Config.lb +++ b/src/mainboard/embeddedplanet/ep405pc/Config.lb @@ -23,5 +23,5 @@ end ## Build the objects we have code for in this directory. ## -addaction coreboot.a "$(CROSS_COMPILE)ranlib coreboot.a" +addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a" makedefine CFLAGS += -msoft-float diff --git a/src/mainboard/embeddedplanet/ep405pc/Options.lb b/src/mainboard/embeddedplanet/ep405pc/Options.lb index 7aabc4f252..c61cc6d2c4 100644 --- a/src/mainboard/embeddedplanet/ep405pc/Options.lb +++ b/src/mainboard/embeddedplanet/ep405pc/Options.lb @@ -2,25 +2,25 @@ ## Config file for the Embedded Planet EP405PC Computing Engine ## -uses PCIC0_CFGADDR +uses CONFIG_PCIC0_CFGADDR uses CONFIG_CBFS uses CONFIG_ARCH_X86 -uses PCIC0_CFGDATA -uses ISA_IO_BASE -uses ISA_MEM_BASE -uses TTYS0_BASE -uses _IO_BASE - -uses CPU_OPT -uses CROSS_COMPILE -uses HAVE_OPTION_TABLE +uses CONFIG_PCIC0_CFGDATA +uses CONFIG_ISA_IO_BASE +uses CONFIG_ISA_MEM_BASE +uses CONFIG_TTYS0_BASE +uses CONFIG_IO_BASE + +uses CONFIG_CPU_OPT +uses CONFIG_CROSS_COMPILE +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_COMPRESS uses CONFIG_CHIP_CONFIGURE -uses DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_USE_INIT uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD TTYS0_DIV -uses NO_POST +uses CONFIG_TTYS0_BAUD CONFIG_TTYS0_DIV +uses CONFIG_NO_POST uses CONFIG_IDE uses CONFIG_FS_PAYLOAD uses CONFIG_FS_EXT2 @@ -28,54 +28,54 @@ uses CONFIG_FS_ISO9660 uses CONFIG_FS_FAT uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses AUTOBOOT_CMDLINE +uses CONFIG_AUTOBOOT_CMDLINE uses CONFIG_SYS_CLK_FREQ -uses IDE_BOOT_DRIVE -#uses IDE_SWAB -uses IDE_OFFSET -uses ROM_SIZE -uses ROM_IMAGE_SIZE -uses _RESET -uses _EXCEPTION_VECTORS -uses _ROMBASE -uses _ROMSTART -uses _RAMBASE -#uses _RAMSTART -uses EMBEDDED_RAM_SIZE -uses STACK_SIZE HEAP_SIZE - -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IDE_BOOT_DRIVE +#uses CONFIG_IDE_SWAB +uses CONFIG_IDE_OFFSET +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_RESET +uses CONFIG_EXCEPTION_VECTORS +uses CONFIG_ROMBASE +uses CONFIG_ROMSTART +uses CONFIG_RAMBASE +#uses CONFIG_RAMSTART +uses CONFIG_EMBEDDED_RAM_SIZE +uses CONFIG_STACK_SIZE CONFIG_HEAP_SIZE + +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY ## ## Set PCI configuration register addresses ## -default PCIC0_CFGADDR=0xeec00000 -default PCIC0_CFGDATA=0xeec00004 +default CONFIG_PCIC0_CFGADDR=0xeec00000 +default CONFIG_PCIC0_CFGDATA=0xeec00004 ## ## Set PCI/ISA I/O and memory base address ## -default ISA_IO_BASE=0xe8000000 -default ISA_MEM_BASE=0x80000000 -default _IO_BASE=ISA_IO_BASE +default CONFIG_ISA_IO_BASE=0xe8000000 +default CONFIG_ISA_MEM_BASE=0x80000000 +default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE ## ## HACK ALERT: the UART0 registers are not in the PCI I/O address space ## but both IDE and UART use the same routines for I/O (inb/outb). To get ## around this we set TTYSO_BASE to the difference between the two. ## -default TTYS0_BASE=0xef600300-ISA_IO_BASE +default CONFIG_TTYS0_BASE=0xef600300-CONFIG_ISA_IO_BASE ## Enable PPC405 instructions -default CPU_OPT="-mcpu=405" -#default CPU_OPT="" +default CONFIG_CPU_OPT="-mcpu=405" +#default CONFIG_CPU_OPT="" default CONFIG_ARCH_X86=0 ## Use stage 1 initialization code @@ -88,14 +88,14 @@ default CONFIG_CHIP_CONFIGURE=1 default CONFIG_COMPRESS=0 ## Turn off POST codes -default NO_POST=1 +default CONFIG_NO_POST=1 ## Enable serial console -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 default CONFIG_CONSOLE_SERIAL8250=1 # Divisor of 69 == 9600 baud due to weird clocking -default TTYS0_DIV=69 -default TTYS0_BAUD=9600 +default CONFIG_TTYS0_DIV=69 +default CONFIG_TTYS0_BAUD=9600 ## Boot linux from IDE default CONFIG_IDE=1 @@ -103,25 +103,25 @@ default CONFIG_FS_PAYLOAD=1 default CONFIG_FS_EXT2=1 default CONFIG_FS_ISO9660=1 default CONFIG_FS_FAT=1 -default AUTOBOOT_CMDLINE="hda1:/vmlinuz" +default CONFIG_AUTOBOOT_CMDLINE="hda1:/vmlinuz" -default ROM_SIZE=1048576 +default CONFIG_ROM_SIZE=1048576 ## Board has fixed size RAM -default EMBEDDED_RAM_SIZE=64*1024*1024 +default CONFIG_EMBEDDED_RAM_SIZE=64*1024*1024 ## Coreboot C code runs at this location in RAM -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Use a 64K stack ## -default STACK_SIZE=0x10000 +default CONFIG_STACK_SIZE=0x10000 ## ## Use a 64K heap ## -default HEAP_SIZE=0x10000 +default CONFIG_HEAP_SIZE=0x10000 ## ## System clock @@ -129,19 +129,19 @@ default HEAP_SIZE=0x10000 default CONFIG_SYS_CLK_FREQ=33 ## -default _ROMBASE=0xfff00000 +default CONFIG_ROMBASE=0xfff00000 ## Reset vector address -default _RESET=0xfffffffc +default CONFIG_RESET=0xfffffffc ## Exception vectors -default _EXCEPTION_VECTORS=_ROMBASE+0x100 +default CONFIG_EXCEPTION_VECTORS=CONFIG_ROMBASE+0x100 ## coreboot ROM start address -default _ROMSTART=0xfff03000 +default CONFIG_ROMSTART=0xfff03000 ## coreboot C code runs at this location in RAM -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ### End Options.lb # diff --git a/src/mainboard/emulation/qemu-x86/Config.lb b/src/mainboard/emulation/qemu-x86/Config.lb index cabcb2deeb..78e5936ffc 100644 --- a/src/mainboard/emulation/qemu-x86/Config.lb +++ b/src/mainboard/emulation/qemu-x86/Config.lb @@ -1,34 +1,34 @@ -## we don't use USE_DCACHE_RAM by default -default USE_DCACHE_RAM=0 +## we don't use CONFIG_USE_DCACHE_RAM by default +default CONFIG_USE_DCACHE_RAM=0 ## ## Compute the location and size of where this firmware image ## (coreboot plus bootloader) will live in the boot rom chip. ## -default ROM_SIZE = 256 * 1024 -default ROM_SECTION_SIZE = ROM_IMAGE_SIZE -default ROM_SECTION_OFFSET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_ROM_SECTION_SIZE = CONFIG_ROM_IMAGE_SIZE +default CONFIG_ROM_SECTION_OFFSET = 0 ## ## Compute the start location and size size of ## The coreboot bootloader. ## -default PAYLOAD_SIZE = ( ROM_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default CONFIG_PAYLOAD_SIZE = ( CONFIG_ROM_SIZE - CONFIG_ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) ## ## Compute where this copy of coreboot will start in the boot rom ## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) +default CONFIG_ROMBASE = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE ) ## ## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## CONFIG_XIP_ROM_SIZE must be a power of 2. +## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE ## -default XIP_ROM_SIZE=32*1024 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) +default CONFIG_XIP_ROM_SIZE=32*1024 +default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE ) ## ## Set all of the defaults for an x86 architecture @@ -41,15 +41,15 @@ arch i386 end ## driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -## ALL dependencies for USE_DCACHE_RAM go here. +## ALL dependencies for CONFIG_USE_DCACHE_RAM go here. ## That way, later, we can simply yank them if we wish. -## We include the old-fashioned entry code in the ! USE_DCACHE_RAM case. +## We include the old-fashioned entry code in the ! CONFIG_USE_DCACHE_RAM case. ## we do not use failover yet in this case. This is a work in progress. -if USE_DCACHE_RAM +if CONFIG_USE_DCACHE_RAM ## ## mainboardinit arch/i386/init/entry.S @@ -63,22 +63,22 @@ else ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -112,7 +112,7 @@ else ldscript /arch/i386/lib/id.lds ## -## end of USE_DCACHE_RAM bits. +## end of CONFIG_USE_DCACHE_RAM bits. ## end diff --git a/src/mainboard/emulation/qemu-x86/Options.lb b/src/mainboard/emulation/qemu-x86/Options.lb index fdb69ffc47..191c6c6a41 100644 --- a/src/mainboard/emulation/qemu-x86/Options.lb +++ b/src/mainboard/emulation/qemu-x86/Options.lb @@ -1,63 +1,63 @@ -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_COMPRESS uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses HAVE_HIGH_TABLES -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_HIGH_TABLES +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_PCI_ROM_RUN uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE uses CONFIG_CONSOLE_SERIAL8250 -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CBFS default CONFIG_CONSOLE_SERIAL8250=1 -default DEFAULT_CONSOLE_LOGLEVEL=8 -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 default CONFIG_CBFS=1 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -66,30 +66,30 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=6 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=6 -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Option ROM init @@ -101,40 +101,40 @@ default CONFIG_PCI_OPTION_ROM_RUN_REALMODE=1 ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = ROM_IMAGE_SIZE +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## known-good settings for qemu -default DCACHE_RAM_BASE=0x8f000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_DCACHE_RAM_BASE=0x8f000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 diff --git a/src/mainboard/gigabyte/ga-6bxc/Config.lb b/src/mainboard/gigabyte/ga-6bxc/Config.lb index 339c6b1a94..acc09b495e 100644 --- a/src/mainboard/gigabyte/ga-6bxc/Config.lb +++ b/src/mainboard/gigabyte/ga-6bxc/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/gigabyte/ga-6bxc/Options.lb b/src/mainboard/gigabyte/ga-6bxc/Options.lb index 2641e766df..4d927e1fb8 100644 --- a/src/mainboard/gigabyte/ga-6bxc/Options.lb +++ b/src/mainboard/gigabyte/ga-6bxc/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/gigabyte/ga-6bxc/auto.c b/src/mainboard/gigabyte/ga-6bxc/auto.c index e67431afc5..9947d20e97 100644 --- a/src/mainboard/gigabyte/ga-6bxc/auto.c +++ b/src/mainboard/gigabyte/ga-6bxc/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - it8671f_enable_serial(SERIAL_DEV, TTYS0_BASE); + it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/gigabyte/ga-6bxc/irq_tables.c b/src/mainboard/gigabyte/ga-6bxc/irq_tables.c index bcc1fcd21b..a56c62d3f8 100644 --- a/src/mainboard/gigabyte/ga-6bxc/irq_tables.c +++ b/src/mainboard/gigabyte/ga-6bxc/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x07 << 3) | 0x0, /* Interrupt router device */ 0xc00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb index c395fb738f..104ace034d 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb +++ b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb @@ -21,8 +21,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -35,30 +35,30 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CPU_OPT) $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_CPU_OPT) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -68,13 +68,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -93,8 +93,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -102,7 +102,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -120,13 +120,13 @@ ldscript /southbridge/sis/sis966/id.lds ## ## ROMSTRAP table for MCP55 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/sis/sis966/romstrap.inc ldscript /southbridge/sis/sis966/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/sis/sis966/romstrap.inc ldscript /southbridge/sis/sis966/romstrap.lds end @@ -142,12 +142,12 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb index a57533bfe2..b84498b658 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb +++ b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb @@ -21,90 +21,90 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_USBDEBUG_DIRECT uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -112,9 +112,9 @@ uses CONFIG_LB_MEM_TOPK uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -123,21 +123,21 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 -#default ROM_SIZE=0x100000 +default CONFIG_ROM_SIZE=524288 +#default CONFIG_ROM_SIZE=0x100000 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE=0x3f000 #FAILOVER: 4K -default FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -145,40 +145,40 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ACPI tables will be included -default HAVE_ACPI_TABLES=0 +default CONFIG_HAVE_ACPI_TABLES=0 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -189,25 +189,25 @@ default CONFIG_MAX_CPUS=2 default CONFIG_MAX_PHYSICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1 -#default SERIAL_CPU_INIT=0 +#default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -216,16 +216,16 @@ default CONFIG_PCI_ROM_RUN=1 #default CONFIG_USBDEBUG_DIRECT=0 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default HT_CHAIN_UNITID_BASE=0 +default CONFIG_HT_CHAIN_UNITID_BASE=0 #real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x6 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -233,15 +233,15 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 default CONFIG_AP_CODE_IN_CAR=0 -default MEM_TRAIN_SEQ=2 -default WAIT_BEFORE_CPUS_INIT=0 +default CONFIG_MEM_TRAIN_SEQ=2 +default CONFIG_WAIT_BEFORE_CPUS_INIT=0 ## ## Build code to setup a generic IOAPIC @@ -251,37 +251,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="ga_2761gxdk" -default MAINBOARD_VENDOR="GIGABYTE" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1039 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234 +default CONFIG_MAINBOARD_PART_NUMBER="ga_2761gxdk" +default CONFIG_MAINBOARD_VENDOR="GIGABYTE" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1039 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -297,8 +297,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -314,21 +314,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -340,17 +340,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c b/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c index 35f2e63896..6fb051e7c8 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c @@ -88,8 +88,8 @@ static void post_code(uint8_t value) { void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c b/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c index f5c77ffee5..e44f4335b4 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c @@ -41,7 +41,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -58,7 +58,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT @@ -82,7 +82,7 @@ #include "superio/ite/it8716f/it8716f_early_serial.c" #include "superio/ite/it8716f/it8716f_early_init.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" @@ -154,7 +154,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/sis/sis966/sis966_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -221,7 +221,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -234,21 +234,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -261,7 +261,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; @@ -272,7 +272,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_enter_ext_func_mode(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x23, 0); - it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE); + it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); @@ -292,7 +292,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/gigabyte/m57sli/Config.lb b/src/mainboard/gigabyte/m57sli/Config.lb index 64864cd3a0..3f69d6f0e5 100644 --- a/src/mainboard/gigabyte/m57sli/Config.lb +++ b/src/mainboard/gigabyte/m57sli/Config.lb @@ -19,8 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -33,30 +33,30 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -66,13 +66,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -91,8 +91,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -100,7 +100,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -118,13 +118,13 @@ ldscript /southbridge/nvidia/mcp55/id.lds ## ## ROMSTRAP table for MCP55 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end @@ -140,17 +140,17 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end -if HAVE_FANCTL +if CONFIG_HAVE_FANCTL object fanctl.o end @@ -166,11 +166,11 @@ end ## ## ACPI Support ## -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o makerule dsdt.c - depends "$(MAINBOARD)/dsdt.asl" - action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.asl" + depends "$(CONFIG_MAINBOARD)/dsdt.asl" + action "iasl -p $(PWD)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o diff --git a/src/mainboard/gigabyte/m57sli/Options.lb b/src/mainboard/gigabyte/m57sli/Options.lb index bcaba18376..7f96271069 100644 --- a/src/mainboard/gigabyte/m57sli/Options.lb +++ b/src/mainboard/gigabyte/m57sli/Options.lb @@ -19,92 +19,92 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_USBDEBUG_DIRECT uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -112,33 +112,33 @@ uses CONFIG_LB_MEM_TOPK uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses HAVE_FANCTL +uses CONFIG_HAVE_FANCTL ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 -#default ROM_SIZE=0x100000 +default CONFIG_ROM_SIZE=524288 +#default CONFIG_ROM_SIZE=0x100000 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE=0x3f000 #FAILOVER: 4K -default FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -146,48 +146,48 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Set-up automatic fan control ## -default HAVE_FANCTL=1 +default CONFIG_HAVE_FANCTL=1 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## HIGH tables support -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -198,25 +198,25 @@ default CONFIG_MAX_CPUS=2 default CONFIG_MAX_PHYSICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1 -#default SERIAL_CPU_INIT=0 +#default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -225,16 +225,16 @@ default CONFIG_PCI_ROM_RUN=1 #default CONFIG_USBDEBUG_DIRECT=1 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default HT_CHAIN_UNITID_BASE=0 +default CONFIG_HT_CHAIN_UNITID_BASE=0 #real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x6 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -242,15 +242,15 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 default CONFIG_AP_CODE_IN_CAR=0 -default MEM_TRAIN_SEQ=2 -default WAIT_BEFORE_CPUS_INIT=0 +default CONFIG_MEM_TRAIN_SEQ=2 +default CONFIG_WAIT_BEFORE_CPUS_INIT=0 ## ## Build code to setup a generic IOAPIC @@ -260,37 +260,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="m57sli" -default MAINBOARD_VENDOR="GIGABYTE" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 +default CONFIG_MAINBOARD_PART_NUMBER="m57sli" +default CONFIG_MAINBOARD_VENDOR="GIGABYTE" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -306,8 +306,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -323,21 +323,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -349,17 +349,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" # # CBFS diff --git a/src/mainboard/gigabyte/m57sli/apc_auto.c b/src/mainboard/gigabyte/m57sli/apc_auto.c index 7c09ae4818..d0730b935a 100644 --- a/src/mainboard/gigabyte/m57sli/apc_auto.c +++ b/src/mainboard/gigabyte/m57sli/apc_auto.c @@ -86,8 +86,8 @@ static void post_code(uint8_t value) { void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c index 5462c31891..ab604c02b1 100644 --- a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c +++ b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c @@ -39,7 +39,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -56,7 +56,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT @@ -79,7 +79,7 @@ #include "superio/ite/it8716f/it8716f_early_serial.c" #include "superio/ite/it8716f/it8716f_early_init.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" @@ -152,7 +152,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -219,7 +219,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -232,21 +232,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -259,7 +259,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; @@ -281,10 +281,10 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_write_config(GPIO_DEV, 0x64, 0x08); pnp_write_config(GPIO_DEV, 0x65, 0x20); /* We can get away with not resetting the logical device because - * it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE) will do that. + * it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE) will do that. */ } - it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE); + it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); @@ -304,7 +304,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/hp/dl145_g3/Config.lb b/src/mainboard/hp/dl145_g3/Config.lb index f493dda3c6..12ea977bab 100644 --- a/src/mainboard/hp/dl145_g3/Config.lb +++ b/src/mainboard/hp/dl145_g3/Config.lb @@ -25,8 +25,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -40,18 +40,18 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -60,7 +60,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -78,7 +78,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -102,7 +102,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/hp/dl145_g3/Options.lb b/src/mainboard/hp/dl145_g3/Options.lb index a66c599901..283e37a3be 100644 --- a/src/mainboard/hp/dl145_g3/Options.lb +++ b/src/mainboard/hp/dl145_g3/Options.lb @@ -24,84 +24,84 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT uses CONFIG_CBFS -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -114,14 +114,14 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=ROM_IMAGE_SIZE +default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -129,37 +129,37 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from linuxBIOS ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=15 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=15 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -170,41 +170,41 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -default SERIAL_CPU_INIT=0 +default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x8 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x8 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=0 #HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0x06 +default CONFIG_HT_CHAIN_UNITID_BASE=0x06 #real SB Unit ID, default is 0x20, mean dont touch it at last -default HT_CHAIN_END_UNITID_BASE=0x01 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x01 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -212,10 +212,10 @@ default SB_HT_CHAIN_ON_BUS0=2 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcc000 -default DCACHE_RAM_SIZE=0x04000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcc000 +default CONFIG_DCACHE_RAM_SIZE=0x04000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 ## @@ -226,37 +226,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="DL145 G3" -default MAINBOARD_VENDOR="HP" -#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 +default CONFIG_MAINBOARD_PART_NUMBER="DL145 G3" +default CONFIG_MAINBOARD_VENDOR="HP" +#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -270,8 +270,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -289,21 +289,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -315,17 +315,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ## ## CBFS diff --git a/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c b/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c index c2269698e8..c3aeca615e 100644 --- a/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c +++ b/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c @@ -44,7 +44,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -62,7 +62,7 @@ #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -84,7 +84,7 @@ #include "superio/nsc/pc87417/pc87417_early_serial.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" @@ -156,7 +156,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "northbridge/amd/amdk8/early_ht.c" @@ -238,7 +238,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -253,21 +253,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -283,7 +283,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; unsigned bsp_apicid = 0; @@ -293,7 +293,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } - pilot_enable_serial(SERIAL_DEV, TTYS0_BASE); + pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); //setup_mp_resource_map(); @@ -310,7 +310,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c index d5732d0738..65a0eb9796 100644 --- a/src/mainboard/hp/dl145_g3/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g3/get_bus_conf.c @@ -108,7 +108,7 @@ void get_bus_conf(void) printk_debug("now found %s...\n",dev_path(dev)); if(dev) { m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); m->bus_isa++; printk_debug("bus_isa 1=%d\n",m->bus_isa); @@ -124,7 +124,7 @@ void get_bus_conf(void) dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0)); if(dev) { m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); m->bus_isa++; printk_debug("bus_isa 2=%d\n",m->bus_isa); diff --git a/src/mainboard/ibm/e325/Config.lb b/src/mainboard/ibm/e325/Config.lb index 86fc7d21f5..0c7cd33d89 100644 --- a/src/mainboard/ibm/e325/Config.lb +++ b/src/mainboard/ibm/e325/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -13,22 +13,22 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -38,7 +38,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -56,7 +56,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -80,7 +80,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/ibm/e325/Options.lb b/src/mainboard/ibm/e325/Options.lb index 98f61b1e0f..475863c2ca 100644 --- a/src/mainboard/ibm/e325/Options.lb +++ b/src/mainboard/ibm/e325/Options.lb @@ -1,54 +1,54 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -58,48 +58,48 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=9 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -117,45 +117,45 @@ default CONFIG_IOAPIC=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="E325" -default MAINBOARD_VENDOR="IBM" -#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 +default CONFIG_MAINBOARD_PART_NUMBER="E325" +default CONFIG_MAINBOARD_VENDOR="IBM" +#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f +#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -169,8 +169,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" default CONFIG_USE_PRINTK_IN_CAR=1 @@ -182,21 +182,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -208,17 +208,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/ibm/e325/cache_as_ram_auto.c b/src/mainboard/ibm/e325/cache_as_ram_auto.c index 98a5a99db9..a6d32b64a0 100644 --- a/src/mainboard/ibm/e325/cache_as_ram_auto.c +++ b/src/mainboard/ibm/e325/cache_as_ram_auto.c @@ -93,7 +93,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -145,7 +145,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -183,7 +183,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) init_cpus(cpu_init_detectedx); } - pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/ibm/e325/irq_tables.c b/src/mainboard/ibm/e325/irq_tables.c index f340a2d31e..cfc28dd0a3 100644 --- a/src/mainboard/ibm/e325/irq_tables.c +++ b/src/mainboard/ibm/e325/irq_tables.c @@ -1,7 +1,7 @@ #include <arch/pirq_routing.h> #include <device/pci.h> -#define IRQ_SLOT_COUNT 12 +#define CONFIG_IRQ_SLOT_COUNT 12 #define IRQ_ROUTER_BUS 0 #define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3) #define IRQ_ROUTER_VENDOR 0x1022 @@ -19,7 +19,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT table entries */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT table entries */ IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/ibm/e326/Config.lb b/src/mainboard/ibm/e326/Config.lb index 75a6be6c94..92a0c52145 100644 --- a/src/mainboard/ibm/e326/Config.lb +++ b/src/mainboard/ibm/e326/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -13,22 +13,22 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -38,7 +38,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -56,7 +56,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -80,7 +80,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/ibm/e326/Options.lb b/src/mainboard/ibm/e326/Options.lb index 9a101d1950..8406ecf84b 100644 --- a/src/mainboard/ibm/e326/Options.lb +++ b/src/mainboard/ibm/e326/Options.lb @@ -1,56 +1,56 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -60,48 +60,48 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=9 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -123,45 +123,45 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="E326" -default MAINBOARD_VENDOR="IBM" -#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 +default CONFIG_MAINBOARD_PART_NUMBER="E326" +default CONFIG_MAINBOARD_VENDOR="IBM" +#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f +#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -175,8 +175,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" default CONFIG_USE_PRINTK_IN_CAR=1 @@ -188,21 +188,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -214,17 +214,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/ibm/e326/cache_as_ram_auto.c b/src/mainboard/ibm/e326/cache_as_ram_auto.c index 872351323d..b036c62f11 100644 --- a/src/mainboard/ibm/e326/cache_as_ram_auto.c +++ b/src/mainboard/ibm/e326/cache_as_ram_auto.c @@ -93,7 +93,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -145,7 +145,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -183,7 +183,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) init_cpus(cpu_init_detectedx); } - pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/ibm/e326/irq_tables.c b/src/mainboard/ibm/e326/irq_tables.c index f340a2d31e..cfc28dd0a3 100644 --- a/src/mainboard/ibm/e326/irq_tables.c +++ b/src/mainboard/ibm/e326/irq_tables.c @@ -1,7 +1,7 @@ #include <arch/pirq_routing.h> #include <device/pci.h> -#define IRQ_SLOT_COUNT 12 +#define CONFIG_IRQ_SLOT_COUNT 12 #define IRQ_ROUTER_BUS 0 #define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3) #define IRQ_ROUTER_VENDOR 0x1022 @@ -19,7 +19,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT table entries */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT table entries */ IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/iei/juki-511p/Config.lb b/src/mainboard/iei/juki-511p/Config.lb index 345f981510..fcc70fd703 100644 --- a/src/mainboard/iei/juki-511p/Config.lb +++ b/src/mainboard/iei/juki-511p/Config.lb @@ -2,31 +2,31 @@ ## Compute the location and size of where this firmware image ## (coreboot plus bootloader) will live in the boot rom chip. ## -default ROM_SIZE = 256 * 1024 -default ROM_SECTION_SIZE = ROM_SIZE -default ROM_SECTION_OFFSET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_ROM_SECTION_SIZE = CONFIG_ROM_SIZE +default CONFIG_ROM_SECTION_OFFSET = 0 ## ## Compute the start location and size size of ## The coreboot bootloader. ## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default CONFIG_PAYLOAD_SIZE = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) ## ## Compute where this copy of coreboot will start in the boot rom ## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) +default CONFIG_ROMBASE = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE ) ## ## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## CONFIG_XIP_ROM_SIZE must be a power of 2. +## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE ## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) +default CONFIG_XIP_ROM_SIZE=65536 +default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE ) ## ## Set all of the defaults for an x86 architecture @@ -40,29 +40,29 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## diff --git a/src/mainboard/iei/juki-511p/Options.lb b/src/mainboard/iei/juki-511p/Options.lb index 2e91257805..acedd0f765 100644 --- a/src/mainboard/iei/juki-511p/Options.lb +++ b/src/mainboard/iei/juki-511p/Options.lb @@ -1,53 +1,53 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET uses CONFIG_UDELAY_IO -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_COMPRESS uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_SERIAL8250 -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_VIDEO_MB -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -56,57 +56,57 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 default CONFIG_UDELAY_IO=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=0 -default IRQ_SLOT_COUNT=2 -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=0 +default CONFIG_IRQ_SLOT_COUNT=2 +default CONFIG_PIRQ_ROUTE=1 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 @@ -116,32 +116,32 @@ default CONFIG_ROM_PAYLOAD = 1 # To Enable the Serial Console default CONFIG_CONSOLE_SERIAL8250=1 -default DEFAULT_CONSOLE_LOGLEVEL=8 -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" default CONFIG_VIDEO_MB = 0 diff --git a/src/mainboard/iei/juki-511p/auto.c b/src/mainboard/iei/juki-511p/auto.c index d24dee98d7..8486e82d55 100644 --- a/src/mainboard/iei/juki-511p/auto.c +++ b/src/mainboard/iei/juki-511p/auto.c @@ -40,7 +40,7 @@ static void main(unsigned long bist) { /* Initialize the serial console. */ - w83977f_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/iei/nova4899r/Config.lb b/src/mainboard/iei/nova4899r/Config.lb index 50b4029a1d..c567647a99 100644 --- a/src/mainboard/iei/nova4899r/Config.lb +++ b/src/mainboard/iei/nova4899r/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,29 +14,29 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -50,7 +50,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -72,7 +72,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/iei/nova4899r/Options.lb b/src/mainboard/iei/nova4899r/Options.lb index 3b49675b70..5072017fd5 100644 --- a/src/mainboard/iei/nova4899r/Options.lb +++ b/src/mainboard/iei/nova4899r/Options.lb @@ -1,43 +1,43 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA @@ -46,10 +46,10 @@ uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_PRECOMPRESSED_PAYLOAD uses CONFIG_VIDEO_MB -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -62,17 +62,17 @@ default CONFIG_PCI_ROM_RUN=1 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=0 +default CONFIG_HAVE_FALLBACK_BOOT=0 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -82,50 +82,50 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=7 -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=7 +default CONFIG_PIRQ_ROUTE=1 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -135,21 +135,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -161,14 +161,14 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 default CONFIG_VIDEO_MB = 0 diff --git a/src/mainboard/iei/nova4899r/auto.c b/src/mainboard/iei/nova4899r/auto.c index 29fde67779..6b198f5337 100644 --- a/src/mainboard/iei/nova4899r/auto.c +++ b/src/mainboard/iei/nova4899r/auto.c @@ -39,7 +39,7 @@ static void main(unsigned long bist) { /* Initialize the serial console. */ - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/iei/nova4899r/irq_tables.c b/src/mainboard/iei/nova4899r/irq_tables.c index 3591fff1ee..5886c20077 100644 --- a/src/mainboard/iei/nova4899r/irq_tables.c +++ b/src/mainboard/iei/nova4899r/irq_tables.c @@ -51,7 +51,7 @@ const struct irq_routing_table intel_irq_routing_table = { .signature = PIRQ_SIGNATURE, /* u32 signature */ .version = PIRQ_VERSION, /* u16 version */ - .size = 32+16*IRQ_SLOT_COUNT, /* There can be total 4 devices on the bus */ + .size = 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 4 devices on the bus */ .rtr_bus = 0x00, /* Where the interrupt router lies (bus) */ .rtr_devfn = (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ .exclusive_irqs = 0x4C20, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Config.lb b/src/mainboard/iei/pcisa-lx-800-r10/Config.lb index 515ffd0246..e4ebbcb170 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Config.lb +++ b/src/mainboard/iei/pcisa-lx-800-r10/Config.lb @@ -18,20 +18,20 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # Compile cache_as_ram.c to auto.inc. makerule ./cache_as_ram_auto.inc - # depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - depends "$(MAINBOARD)/cache_as_ram_auto.c" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -39,7 +39,7 @@ mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -48,7 +48,7 @@ else end mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds # mainboardinit ./failover.inc end diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Options.lb b/src/mainboard/iei/pcisa-lx-800-r10/Options.lb index a3034b0a45..8da41c1b04 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Options.lb +++ b/src/mainboard/iei/pcisa-lx-800-r10/Options.lb @@ -18,93 +18,93 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESS uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_IO uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -default ROM_SIZE = 256 * 1024 +default CONFIG_ROM_SIZE = 256 * 1024 default CONFIG_CONSOLE_VGA = 0 default CONFIG_VIDEO_MB = 8 default CONFIG_PCI_ROM_RUN = 0 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_IO = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 9 -default PIRQ_ROUTE = 1 -default HAVE_OPTION_TABLE = 0 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xc8000 -default DCACHE_RAM_SIZE = 32 * 1024 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 9 +default CONFIG_PIRQ_ROUTE = 1 +default CONFIG_HAVE_OPTION_TABLE = 0 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xc8000 +default CONFIG_DCACHE_RAM_SIZE = 32 * 1024 default CONFIG_USE_PRINTK_IN_CAR=1 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 -default DEFAULT_CONSOLE_LOGLEVEL=8 -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c b/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c index 23a740aeb4..cccb4a7509 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c @@ -118,7 +118,7 @@ void cache_as_ram_main(void) /* Note: must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); uart_init(); console_init(); diff --git a/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c b/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c index affbfc6790..6f6d38b865 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c @@ -47,7 +47,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT,/* there can be total 6 devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* there can be total 6 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ EXCLUSIVE_PCI_IRQS, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/intel/jarrell/Config.lb b/src/mainboard/intel/jarrell/Config.lb index 4a2468ab03..01bcf82862 100644 --- a/src/mainboard/intel/jarrell/Config.lb +++ b/src/mainboard/intel/jarrell/Config.lb @@ -1,10 +1,10 @@ ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## @@ -18,30 +18,30 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/intel/jarrell/Options.lb b/src/mainboard/intel/jarrell/Options.lb index a0e1f9ecf6..efa594a9c2 100644 --- a/src/mainboard/intel/jarrell/Options.lb +++ b/src/mainboard/intel/jarrell/Options.lb @@ -1,59 +1,59 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_BTEXT uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY -uses MAX_REBOOT_CNT -uses USE_WATCHDOG_ON_BOOT +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY +uses CONFIG_MAX_REBOOT_CNT +uses CONFIG_USE_WATCHDOG_ON_BOOT ### @@ -63,23 +63,23 @@ uses USE_WATCHDOG_ON_BOOT ## ## Because we do the stutter start we need more attempts ## -default MAX_REBOOT_CNT=8 +default CONFIG_MAX_REBOOT_CNT=8 ## ## Use the watchdog to break out of a lockup condition ## -default USE_WATCHDOG_ON_BOOT=1 +default CONFIG_USE_WATCHDOG_ON_BOOT=1 ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=2097152 +default CONFIG_ROM_SIZE=2097152 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -91,31 +91,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=9 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -133,40 +133,40 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="SE7520JR22D" -default MAINBOARD_VENDOR= "Intel" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1079 -#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3437 +default CONFIG_MAINBOARD_PART_NUMBER="SE7520JR22D" +default CONFIG_MAINBOARD_VENDOR= "Intel" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1079 +#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3437 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -181,8 +181,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -197,21 +197,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -223,17 +223,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ## ## Don't enable the btext console diff --git a/src/mainboard/intel/jarrell/auto.c b/src/mainboard/intel/jarrell/auto.c index 61b066adfd..9745f761f8 100644 --- a/src/mainboard/intel/jarrell/auto.c +++ b/src/mainboard/intel/jarrell/auto.c @@ -81,7 +81,7 @@ static void main(unsigned long bist) /* Setup the console */ pc87427_disable_dev(CONSOLE_SERIAL_DEV); pc87427_disable_dev(HIDDEN_SERIAL_DEV); - pc87427_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); /* Enable Serial 2 lines instead of GPIO */ outb(0x2c, 0x2e); outb((inb(0x2f) & (~1<<1)), 0x2f); diff --git a/src/mainboard/intel/mtarvon/Config.lb b/src/mainboard/intel/mtarvon/Config.lb index dd9ea4a5a6..0613d7d369 100644 --- a/src/mainboard/intel/mtarvon/Config.lb +++ b/src/mainboard/intel/mtarvon/Config.lb @@ -17,8 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## @@ -32,29 +32,29 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -68,7 +68,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -90,7 +90,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/intel/mtarvon/Options.lb b/src/mainboard/intel/mtarvon/Options.lb index 47e7ff05f8..f1e76b000e 100644 --- a/src/mainboard/intel/mtarvon/Options.lb +++ b/src/mainboard/intel/mtarvon/Options.lb @@ -17,56 +17,56 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY ### @@ -74,14 +74,14 @@ uses OBJCOPY ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE = 2 * 1024 * 1024 +default CONFIG_ROM_SIZE = 2 * 1024 * 1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -93,19 +93,19 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=1 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code for SMP support @@ -123,39 +123,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="Mt. Arvon" -default MAINBOARD_VENDOR= "Intel" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680 +default CONFIG_MAINBOARD_PART_NUMBER="Mt. Arvon" +default CONFIG_MAINBOARD_VENDOR= "Intel" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680 ### ### Coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -170,8 +170,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -186,21 +186,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -212,17 +212,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=5 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=5 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/intel/mtarvon/auto.c b/src/mainboard/intel/mtarvon/auto.c index dd4b76346c..59c4e2fbc1 100644 --- a/src/mainboard/intel/mtarvon/auto.c +++ b/src/mainboard/intel/mtarvon/auto.c @@ -86,7 +86,7 @@ static void main(unsigned long bist) } /* Set up the console */ i3100_enable_superio(); - i3100_enable_serial(0x4e, I3100_SP1, TTYS0_BASE); + i3100_enable_serial(0x4e, I3100_SP1, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/intel/mtarvon/irq_tables.c b/src/mainboard/intel/mtarvon/irq_tables.c index 9a295999ef..ddf5d9f795 100644 --- a/src/mainboard/intel/mtarvon/irq_tables.c +++ b/src/mainboard/intel/mtarvon/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ 0x00, /* u8 Bus 0 */ (0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */ 0x0000, /* u16 reserve IRQ for PCI */ diff --git a/src/mainboard/intel/truxton/Config.lb b/src/mainboard/intel/truxton/Config.lb index 0f57a779b5..4a80852317 100644 --- a/src/mainboard/intel/truxton/Config.lb +++ b/src/mainboard/intel/truxton/Config.lb @@ -17,8 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## @@ -32,29 +32,29 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -68,7 +68,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -90,7 +90,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/intel/truxton/Options.lb b/src/mainboard/intel/truxton/Options.lb index d4c777c4e2..48160b42f4 100644 --- a/src/mainboard/intel/truxton/Options.lb +++ b/src/mainboard/intel/truxton/Options.lb @@ -17,56 +17,56 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY ### @@ -74,14 +74,14 @@ uses OBJCOPY ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE = 2 * 1024 * 1024 +default CONFIG_ROM_SIZE = 2 * 1024 * 1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -93,19 +93,19 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=1 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code for SMP support @@ -123,39 +123,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="Truxton" -default MAINBOARD_VENDOR= "Intel" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680 +default CONFIG_MAINBOARD_PART_NUMBER="Truxton" +default CONFIG_MAINBOARD_VENDOR= "Intel" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680 ### ### Coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -170,8 +170,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -186,21 +186,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -212,17 +212,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=5 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=5 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb diff --git a/src/mainboard/intel/truxton/auto.c b/src/mainboard/intel/truxton/auto.c index 08c64dffe7..8176774fb3 100644 --- a/src/mainboard/intel/truxton/auto.c +++ b/src/mainboard/intel/truxton/auto.c @@ -84,7 +84,7 @@ static void main(unsigned long bist) /* Set up the console */ i3100_enable_superio(); - i3100_enable_serial(I3100_SUPERIO_CONFIG_PORT, I3100_SP1, TTYS0_BASE); + i3100_enable_serial(I3100_SUPERIO_CONFIG_PORT, I3100_SP1, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/intel/truxton/irq_tables.c b/src/mainboard/intel/truxton/irq_tables.c index ce31ca3385..f7ed1c59e9 100644 --- a/src/mainboard/intel/truxton/irq_tables.c +++ b/src/mainboard/intel/truxton/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ 0x00, /* u8 Bus 0 */ (0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */ 0x0000, /* u16 reserve IRQ for PCI */ diff --git a/src/mainboard/intel/xe7501devkit/Config.lb b/src/mainboard/intel/xe7501devkit/Config.lb index bf5c938dfe..2ac608f066 100644 --- a/src/mainboard/intel/xe7501devkit/Config.lb +++ b/src/mainboard/intel/xe7501devkit/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -9,9 +9,9 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_ACPI_TABLES object acpi_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o end object reset.o # Include the VGA option ROM, but only if we're compiled to use it @@ -29,22 +29,22 @@ end ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -58,8 +58,8 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FALLBACK_BOOT - if USE_FALLBACK_IMAGE +if CONFIG_HAVE_FALLBACK_BOOT + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -85,7 +85,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/intel/xe7501devkit/Options.lb b/src/mainboard/intel/xe7501devkit/Options.lb index d3036df6a7..2420b6a1af 100644 --- a/src/mainboard/intel/xe7501devkit/Options.lb +++ b/src/mainboard/intel/xe7501devkit/Options.lb @@ -1,11 +1,11 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses HAVE_PIRQ_TABLE -uses HAVE_FALLBACK_BOOT -uses HAVE_OPTION_TABLE -uses IRQ_SLOT_COUNT +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_IRQ_SLOT_COUNT uses CONFIG_MAX_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_PHYSICAL_CPUS @@ -14,72 +14,72 @@ uses CONFIG_SMP uses CONFIG_ROM_PAYLOAD uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses DEBUG -#uses CPU_OPT +uses CONFIG_DEBUG +#uses CONFIG_CPU_OPT uses CONFIG_IDE ## The default definitions are used for these uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE +uses CONFIG_PAYLOAD_SIZE ## These are defined in target Config.lb, don't add here -uses USE_FALLBACK_IMAGE -uses ROM_SIZE -uses ROM_IMAGE_SIZE -uses FALLBACK_SIZE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_FALLBACK_SIZE uses COREBOOT_EXTRA_VERSION ## These are defined in mainboard Config.lb, don't add here -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=2097152 -default ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_SIZE=2097152 +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Build code for the fallback boot? ## -default HAVE_FALLBACK_BOOT=1 -default FALLBACK_SIZE=131072 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_FALLBACK_SIZE=131072 ## Delay timer options @@ -90,28 +90,28 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=12 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=12 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## Build code to export ACPI tables? -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## ## Build code to export a CMOS option table? ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ## CMOS checksum definitions (units == bytes) ## These must match the checksum record in cmos.layout -default LB_CKS_RANGE_START=128 -default LB_CKS_RANGE_END=130 -default LB_CKS_LOC=131 +default CONFIG_LB_CKS_RANGE_START=128 +default CONFIG_LB_CKS_RANGE_END=130 +default CONFIG_LB_CKS_LOC=131 ## ## Build code for SMP support @@ -138,10 +138,10 @@ default CONFIG_IOAPIC=1 ## ## Motherboard identification ## -default MAINBOARD_PART_NUMBER="EIDXE7501DEVKIT" -default MAINBOARD_VENDOR="Intel" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480 +default CONFIG_MAINBOARD_PART_NUMBER="EIDXE7501DEVKIT" +default CONFIG_MAINBOARD_VENDOR="Intel" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480 ### ### coreboot layout values @@ -150,22 +150,22 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## CMOS settings not currently supported due to conflicts with factory BIOS ## -default USE_OPTION_TABLE = 0 +default CONFIG_USE_OPTION_TABLE = 0 ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -179,8 +179,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -195,21 +195,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -221,23 +221,23 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ## Things we may not have default CONFIG_IDE=1 -default DEBUG=1 -# default CPU_OPT="-g" +default CONFIG_DEBUG=1 +# default CONFIG_CPU_OPT="-g" ### End Options.lb # diff --git a/src/mainboard/intel/xe7501devkit/auto.c b/src/mainboard/intel/xe7501devkit/auto.c index b106595803..fc845a2ee9 100644 --- a/src/mainboard/intel/xe7501devkit/auto.c +++ b/src/mainboard/intel/xe7501devkit/auto.c @@ -66,7 +66,7 @@ static void main(unsigned long bist) // Get the serial port running and print a welcome banner - lpc47b272_enable_serial(SERIAL_DEV, TTYS0_BASE); + lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/iwill/dk8_htx/Config.lb b/src/mainboard/iwill/dk8_htx/Config.lb index faa294924f..54a66c7939 100644 --- a/src/mainboard/iwill/dk8_htx/Config.lb +++ b/src/mainboard/iwill/dk8_htx/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -15,25 +15,25 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end -#if HAVE_ACPI_TABLES +#if CONFIG_HAVE_ACPI_TABLES # object acpi_tables.o # object fadt.o -# if SB_HT_CHAIN_ON_BUS0 +# if CONFIG_SB_HT_CHAIN_ON_BUS0 # object dsdt_bus0.o # else # object dsdt.o # end # object ssdt.o -# if ACPI_SSDTX_NUM -# if SB_HT_CHAIN_ON_BUS0 +# if CONFIG_ACPI_SSDTX_NUM +# if CONFIG_SB_HT_CHAIN_ON_BUS0 # object ssdt2_bus0.o # else # object ssdt2.o @@ -41,43 +41,43 @@ end # end #end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o object fadt.o makerule dsdt.c - depends "$(MAINBOARD)/dx/dsdt_lb.dsl" - action "iasl -p $(CURDIR)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl" + depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" + action "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" action "mv dsdt_lb.hex dsdt.c" end object ./dsdt.o #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb - if ACPI_SSDTX_NUM + if CONFIG_ACPI_SSDTX_NUM makerule ssdt2.c - depends "$(MAINBOARD)/dx/pci2.asl" - action "iasl -p $(CURDIR)/pci2 -tc $(MAINBOARD)/dx/pci2.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci2.asl" + action "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" action "mv pci2.hex ssdt2.c" end object ./ssdt2.o makerule ssdt3.c - depends "$(MAINBOARD)/dx/pci3.asl" - action "iasl -p $(CURDIR)/pci3 -tc $(MAINBOARD)/dx/pci3.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci3.asl" + action "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex" action "mv pci3.hex ssdt3.c" end object ./ssdt3.o makerule ssdt4.c - depends "$(MAINBOARD)/dx/pci4.asl" - action "iasl -p $(CURDIR)/pci4 -tc $(MAINBOARD)/dx/pci4.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci4.asl" + action "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex" action "mv pci4.hex ssdt4.c" end object ./ssdt4.o makerule ssdt5.c - depends "$(MAINBOARD)/dx/pci5.asl" - action "iasl -p $(CURDIR)/pci5 -tc $(MAINBOARD)/dx/pci5.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci5.asl" + action "iasl -p $(CURDIR)/pci5 -tc $(CONFIG_MAINBOARD)/dx/pci5.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex" action "mv pci5.hex ssdt5.c" end @@ -88,27 +88,27 @@ end if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -118,13 +118,13 @@ end ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -142,8 +142,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -151,7 +151,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -176,12 +176,12 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/iwill/dk8_htx/Options.lb b/src/mainboard/iwill/dk8_htx/Options.lb index 305d8026bc..1f08f6a603 100644 --- a/src/mainboard/iwill/dk8_htx/Options.lb +++ b/src/mainboard/iwill/dk8_htx/Options.lb @@ -1,85 +1,85 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -87,9 +87,9 @@ uses CONFIG_LB_MEM_TOPK uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -98,20 +98,20 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-8K -default FALLBACK_SIZE=0x3e000 +default CONFIG_FALLBACK_SIZE=0x3e000 #FAILOVER: 8K -default FAILOVER_SIZE=0x02000 +default CONFIG_FAILOVER_SIZE=0x02000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -119,42 +119,42 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## extra SSDT num -default ACPI_SSDTX_NUM=3 +default CONFIG_ACPI_SSDTX_NUM=3 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -165,41 +165,41 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -default SERIAL_CPU_INIT=0 +default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -#default HW_MEM_HOLE_SIZEK=0x100000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -default HW_MEM_HOLE_SIZEK=0x80000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 #HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0xa +default CONFIG_HT_CHAIN_UNITID_BASE=0xa #real SB Unit ID, default is 0x20, mean dont touch it at last -default HT_CHAIN_END_UNITID_BASE=0x6 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -207,18 +207,18 @@ default SB_HT_CHAIN_ON_BUS0=2 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc4000 -default DCACHE_RAM_SIZE=0x0c000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc4000 +default CONFIG_DCACHE_RAM_SIZE=0x0c000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 ## ## for rev F training on AP purpose ## #default CONFIG_AP_CODE_IN_CAR=1 -#default MEM_TRAIN_SEQ=1 -#default WAIT_BEFORE_CPUS_INIT=1 +#default CONFIG_MEM_TRAIN_SEQ=1 +#default CONFIG_WAIT_BEFORE_CPUS_INIT=1 ## ## Build code to setup a generic IOAPIC @@ -228,37 +228,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="dk8_htx" -default MAINBOARD_VENDOR="IWILL" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 +default CONFIG_MAINBOARD_PART_NUMBER="dk8_htx" +default CONFIG_MAINBOARD_VENDOR="IWILL" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -272,8 +272,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -289,21 +289,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -315,17 +315,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index c382e3e298..53822bd9d6 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -40,7 +40,7 @@ static void dump_mem(unsigned start, unsigned end) extern unsigned char AmlCode[]; -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 extern unsigned char AmlCode_ssdt2[]; extern unsigned char AmlCode_ssdt3[]; extern unsigned char AmlCode_ssdt4[]; @@ -266,7 +266,7 @@ unsigned long write_acpi_tables(unsigned long start) current += ssdt->length; acpi_add_table(rsdt, ssdt); -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table diff --git a/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c b/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c index cb292bde7b..72c1b86b63 100644 --- a/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c +++ b/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c @@ -19,7 +19,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -34,7 +34,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include <cpu/amd/model_fxx_rev.h> @@ -48,7 +48,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" #include "lib/delay.c" @@ -132,7 +132,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/fidvid.c" #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -177,7 +177,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -191,21 +191,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -221,7 +221,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; int i; unsigned bsp_apicid = 0; @@ -230,7 +230,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -243,7 +243,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c index d49333c261..ae3b25dcb7 100644 --- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c +++ b/src/mainboard/iwill/dk8_htx/get_bus_conf.c @@ -109,7 +109,7 @@ void get_bus_conf(void) dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); if (dev) { m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); m->bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); @@ -132,7 +132,7 @@ void get_bus_conf(void) dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0)); if (dev) { m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); m->bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); diff --git a/src/mainboard/iwill/dk8s2/Config.lb b/src/mainboard/iwill/dk8s2/Config.lb index bf1806b440..8f34a30aa3 100644 --- a/src/mainboard/iwill/dk8s2/Config.lb +++ b/src/mainboard/iwill/dk8s2/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -13,8 +13,8 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ATI Rage XL framebuffering graphics driver @@ -23,15 +23,15 @@ dir /drivers/ati/ragexl if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -41,7 +41,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -59,7 +59,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -83,7 +83,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/iwill/dk8s2/Options.lb b/src/mainboard/iwill/dk8s2/Options.lb index 6c0fb018c3..e9a3bafc34 100644 --- a/src/mainboard/iwill/dk8s2/Options.lb +++ b/src/mainboard/iwill/dk8s2/Options.lb @@ -1,106 +1,106 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE=524288 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE=524288 ### ### Build options ### ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=9 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -118,46 +118,46 @@ default CONFIG_IOAPIC=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="HDAMA" -default MAINBOARD_VENDOR="ARIMA" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 +default CONFIG_MAINBOARD_PART_NUMBER="HDAMA" +default CONFIG_MAINBOARD_VENDOR="ARIMA" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -171,8 +171,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -#default CC="$(CROSS_COMPILE)gcc -m32" -#default HOSTCC="gcc" +#default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +#default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -189,21 +189,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -215,17 +215,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c b/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c index 6716a55825..51617ab0ce 100644 --- a/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c +++ b/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c @@ -19,7 +19,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -34,7 +34,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include <cpu/amd/model_fxx_rev.h> @@ -48,7 +48,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" #include "lib/delay.c" @@ -132,7 +132,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/fidvid.c" #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -177,7 +177,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -191,21 +191,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -221,7 +221,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; int i; unsigned bsp_apicid = 0; @@ -230,7 +230,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -243,7 +243,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/iwill/dk8x/Config.lb b/src/mainboard/iwill/dk8x/Config.lb index 216cceb172..7e2dd6dbf5 100644 --- a/src/mainboard/iwill/dk8x/Config.lb +++ b/src/mainboard/iwill/dk8x/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -13,22 +13,22 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -38,7 +38,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -56,7 +56,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -80,7 +80,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/iwill/dk8x/Options.lb b/src/mainboard/iwill/dk8x/Options.lb index a515945180..5b6cd23ed4 100644 --- a/src/mainboard/iwill/dk8x/Options.lb +++ b/src/mainboard/iwill/dk8x/Options.lb @@ -1,106 +1,106 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE=524288 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE=524288 ### ### Build options ### ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=9 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -118,45 +118,45 @@ default CONFIG_IOAPIC=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## ## Clean up the motherboard id strings ## -#default MAINBOARD_PART_NUMBER="HDAMA" -#default MAINBOARD_VENDOR="ARIMA" -#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 +#default CONFIG_MAINBOARD_PART_NUMBER="HDAMA" +#default CONFIG_MAINBOARD_VENDOR="ARIMA" +#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f +#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -170,8 +170,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -#default CC="$(CROSS_COMPILE)gcc -m32" -#default HOSTCC="gcc" +#default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +#default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -188,21 +188,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -214,17 +214,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/iwill/dk8x/cache_as_ram_auto.c b/src/mainboard/iwill/dk8x/cache_as_ram_auto.c index 6716a55825..51617ab0ce 100644 --- a/src/mainboard/iwill/dk8x/cache_as_ram_auto.c +++ b/src/mainboard/iwill/dk8x/cache_as_ram_auto.c @@ -19,7 +19,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -34,7 +34,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include <cpu/amd/model_fxx_rev.h> @@ -48,7 +48,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" #include "lib/delay.c" @@ -132,7 +132,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/fidvid.c" #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -177,7 +177,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -191,21 +191,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -221,7 +221,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; int i; unsigned bsp_apicid = 0; @@ -230,7 +230,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -243,7 +243,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/iwill/dk8x/irq_tables.c b/src/mainboard/iwill/dk8x/irq_tables.c index 6322c3df21..1f35cbaef2 100644 --- a/src/mainboard/iwill/dk8x/irq_tables.c +++ b/src/mainboard/iwill/dk8x/irq_tables.c @@ -18,7 +18,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT * devices on the bus */ IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ diff --git a/src/mainboard/jetway/j7f24/Config.lb b/src/mainboard/jetway/j7f24/Config.lb index 832fe36251..bd33c3ffc1 100644 --- a/src/mainboard/jetway/j7f24/Config.lb +++ b/src/mainboard/jetway/j7f24/Config.lb @@ -19,40 +19,40 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_MP_TABLE object mptable.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_ACPI_TABLES object fadt.o object dsdt.o object acpi_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -62,7 +62,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/jetway/j7f24/Options.lb b/src/mainboard/jetway/j7f24/Options.lb index 1000212827..0bc79aa261 100644 --- a/src/mainboard/jetway/j7f24/Options.lb +++ b/src/mainboard/jetway/j7f24/Options.lb @@ -19,83 +19,83 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_PCI_ROM_RUN uses CONFIG_CONSOLE_VGA uses CONFIG_MAX_PCI_BUSES -uses TTYS0_BAUD +uses CONFIG_TTYS0_BAUD uses CONFIG_VIDEO_MB uses CONFIG_IOAPIC -default ROM_SIZE = 512 * 1024 +default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_IOAPIC = 0 default CONFIG_VIDEO_MB = 32 default CONFIG_CONSOLE_SERIAL8250 = 1 default CONFIG_PCI_ROM_RUN = 0 default CONFIG_CONSOLE_VGA = 0 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_HARD_RESET = 0 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 10 -default HAVE_ACPI_TABLES = 0 -default HAVE_OPTION_TABLE = 0 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = ROM_SIZE -default USE_FALLBACK_IMAGE = 1 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -#default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 10 +default CONFIG_HAVE_ACPI_TABLES = 0 +default CONFIG_HAVE_OPTION_TABLE = 0 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE +default CONFIG_USE_FALLBACK_IMAGE = 1 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +#default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector" +default CONFIG_HOSTCC = "gcc" ## ## Set this to the max PCI bus number you would ever use for PCI config I/O. diff --git a/src/mainboard/jetway/j7f24/auto.c b/src/mainboard/jetway/j7f24/auto.c index 15764e932c..59697259cf 100644 --- a/src/mainboard/jetway/j7f24/auto.c +++ b/src/mainboard/jetway/j7f24/auto.c @@ -40,7 +40,7 @@ #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "superio/fintek/f71805f/f71805f_early_serial.c" -#if TTYS0_BASE == 0x2f8 +#if CONFIG_TTYS0_BASE == 0x2f8 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2) #else #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP1) @@ -101,7 +101,7 @@ static void main(unsigned long bist) /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - f71805f_enable_serial(SERIAL_DEV, TTYS0_BASE); + f71805f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/jetway/j7f24/irq_tables.c b/src/mainboard/jetway/j7f24/irq_tables.c index fef553e219..9037e344a2 100644 --- a/src/mainboard/jetway/j7f24/irq_tables.c +++ b/src/mainboard/jetway/j7f24/irq_tables.c @@ -24,7 +24,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x11 << 3) | 0x0, /* Interrupt router device */ 0x828, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/kontron/986lcd-m/Config.lb b/src/mainboard/kontron/986lcd-m/Config.lb index 303b4e5840..b768bf326c 100644 --- a/src/mainboard/kontron/986lcd-m/Config.lb +++ b/src/mainboard/kontron/986lcd-m/Config.lb @@ -26,10 +26,10 @@ ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -44,16 +44,16 @@ arch i386 end driver mainboard.o driver rtl8168.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_SMI_HANDLER smmobject mainboard_smi.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_SMI_HANDLER smmobject mainboard_smi.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object fadt.o object acpi_tables.o makerule dsdt.c - depends "$(MAINBOARD)/dsdt.asl" - action "iasl -p dsdt -tc $(MAINBOARD)/dsdt.asl" + depends "$(CONFIG_MAINBOARD)/dsdt.asl" + action "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" action "mv $(CURDIR)/dsdt.hex dsdt.c" end object ./dsdt.o @@ -64,15 +64,15 @@ object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -93,7 +93,7 @@ end ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -118,7 +118,7 @@ mainboardinit cpu/intel/model_6ex/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/kontron/986lcd-m/Options.lb b/src/mainboard/kontron/986lcd-m/Options.lb index f4ab0dfd77..07c139f98a 100644 --- a/src/mainboard/kontron/986lcd-m/Options.lb +++ b/src/mainboard/kontron/986lcd-m/Options.lb @@ -20,17 +20,17 @@ ## # Tables -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses HAVE_MAINBOARD_RESOURCES +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_HAVE_MAINBOARD_RESOURCES # SMP uses CONFIG_SMP uses CONFIG_LOGICAL_CPUS @@ -39,71 +39,71 @@ uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_IOAPIC # Image Size -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET # Payload uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE +uses CONFIG_PAYLOAD_SIZE # Build Internals -uses _RAMBASE -uses _ROMBASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_RAMBASE +uses CONFIG_ROMBASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses XIP_ROM_BASE -uses XIP_ROM_SIZE -uses HAVE_HARD_RESET -uses HAVE_SMI_HANDLER +uses CONFIG_XIP_ROM_BASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_SMI_HANDLER uses CONFIG_PCIE_CONFIGSPACE_HOLE -uses MMCONF_SUPPORT -uses MMCONF_BASE_ADDRESS +uses CONFIG_MMCONF_SUPPORT +uses CONFIG_MMCONF_BASE_ADDRESS uses CONFIG_GFXUMA uses CONFIG_CBFS # -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID # Timers uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 # Console uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_VGA uses CONFIG_VGA_ROM_RUN uses CONFIG_PCI_ROM_RUN -uses DEBUG +uses CONFIG_DEBUG # Toolchain uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY # Tweaks uses CONFIG_GDB_STUB -uses MAX_REBOOT_CNT -uses USE_WATCHDOG_ON_BOOT +uses CONFIG_MAX_REBOOT_CNT +uses CONFIG_USE_WATCHDOG_ON_BOOT uses COREBOOT_EXTRA_VERSION -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL ### ### Build options @@ -111,23 +111,23 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL ## ## -default MAX_REBOOT_CNT=3 +default CONFIG_MAX_REBOOT_CNT=3 ## ## Use the watchdog to break out of a lockup condition ## -default USE_WATCHDOG_ON_BOOT=0 +default CONFIG_USE_WATCHDOG_ON_BOOT=0 ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1024*1024 +default CONFIG_ROM_SIZE=1024*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -139,20 +139,20 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build SMI handler ## -default HAVE_SMI_HANDLER=1 +default CONFIG_HAVE_SMI_HANDLER=1 ## ## Leave a hole for mmapped PCIe config space ## default CONFIG_PCIE_CONFIGSPACE_HOLE=1 -default MMCONF_SUPPORT=1 -default MMCONF_BASE_ADDRESS=0xf0000000 +default CONFIG_MMCONF_SUPPORT=1 +default CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 ## ## UMA @@ -162,32 +162,32 @@ default CONFIG_GFXUMA=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=18 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=18 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to provide ACPI support ## -default HAVE_ACPI_TABLES=1 -default HAVE_MAINBOARD_RESOURCES=1 +default CONFIG_HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_MAINBOARD_RESOURCES=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -196,7 +196,7 @@ default CONFIG_CONSOLE_VGA=1 # for now: default CONFIG_VGA_ROM_RUN=1 default CONFIG_PCI_ROM_RUN=0 -default DEBUG=0 +default CONFIG_DEBUG=0 ## ## Build code for SMP support @@ -211,9 +211,9 @@ default CONFIG_AP_IN_SIPI_WAIT=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_SIZE=0x8000 -default DCACHE_RAM_BASE=( 0xfff00000 - DCACHE_RAM_SIZE - 1024*1024) +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_SIZE=0x8000 +default CONFIG_DCACHE_RAM_BASE=( 0xfff00000 - CONFIG_DCACHE_RAM_SIZE - 1024*1024) default CONFIG_USE_PRINTK_IN_CAR=1 ## @@ -224,37 +224,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="986LCD-M" -default MAINBOARD_VENDOR= "KONTRON" +default CONFIG_MAINBOARD_PART_NUMBER="986LCD-M" +default CONFIG_MAINBOARD_VENDOR= "KONTRON" ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=ROM_IMAGE_SIZE +default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE ## ## coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -268,8 +268,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -284,21 +284,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -310,17 +310,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=5 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" # # CBFS diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c index 2f9c1ec71f..c7c060f0a3 100644 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c @@ -313,7 +313,7 @@ unsigned long write_acpi_tables(unsigned long start) printk_debug("ACPI: * DMI (Linux workaround)\n"); memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); -#if HAVE_HIGH_TABLES == 1 +#if CONFIG_HAVE_HIGH_TABLES == 1 memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); current += DMI_TABLE_SIZE; ALIGN_CURRENT; diff --git a/src/mainboard/kontron/986lcd-m/auto.c b/src/mainboard/kontron/986lcd-m/auto.c index 06023e67af..781ef2ceba 100644 --- a/src/mainboard/kontron/986lcd-m/auto.c +++ b/src/mainboard/kontron/986lcd-m/auto.c @@ -296,7 +296,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/intel/i82801gx/cmos_failover.c" #endif @@ -331,7 +331,7 @@ void real_main(unsigned long bist) /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if DEFAULT_CONSOLE_LOGLEVEL > 8 +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif @@ -351,7 +351,7 @@ void real_main(unsigned long bist) /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(); -#if DEFAULT_CONSOLE_LOGLEVEL > 8 +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 #if defined(DEBUG_RAM_SETUP) sdram_dump_mchbar_registers(); #endif diff --git a/src/mainboard/lippert/frontrunner/Config.lb b/src/mainboard/lippert/frontrunner/Config.lb index 4dc35b58f1..daf513380f 100644 --- a/src/mainboard/lippert/frontrunner/Config.lb +++ b/src/mainboard/lippert/frontrunner/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,29 +14,29 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -50,7 +50,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -72,7 +72,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/lippert/frontrunner/Options.lb b/src/mainboard/lippert/frontrunner/Options.lb index 70c05bfa56..eff01c1087 100644 --- a/src/mainboard/lippert/frontrunner/Options.lb +++ b/src/mainboard/lippert/frontrunner/Options.lb @@ -1,50 +1,50 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -53,17 +53,17 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -73,49 +73,49 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=2 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=2 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -125,21 +125,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -151,13 +151,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/lippert/frontrunner/auto.c b/src/mainboard/lippert/frontrunner/auto.c index 781fe1d0d2..3bcad1f714 100644 --- a/src/mainboard/lippert/frontrunner/auto.c +++ b/src/mainboard/lippert/frontrunner/auto.c @@ -84,7 +84,7 @@ static void main(unsigned long bist) SystemPreInit(); msr_init(); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/lippert/roadrunner-lx/Config.lb b/src/mainboard/lippert/roadrunner-lx/Config.lb index 21c75d60fa..00b6713896 100644 --- a/src/mainboard/lippert/roadrunner-lx/Config.lb +++ b/src/mainboard/lippert/roadrunner-lx/Config.lb @@ -20,8 +20,8 @@ ## Based on Config.lb from AMD's DB800 and DBM690T mainboards. -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -36,14 +36,14 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/.rodata/.rom.data/g' -pi $@" action "perl -e 's/.text/.section .rom.text/g' -pi $@" end @@ -59,7 +59,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -81,7 +81,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds # mainboardinit ./failover.inc end diff --git a/src/mainboard/lippert/roadrunner-lx/Options.lb b/src/mainboard/lippert/roadrunner-lx/Options.lb index d91f602534..530c43ea78 100644 --- a/src/mainboard/lippert/roadrunner-lx/Options.lb +++ b/src/mainboard/lippert/roadrunner-lx/Options.lb @@ -20,69 +20,69 @@ ## Based on Options.lb from AMD's DB800 mainboard. -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD uses CONFIG_IDE uses CONFIG_FS_PAYLOAD uses CONFIG_FS_EXT2 -uses AUTOBOOT_DELAY -uses AUTOBOOT_CMDLINE -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_AUTOBOOT_DELAY +uses CONFIG_AUTOBOOT_CMDLINE +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESS uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEBUG -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEBUG +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 512 * 1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 512 * 1024 ### ### Build options @@ -94,17 +94,17 @@ default CONFIG_PCI_ROM_RUN = 0 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_FALLBACK_BOOT = 1 ## ## no MP table ## -default HAVE_MP_TABLE = 0 +default CONFIG_HAVE_MP_TABLE = 0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET = 0 +default CONFIG_HAVE_HARD_RESET = 0 ## Delay timer options ## @@ -114,57 +114,57 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 7 -default PIRQ_ROUTE = 1 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 7 +default CONFIG_PIRQ_ROUTE = 1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE = 0 +default CONFIG_HAVE_OPTION_TABLE = 0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xc8000 -default DCACHE_RAM_SIZE = 0x08000 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xc8000 +default CONFIG_DCACHE_RAM_SIZE = 0x08000 default CONFIG_USE_PRINTK_IN_CAR=1 ## ## Use a small 8K stack ## -default STACK_SIZE = 8 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 ## ## Use a small 16K heap ## -default HEAP_SIZE = 16 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" ## ## The Serial Console @@ -174,24 +174,24 @@ default HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 ## Select the serial console baud rate -default TTYS0_BAUD = 115200 -#default TTYS0_BAUD = 57600 -#default TTYS0_BAUD = 38400 -#default TTYS0_BAUD = 19200 -#default TTYS0_BAUD = 9600 -#default TTYS0_BAUD = 4800 -#default TTYS0_BAUD = 2400 -#default TTYS0_BAUD = 1200 +default CONFIG_TTYS0_BAUD = 115200 +#default CONFIG_TTYS0_BAUD = 57600 +#default CONFIG_TTYS0_BAUD = 38400 +#default CONFIG_TTYS0_BAUD = 19200 +#default CONFIG_TTYS0_BAUD = 9600 +#default CONFIG_TTYS0_BAUD = 4800 +#default CONFIG_TTYS0_BAUD = 2400 +#default CONFIG_TTYS0_BAUD = 1200 # Select the serial console base port -default TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_BASE = 0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS = 0x3 +default CONFIG_TTYS0_LCS = 0x3 # Compile extra debugging code -default DEBUG = 1 +default CONFIG_DEBUG = 1 ## ### Select the coreboot loglevel @@ -203,13 +203,13 @@ default DEBUG = 1 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL = 8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL = 8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 # # CBFS diff --git a/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c b/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c index 660a9de02f..6a07a05e44 100644 --- a/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c +++ b/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c @@ -103,7 +103,7 @@ static const u16 sio_init_table[] = { // hi=data, lo=index 0x1E2C, // disable ATXPowerGood - will cause a reboot! 0x0423, // don't delay POWerOK1/2 0x9072, // watchdog triggers POWOK, counts seconds -#if !USE_WATCHDOG_ON_BOOT +#if !CONFIG_USE_WATCHDOG_ON_BOOT 0x0073, 0x0074, // disable watchdog by setting timeout to 0 #endif 0xBF25, 0x372A, 0xF326, // select GPIO function for most pins @@ -149,7 +149,7 @@ void cache_as_ram_main(void) * Note: must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - it8712f_enable_serial(0, TTYS0_BASE); // Does not use its 1st parameter + it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter mb_gpio_init(); uart_init(); console_init(); diff --git a/src/mainboard/lippert/roadrunner-lx/irq_tables.c b/src/mainboard/lippert/roadrunner-lx/irq_tables.c index 4ee33d4245..0e7572da90 100644 --- a/src/mainboard/lippert/roadrunner-lx/irq_tables.c +++ b/src/mainboard/lippert/roadrunner-lx/irq_tables.c @@ -47,7 +47,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT,/* there can be total 7 devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* there can be total 7 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -57,7 +57,7 @@ const struct irq_routing_table intel_irq_routing_table = { {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0xE0, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ + /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ diff --git a/src/mainboard/lippert/spacerunner-lx/Config.lb b/src/mainboard/lippert/spacerunner-lx/Config.lb index 0c2866a743..b74ce8b911 100644 --- a/src/mainboard/lippert/spacerunner-lx/Config.lb +++ b/src/mainboard/lippert/spacerunner-lx/Config.lb @@ -20,8 +20,8 @@ ## Based on Config.lb from AMD's DB800 and DBM690T mainboards. -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -35,14 +35,14 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -58,7 +58,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -80,7 +80,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds # mainboardinit ./failover.inc end diff --git a/src/mainboard/lippert/spacerunner-lx/Options.lb b/src/mainboard/lippert/spacerunner-lx/Options.lb index 5d8dd0981a..805148b7f2 100644 --- a/src/mainboard/lippert/spacerunner-lx/Options.lb +++ b/src/mainboard/lippert/spacerunner-lx/Options.lb @@ -20,69 +20,69 @@ ## Based on Options.lb from AMD's DB800 mainboard. -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD uses CONFIG_IDE uses CONFIG_FS_PAYLOAD uses CONFIG_FS_EXT2 -uses AUTOBOOT_DELAY -uses AUTOBOOT_CMDLINE -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_AUTOBOOT_DELAY +uses CONFIG_AUTOBOOT_CMDLINE +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESS uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEBUG -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEBUG +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 512*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 512*1024 ### ### Build options @@ -94,17 +94,17 @@ default CONFIG_PCI_ROM_RUN = 0 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_FALLBACK_BOOT = 1 ## ## no MP table ## -default HAVE_MP_TABLE = 0 +default CONFIG_HAVE_MP_TABLE = 0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET = 0 +default CONFIG_HAVE_HARD_RESET = 0 ## Delay timer options ## @@ -114,57 +114,57 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 7 -default PIRQ_ROUTE = 1 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 7 +default CONFIG_PIRQ_ROUTE = 1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE = 0 +default CONFIG_HAVE_OPTION_TABLE = 0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xc8000 -default DCACHE_RAM_SIZE = 0x08000 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xc8000 +default CONFIG_DCACHE_RAM_SIZE = 0x08000 default CONFIG_USE_PRINTK_IN_CAR=1 ## ## Use a small 8K stack ## -default STACK_SIZE = 0x2000 +default CONFIG_STACK_SIZE = 0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE = 0x4000 +default CONFIG_HEAP_SIZE = 0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" ## ## The Serial Console @@ -174,24 +174,24 @@ default HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 ## Select the serial console baud rate -default TTYS0_BAUD = 115200 -#default TTYS0_BAUD = 57600 -#default TTYS0_BAUD = 38400 -#default TTYS0_BAUD = 19200 -#default TTYS0_BAUD = 9600 -#default TTYS0_BAUD = 4800 -#default TTYS0_BAUD = 2400 -#default TTYS0_BAUD = 1200 +default CONFIG_TTYS0_BAUD = 115200 +#default CONFIG_TTYS0_BAUD = 57600 +#default CONFIG_TTYS0_BAUD = 38400 +#default CONFIG_TTYS0_BAUD = 19200 +#default CONFIG_TTYS0_BAUD = 9600 +#default CONFIG_TTYS0_BAUD = 4800 +#default CONFIG_TTYS0_BAUD = 2400 +#default CONFIG_TTYS0_BAUD = 1200 # Select the serial console base port -default TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_BASE = 0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS = 0x3 +default CONFIG_TTYS0_LCS = 0x3 # Compile extra debugging code -default DEBUG = 1 +default CONFIG_DEBUG = 1 ## ### Select the coreboot loglevel @@ -203,13 +203,13 @@ default DEBUG = 1 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL = 8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL = 8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 # # CBFS diff --git a/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c b/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c index 08be2de149..af26262387 100644 --- a/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c +++ b/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c @@ -89,7 +89,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) if (device != DIMM0) return 0xFF; /* No DIMM1, don't even try. */ -#if DEBUG +#if CONFIG_DEBUG if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) { print_err("ERROR: spd_read_byte(DIMM0, 0x"); print_err_hex8(address); @@ -165,7 +165,7 @@ static const u16 sio_init_table[] = { // hi=data, lo=index 0x1E2C, // disable ATXPowerGood 0x0423, // don't delay POWerOK1/2 0x9072, // watchdog triggers POWOK, counts seconds -#if !USE_WATCHDOG_ON_BOOT +#if !CONFIG_USE_WATCHDOG_ON_BOOT 0x0073, 0x0074, // disable watchdog by setting timeout to 0 #endif 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins @@ -211,7 +211,7 @@ void cache_as_ram_main(void) * Note: Must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - it8712f_enable_serial(0, TTYS0_BASE); // Does not use its 1st parameter + it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter mb_gpio_init(); uart_init(); console_init(); diff --git a/src/mainboard/lippert/spacerunner-lx/irq_tables.c b/src/mainboard/lippert/spacerunner-lx/irq_tables.c index df2b20a969..5350b57a4d 100644 --- a/src/mainboard/lippert/spacerunner-lx/irq_tables.c +++ b/src/mainboard/lippert/spacerunner-lx/irq_tables.c @@ -47,7 +47,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT,/* There can be total 7 devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* There can be total 7 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -57,7 +57,7 @@ const struct irq_routing_table intel_irq_routing_table = { {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0xE0, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ + /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ diff --git a/src/mainboard/motorola/sandpoint/Config.lb b/src/mainboard/motorola/sandpoint/Config.lb index ee6abf85fd..5ed46bd3b7 100644 --- a/src/mainboard/motorola/sandpoint/Config.lb +++ b/src/mainboard/motorola/sandpoint/Config.lb @@ -15,7 +15,7 @@ initobject clock.o object clock.o ## -## Set our ARCH +## Set our CONFIG_ARCH ## arch ppc end @@ -26,5 +26,5 @@ arch ppc end dir nvram dir flash -addaction coreboot.a "$(CROSS_COMPILE)ranlib coreboot.a" +addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a" makedefine CFLAGS += -g diff --git a/src/mainboard/motorola/sandpoint/Options.lb b/src/mainboard/motorola/sandpoint/Options.lb index 239ebc4a08..7d50c39ce1 100644 --- a/src/mainboard/motorola/sandpoint/Options.lb +++ b/src/mainboard/motorola/sandpoint/Options.lb @@ -5,70 +5,70 @@ uses CONFIG_SANDPOINT_TALUS uses CONFIG_SANDPOINT_UNITY uses CONFIG_SANDPOINT_VALIS uses CONFIG_SANDPOINT_GYRUS -uses ISA_IO_BASE -uses ISA_MEM_BASE -uses PCIC0_CFGADDR -uses PCIC0_CFGDATA -uses PNP_CFGADDR -uses PNP_CFGDATA -uses _IO_BASE - -uses CROSS_COMPILE -uses HAVE_OPTION_TABLE +uses CONFIG_ISA_IO_BASE +uses CONFIG_ISA_MEM_BASE +uses CONFIG_PCIC0_CFGADDR +uses CONFIG_PCIC0_CFGDATA +uses CONFIG_PNP_CFGADDR +uses CONFIG_PNP_CFGDATA +uses CONFIG_IO_BASE + +uses CONFIG_CROSS_COMPILE +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_SANDPOINT_ALTIMUS uses CONFIG_COMPRESS -uses DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_USE_INIT uses CONFIG_CHIP_CONFIGURE -uses NO_POST +uses CONFIG_NO_POST uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BASE +uses CONFIG_TTYS0_BASE uses CONFIG_IDE uses CONFIG_FS_PAYLOAD uses CONFIG_FS_EXT2 uses CONFIG_FS_ISO9660 uses CONFIG_FS_FAT -uses AUTOBOOT_CMDLINE -uses PAYLOAD_SIZE -uses ROM_SIZE -uses ROM_IMAGE_SIZE -uses _RESET -uses _EXCEPTION_VECTORS -uses _ROMBASE -uses _ROMSTART -uses _RAMBASE -uses _RAMSTART -uses STACK_SIZE -uses HEAP_SIZE - -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_AUTOBOOT_CMDLINE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_RESET +uses CONFIG_EXCEPTION_VECTORS +uses CONFIG_ROMBASE +uses CONFIG_ROMSTART +uses CONFIG_RAMBASE +uses CONFIG_RAMSTART +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE + +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY ## ## Set memory map ## -default ISA_IO_BASE=0xfe000000 -default ISA_MEM_BASE=0xfd000000 -default PCIC0_CFGADDR=0xfec00000 -default PCIC0_CFGDATA=0xfee00000 -default PNP_CFGADDR=0x15c -default PNP_CFGDATA=0x15d -default _IO_BASE=ISA_IO_BASE +default CONFIG_ISA_IO_BASE=0xfe000000 +default CONFIG_ISA_MEM_BASE=0xfd000000 +default CONFIG_PCIC0_CFGADDR=0xfec00000 +default CONFIG_PCIC0_CFGDATA=0xfee00000 +default CONFIG_PNP_CFGADDR=0x15c +default CONFIG_PNP_CFGDATA=0x15d +default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc" +default CONFIG_HOSTCC="gcc" ## use a cross compiler -#default CROSS_COMPILE="powerpc-eabi-" -#default CROSS_COMPILE="ppc_74xx-" +#default CONFIG_CROSS_COMPILE="powerpc-eabi-" +#default CONFIG_CROSS_COMPILE="ppc_74xx-" default CONFIG_ARCH_X86=0 ## Use stage 1 initialization code @@ -81,12 +81,12 @@ default CONFIG_CHIP_CONFIGURE=1 default CONFIG_COMPRESS=0 ## Turn off POST codes -default NO_POST=1 +default CONFIG_NO_POST=1 ## Enable serial console -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 default CONFIG_CONSOLE_SERIAL8250=1 -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 ## Load payload using filo default CONFIG_IDE=1 @@ -94,34 +94,34 @@ default CONFIG_FS_PAYLOAD=1 default CONFIG_FS_EXT2=1 default CONFIG_FS_ISO9660=1 default CONFIG_FS_FAT=1 -default AUTOBOOT_CMDLINE="hdc1:/vmlinuz" +default CONFIG_AUTOBOOT_CMDLINE="hdc1:/vmlinuz" # coreboot must fit into 128KB -default ROM_IMAGE_SIZE=131072 -default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE} -default PAYLOAD_SIZE=262144 +default CONFIG_ROM_IMAGE_SIZE=131072 +default CONFIG_ROM_SIZE={CONFIG_ROM_IMAGE_SIZE+CONFIG_PAYLOAD_SIZE} +default CONFIG_PAYLOAD_SIZE=262144 # Set stack and heap sizes (stage 2) -default STACK_SIZE=0x10000 -default HEAP_SIZE=0x10000 +default CONFIG_STACK_SIZE=0x10000 +default CONFIG_HEAP_SIZE=0x10000 # Sandpoint Demo Board ## Base of ROM -default _ROMBASE=0xfff00000 +default CONFIG_ROMBASE=0xfff00000 ## Sandpoint reset vector -default _RESET=_ROMBASE+0x100 +default CONFIG_RESET=CONFIG_ROMBASE+0x100 ## Exception vectors (other than reset vector) -default _EXCEPTION_VECTORS=_RESET+0x100 +default CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100 ## Start of coreboot in the boot rom -## = _RESET + exeception vector table size -default _ROMSTART=_RESET+0x3100 +## = CONFIG_RESET + exeception vector table size +default CONFIG_ROMSTART=CONFIG_RESET+0x3100 ## Coreboot C code runs at this location in RAM -default _RAMBASE=0x00100000 -default _RAMSTART=0x00100000 +default CONFIG_RAMBASE=0x00100000 +default CONFIG_RAMSTART=0x00100000 default CONFIG_SANDPOINT_ALTIMUS=1 diff --git a/src/mainboard/motorola/sandpoint/init.c b/src/mainboard/motorola/sandpoint/init.c index 567a6aed70..42acd35164 100644 --- a/src/mainboard/motorola/sandpoint/init.c +++ b/src/mainboard/motorola/sandpoint/init.c @@ -38,8 +38,8 @@ void pnp_output(char address, char data) { - outb(address, PNP_CFGADDR); - outb(data, PNP_CFGDATA); + outb(address, CONFIG_PNP_CFGADDR); + outb(data, CONFIG_PNP_CFGDATA); } void @@ -55,10 +55,10 @@ board_init(void) */ pnp_output(0x07, 6); /* LD 6 = UART0 */ pnp_output(0x30, 0); /* Dectivate */ - pnp_output(0x60, TTYS0_BASE >> 8); /* IO Base */ - pnp_output(0x61, TTYS0_BASE & 0xFF); /* IO Base */ + pnp_output(0x60, CONFIG_TTYS0_BASE >> 8); /* IO Base */ + pnp_output(0x61, CONFIG_TTYS0_BASE & 0xFF); /* IO Base */ pnp_output(0x30, 1); /* Activate */ - uart8250_init(TTYS0_BASE, 115200/TTYS0_BAUD, TTYS0_LCS); + uart8250_init(CONFIG_TTYS0_BASE, 115200/CONFIG_TTYS0_BAUD, CONFIG_TTYS0_LCS); } void diff --git a/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb b/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb index 42b183f916..1a47974bf8 100644 --- a/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb +++ b/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb @@ -1,22 +1,22 @@ -uses ISA_IO_BASE +uses CONFIG_ISA_IO_BASE uses CONFIG_CBFS -uses ISA_MEM_BASE -uses PCIC0_CFGADDR -uses PCIC0_CFGDATA -uses PNP_CFGADDR -uses PNP_CFGDATA -uses _IO_BASE - -uses CROSS_COMPILE -uses HAVE_OPTION_TABLE +uses CONFIG_ISA_MEM_BASE +uses CONFIG_PCIC0_CFGADDR +uses CONFIG_PCIC0_CFGDATA +uses CONFIG_PNP_CFGADDR +uses CONFIG_PNP_CFGDATA +uses CONFIG_IO_BASE + +uses CONFIG_CROSS_COMPILE +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_SANDPOINT_ALTIMUS uses CONFIG_COMPRESS -uses DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_USE_INIT uses CONFIG_CHIP_CONFIGURE -uses NO_POST +uses CONFIG_NO_POST uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BASE +uses CONFIG_TTYS0_BASE uses CONFIG_IDE uses CONFIG_FS_PAYLOAD uses CONFIG_FS_EXT2 @@ -24,47 +24,47 @@ uses CONFIG_FS_ISO9660 uses CONFIG_FS_FAT uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses AUTOBOOT_CMDLINE -uses PAYLOAD_SIZE -uses ROM_SIZE -uses ROM_IMAGE_SIZE -uses _RESET -uses _EXCEPTION_VECTORS -uses _ROMBASE -uses _ROMSTART -uses _RAMBASE -uses _RAMSTART -uses STACK_SIZE -uses HEAP_SIZE - -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_AUTOBOOT_CMDLINE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_RESET +uses CONFIG_EXCEPTION_VECTORS +uses CONFIG_ROMBASE +uses CONFIG_ROMSTART +uses CONFIG_RAMBASE +uses CONFIG_RAMSTART +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE + +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY ## ## Set memory map ## -default ISA_IO_BASE=0xfe000000 -default ISA_MEM_BASE=0xfd000000 -default PCIC0_CFGADDR=0xfec00000 -default PCIC0_CFGDATA=0xfee00000 -default PNP_CFGADDR=0x15c -default PNP_CFGDATA=0x15d -default _IO_BASE=ISA_IO_BASE +default CONFIG_ISA_IO_BASE=0xfe000000 +default CONFIG_ISA_MEM_BASE=0xfd000000 +default CONFIG_PCIC0_CFGADDR=0xfec00000 +default CONFIG_PCIC0_CFGDATA=0xfee00000 +default CONFIG_PNP_CFGADDR=0x15c +default CONFIG_PNP_CFGDATA=0x15d +default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc" +default CONFIG_HOSTCC="gcc" ## use a cross compiler -#default CROSS_COMPILE="powerpc-eabi-" -#default CROSS_COMPILE="ppc_74xx-" +#default CONFIG_CROSS_COMPILE="powerpc-eabi-" +#default CONFIG_CROSS_COMPILE="ppc_74xx-" ## Use stage 1 initialization code default CONFIG_USE_INIT=1 @@ -76,12 +76,12 @@ default CONFIG_CHIP_CONFIGURE=1 default CONFIG_COMPRESS=0 ## Turn off POST codes -default NO_POST=1 +default CONFIG_NO_POST=1 ## Enable serial console -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 default CONFIG_CONSOLE_SERIAL8250=1 -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 ## Load payload using filo default CONFIG_IDE=1 @@ -89,34 +89,34 @@ default CONFIG_FS_PAYLOAD=1 default CONFIG_FS_EXT2=1 default CONFIG_FS_ISO9660=1 default CONFIG_FS_FAT=1 -default AUTOBOOT_CMDLINE="hdc1:/vmlinuz" +default CONFIG_AUTOBOOT_CMDLINE="hdc1:/vmlinuz" # coreboot must fit into 128KB -default ROM_IMAGE_SIZE=131072 -default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE} -default PAYLOAD_SIZE=262144 +default CONFIG_ROM_IMAGE_SIZE=131072 +default CONFIG_ROM_SIZE={CONFIG_ROM_IMAGE_SIZE+CONFIG_PAYLOAD_SIZE} +default CONFIG_PAYLOAD_SIZE=262144 # Set stack and heap sizes (stage 2) -default STACK_SIZE=0x10000 -default HEAP_SIZE=0x10000 +default CONFIG_STACK_SIZE=0x10000 +default CONFIG_HEAP_SIZE=0x10000 # Sandpoint Demo Board ## Base of ROM -default _ROMBASE=0xfff00000 +default CONFIG_ROMBASE=0xfff00000 ## Sandpoint reset vector -default _RESET=_ROMBASE+0x100 +default CONFIG_RESET=CONFIG_ROMBASE+0x100 ## Exception vectors (other than reset vector) -default _EXCEPTION_VECTORS=_RESET+0x100 +default CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100 ## Start of coreboot in the boot rom -## = _RESET + exeception vector table size -default _ROMSTART=_RESET+0x3100 +## = CONFIG_RESET + exeception vector table size +default CONFIG_ROMSTART=CONFIG_RESET+0x3100 ## Coreboot C code runs at this location in RAM -default _RAMBASE=0x00100000 -default _RAMSTART=0x00100000 +default CONFIG_RAMBASE=0x00100000 +default CONFIG_RAMSTART=0x00100000 ### End Options.lb # diff --git a/src/mainboard/msi/ms6119/Config.lb b/src/mainboard/msi/ms6119/Config.lb index df78d8ee7a..608a458e47 100644 --- a/src/mainboard/msi/ms6119/Config.lb +++ b/src/mainboard/msi/ms6119/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/msi/ms6119/Options.lb b/src/mainboard/msi/ms6119/Options.lb index 31c70358f5..feb32318c7 100644 --- a/src/mainboard/msi/ms6119/Options.lb +++ b/src/mainboard/msi/ms6119/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/msi/ms6119/auto.c b/src/mainboard/msi/ms6119/auto.c index 8db62487d4..e5dd2055be 100644 --- a/src/mainboard/msi/ms6119/auto.c +++ b/src/mainboard/msi/ms6119/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/msi/ms6119/irq_tables.c b/src/mainboard/msi/ms6119/irq_tables.c index effdfae731..143a1104f5 100644 --- a/src/mainboard/msi/ms6119/irq_tables.c +++ b/src/mainboard/msi/ms6119/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x07 << 3) | 0x0, /* Interrupt router device */ 0x800, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/msi/ms6147/Config.lb b/src/mainboard/msi/ms6147/Config.lb index ccae4ceeac..29601be4e4 100644 --- a/src/mainboard/msi/ms6147/Config.lb +++ b/src/mainboard/msi/ms6147/Config.lb @@ -18,34 +18,34 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc @@ -53,7 +53,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -66,7 +66,7 @@ mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/msi/ms6147/Options.lb b/src/mainboard/msi/ms6147/Options.lb index 9e0f7225dd..79efc55c9f 100644 --- a/src/mainboard/msi/ms6147/Options.lb +++ b/src/mainboard/msi/ms6147/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/msi/ms6147/auto.c b/src/mainboard/msi/ms6147/auto.c index 6172743b40..a9a95a8689 100644 --- a/src/mainboard/msi/ms6147/auto.c +++ b/src/mainboard/msi/ms6147/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/msi/ms6147/irq_tables.c b/src/mainboard/msi/ms6147/irq_tables.c index fbea5319e1..b3cd1194a6 100644 --- a/src/mainboard/msi/ms6147/irq_tables.c +++ b/src/mainboard/msi/ms6147/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x07 << 3) | 0x0, /* Interrupt router device */ 0x1c00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/msi/ms6178/Config.lb b/src/mainboard/msi/ms6178/Config.lb index 801a9b24d4..391ccf0f6f 100644 --- a/src/mainboard/msi/ms6178/Config.lb +++ b/src/mainboard/msi/ms6178/Config.lb @@ -18,37 +18,37 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -58,7 +58,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/msi/ms6178/Options.lb b/src/mainboard/msi/ms6178/Options.lb index 6e2277654b..67f52f37e5 100644 --- a/src/mainboard/msi/ms6178/Options.lb +++ b/src/mainboard/msi/ms6178/Options.lb @@ -18,84 +18,84 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES -default ROM_SIZE = 512 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = ROM_IMAGE_SIZE -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 default CONFIG_CBFS = 1 -default HAVE_HIGH_TABLES = 1 +default CONFIG_HAVE_HIGH_TABLES = 1 end diff --git a/src/mainboard/msi/ms6178/auto.c b/src/mainboard/msi/ms6178/auto.c index a59074d17a..9d91b13018 100644 --- a/src/mainboard/msi/ms6178/auto.c +++ b/src/mainboard/msi/ms6178/auto.c @@ -49,7 +49,7 @@ static void main(unsigned long bist) outb(0x87, 0x2e); outb(0x87, 0x2e); pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); outb(0x87, 0xaa); uart_init(); diff --git a/src/mainboard/msi/ms6178/irq_tables.c b/src/mainboard/msi/ms6178/irq_tables.c index 97cd2a6ec0..10159b3c52 100644 --- a/src/mainboard/msi/ms6178/irq_tables.c +++ b/src/mainboard/msi/ms6178/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x1f << 3) | 0x0, /* Interrupt router device */ 0x1c00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/msi/ms7135/Config.lb b/src/mainboard/msi/ms7135/Config.lb index d316182ebd..5bd867b888 100644 --- a/src/mainboard/msi/ms7135/Config.lb +++ b/src/mainboard/msi/ms7135/Config.lb @@ -22,8 +22,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -39,23 +39,23 @@ driver mainboard.o # Needed by irq_tables and mptable and acpi_tables. object get_bus_conf.o -if HAVE_MP_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -64,13 +64,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code. ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -86,8 +86,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (this is where coreboot is entered). ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -95,7 +95,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -113,13 +113,13 @@ ldscript /southbridge/nvidia/ck804/id.lds ## ## ROMSTRAP table for CK804 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end @@ -135,12 +135,12 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/msi/ms7135/Options.lb b/src/mainboard/msi/ms7135/Options.lb index 36260c76e0..e5f8ead7e5 100644 --- a/src/mainboard/msi/ms7135/Options.lb +++ b/src/mainboard/msi/ms7135/Options.lb @@ -20,102 +20,102 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_CONSOLE_BTEXT -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_AP_CODE_IN_CAR uses CONFIG_USE_PRINTK_IN_CAR -uses MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_MEM_TRAIN_SEQ +uses CONFIG_WAIT_BEFORE_CPUS_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_LB_MEM_TOPK -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## ---> 512 Kbytes -default ROM_SIZE=(512*1024) +default CONFIG_ROM_SIZE=(512*1024) ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=(252*1024) +default CONFIG_FALLBACK_SIZE=(252*1024) #FAILOVER: 4K -default FAILOVER_SIZE=(4*1024) +default CONFIG_FAILOVER_SIZE=(4*1024) ### ### Build options @@ -124,37 +124,37 @@ default FAILOVER_SIZE=(4*1024) ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=13 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=13 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -166,19 +166,19 @@ default CONFIG_MAX_PHYSICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 ##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0 +default CONFIG_HT_CHAIN_UNITID_BASE=0 ##real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x10 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x10 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 @@ -190,22 +190,22 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -#default DCACHE_RAM_BASE=0xcf000 -#default DCACHE_RAM_SIZE=0x1000 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +#default CONFIG_DCACHE_RAM_BASE=0xcf000 +#default CONFIG_DCACHE_RAM_SIZE=0x1000 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 default CONFIG_AP_CODE_IN_CAR=0 -default MEM_TRAIN_SEQ=2 -default WAIT_BEFORE_CPUS_INIT=0 +default CONFIG_MEM_TRAIN_SEQ=2 +default CONFIG_WAIT_BEFORE_CPUS_INIT=0 ## APIC stuff -#default ENABLE_APIC_EXT_ID=0 -#default APIC_ID_OFFSET=0x10 -#default LIFT_BSP_APIC_ID=0 +#default CONFIG_ENABLE_APIC_EXT_ID=0 +#default CONFIG_APIC_ID_OFFSET=0x10 +#default CONFIG_LIFT_BSP_APIC_ID=0 #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -218,39 +218,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="K8N Neo3 (MS-7135)" -default MAINBOARD_VENDOR="MSI" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x7135 +default CONFIG_MAINBOARD_PART_NUMBER="K8N Neo3 (MS-7135)" +default CONFIG_MAINBOARD_VENDOR="MSI" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x7135 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = (64*1024) +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = (64*1024) #65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#efault USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +#efault CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -264,8 +264,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -282,21 +282,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -308,17 +308,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/msi/ms7135/cache_as_ram_auto.c b/src/mainboard/msi/ms7135/cache_as_ram_auto.c index eaeeeb16e5..b8a22a97c5 100644 --- a/src/mainboard/msi/ms7135/cache_as_ram_auto.c +++ b/src/mainboard/msi/ms7135/cache_as_ram_auto.c @@ -50,7 +50,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#if USE_FAILOVER_IMAGE == 0 +#if CONFIG_USE_FAILOVER_IMAGE == 0 /* Used by ck804_early_setup(). */ #define CK804_NUM 1 @@ -101,10 +101,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#endif /* USE_FAILOVER_IMAGE */ +#endif /* CONFIG_USE_FAILOVER_IMAGE */ -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) \ - || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) \ + || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -169,7 +169,7 @@ normal_image: fallback_image: -#if HAVE_FAILOVER_BOOT == 1 +#if CONFIG_HAVE_FAILOVER_BOOT == 1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ @@ -178,27 +178,27 @@ fallback_image: ; } -#endif /* ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) ... */ +#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) ... */ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT == 1 -#if USE_FAILOVER_IMAGE == 1 +#if CONFIG_HAVE_FAILOVER_BOOT == 1 +#if CONFIG_USE_FAILOVER_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE == 0 +#if CONFIG_USE_FAILOVER_IMAGE == 0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { @@ -218,7 +218,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -270,4 +270,4 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } -#endif /* USE_FAILOVER_IMAGE */ +#endif /* CONFIG_USE_FAILOVER_IMAGE */ diff --git a/src/mainboard/msi/ms7260/Config.lb b/src/mainboard/msi/ms7260/Config.lb index fdea44ed0a..d17e0973f2 100644 --- a/src/mainboard/msi/ms7260/Config.lb +++ b/src/mainboard/msi/ms7260/Config.lb @@ -18,50 +18,50 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end driver mainboard.o object get_bus_conf.o # Needed by irq_tables and mptable (and acpi_tables). -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end end -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -76,8 +76,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/amd/car/cache_as_ram.lds end -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -85,7 +85,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -98,13 +98,13 @@ mainboardinit southbridge/nvidia/mcp55/id.inc ldscript /southbridge/nvidia/mcp55/id.lds # ROMSTRAP table for MCP55. -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end @@ -112,12 +112,12 @@ end mainboardinit cpu/amd/car/cache_as_ram.inc -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/msi/ms7260/Options.lb b/src/mainboard/msi/ms7260/Options.lb index b16ebcaf61..9c657d4d0b 100644 --- a/src/mainboard/msi/ms7260/Options.lb +++ b/src/mainboard/msi/ms7260/Options.lb @@ -18,137 +18,137 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER # ? -uses CROSS_COMPILE +uses CONFIG_HAVE_INIT_TIMER # ? +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_USBDEBUG_DIRECT -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_SERIAL_CPU_INIT +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM uses CONFIG_LB_MEM_TOPK uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_MEM_TRAIN_SEQ +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR -default ROM_SIZE = 512 * 1024 -default FALLBACK_SIZE = (256 * 1024) - (4 * 1024) -default FAILOVER_SIZE = 4 * 1024 +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_FALLBACK_SIZE = (256 * 1024) - (4 * 1024) +default CONFIG_FAILOVER_SIZE = 4 * 1024 default CONFIG_LB_MEM_TOPK = 2048 # 1MB more for pgtbl. -default HAVE_FALLBACK_BOOT = 1 -default HAVE_FAILOVER_BOOT = 1 -default HAVE_HARD_RESET = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 11 # TODO: Check if correct. -default HAVE_MP_TABLE = 1 # TODO: Check if correct. -default HAVE_OPTION_TABLE = 1 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_FAILOVER_BOOT = 1 +default CONFIG_HAVE_HARD_RESET = 1 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 11 # TODO: Check if correct. +default CONFIG_HAVE_MP_TABLE = 1 # TODO: Check if correct. +default CONFIG_HAVE_OPTION_TABLE = 1 default CONFIG_SMP = 1 default CONFIG_MAX_CPUS = 2 default CONFIG_MAX_PHYSICAL_CPUS = 1 default CONFIG_LOGICAL_CPUS = 1 -# default SERIAL_CPU_INIT = 0 -default ENABLE_APIC_EXT_ID = 0 -default APIC_ID_OFFSET = 0x10 -default LIFT_BSP_APIC_ID = 1 +# default CONFIG_SERIAL_CPU_INIT = 0 +default CONFIG_ENABLE_APIC_EXT_ID = 0 +default CONFIG_APIC_ID_OFFSET = 0x10 +default CONFIG_LIFT_BSP_APIC_ID = 1 # Move the default coreboot CMOS range off of AMD RTC registers. -default LB_CKS_RANGE_START = 49 -default LB_CKS_RANGE_END = 122 -default LB_CKS_LOC = 123 +default CONFIG_LB_CKS_RANGE_START = 49 +default CONFIG_LB_CKS_RANGE_END = 122 +default CONFIG_LB_CKS_LOC = 123 # Memory hole size. 0 means disable, others will enable the hole. In that # case, if it is smaller than mmio_basek, it will use mmio_basek instead. -# default HW_MEM_HOLE_SIZEK = 0x200000 # 2GB -default HW_MEM_HOLE_SIZEK = 0x100000 # 1GB -# default HW_MEM_HOLE_SIZEK = 0x80000 # 512MB +# default CONFIG_HW_MEM_HOLE_SIZEK = 0x200000 # 2GB +default CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 # 1GB +# default CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 # 512MB # Make auto increase hole size to avoid hole_startk equal to basek so as # to make some kernel happy. -# default HW_MEM_HOLE_SIZE_AUTO_INC = 1 +# default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC = 1 # Opteron K8 1G HT support. -default K8_HT_FREQ_1G_SUPPORT = 1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1 # HT Unit ID offset, default is 1, the typical one, 0 means only one HT device. -default HT_CHAIN_UNITID_BASE = 0 +default CONFIG_HT_CHAIN_UNITID_BASE = 0 # Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default HT_CHAIN_END_UNITID_BASE = 0x6 +# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 # Make the SB HT chain on bus 0, default is not (0). -default SB_HT_CHAIN_ON_BUS0 = 2 +default CONFIG_SB_HT_CHAIN_ON_BUS0 = 2 # Only offset for SB chain? Default is yes (1). -default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 # Allow capable device use that above 4GB. # default CONFIG_PCI_64BIT_PREF_MEM = 1 @@ -156,35 +156,35 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 default CONFIG_CONSOLE_VGA = 1 # Needed for VGA. default CONFIG_PCI_ROM_RUN = 1 # Needed for VGA. default CONFIG_USBDEBUG_DIRECT = 0 -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xc8000 -default DCACHE_RAM_SIZE = 0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xc8000 +default CONFIG_DCACHE_RAM_SIZE = 0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 default CONFIG_USE_INIT = 0 default CONFIG_AP_CODE_IN_CAR = 0 -default MEM_TRAIN_SEQ = 2 -default WAIT_BEFORE_CPUS_INIT = 0 +default CONFIG_MEM_TRAIN_SEQ = 2 +default CONFIG_WAIT_BEFORE_CPUS_INIT = 0 default CONFIG_IOAPIC = 1 -default MAINBOARD_PART_NUMBER = "K9N Neo (MS-7260)" -default MAINBOARD_VENDOR = "MSI" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x7260 -default ROM_IMAGE_SIZE = 65536 -default STACK_SIZE = 0x2000 -default HEAP_SIZE = 0x8000 -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE) -default _RAMBASE = 0x00100000 +default CONFIG_MAINBOARD_PART_NUMBER = "K9N Neo (MS-7260)" +default CONFIG_MAINBOARD_VENDOR = "MSI" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x7260 +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_STACK_SIZE = 0x2000 +default CONFIG_HEAP_SIZE = 0x8000 +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE) +default CONFIG_RAMBASE = 0x00100000 default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_USE_PRINTK_IN_CAR = 1 default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" # # CBFS diff --git a/src/mainboard/msi/ms7260/apc_auto.c b/src/mainboard/msi/ms7260/apc_auto.c index 33217d1d8a..880952b267 100644 --- a/src/mainboard/msi/ms7260/apc_auto.c +++ b/src/mainboard/msi/ms7260/apc_auto.c @@ -61,10 +61,10 @@ void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - - DCACHE_RAM_GLOBAL_VAR_SIZE); /* in CACHE */ + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - + CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in CACHE */ struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK << 10) - - DCACHE_RAM_GLOBAL_VAR_SIZE); /* in RAM */ + CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in RAM */ struct node_core_id id; id = get_node_core_id_x(); diff --git a/src/mainboard/msi/ms7260/cache_as_ram_auto.c b/src/mainboard/msi/ms7260/cache_as_ram_auto.c index c9e429d5ca..8089b577e0 100644 --- a/src/mainboard/msi/ms7260/cache_as_ram_auto.c +++ b/src/mainboard/msi/ms7260/cache_as_ram_auto.c @@ -43,7 +43,7 @@ /* If we want to wait for core1 done before DQS training, set it to 0. */ #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -60,7 +60,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE == 0 +#if CONFIG_USE_FAILOVER_IMAGE == 0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" @@ -82,7 +82,7 @@ #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" #include "superio/winbond/w83627ehg/w83627ehg_early_init.c" -#if USE_FAILOVER_IMAGE == 0 +#if CONFIG_USE_FAILOVER_IMAGE == 0 #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -133,7 +133,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -194,7 +194,7 @@ normal_image: ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image": :"a" (bist), "b"(cpu_init_detectedx) ) @@ -207,21 +207,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT == 1 -#if USE_FAILOVER_IMAGE == 1 +#if CONFIG_HAVE_FAILOVER_BOOT == 1 +#if CONFIG_USE_FAILOVER_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE == 0 +#if CONFIG_USE_FAILOVER_IMAGE == 0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -235,7 +235,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; struct sys_info *sysinfo = - (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; @@ -246,7 +246,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_enter_ext_func_mode(SERIAL_DEV); /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */ pnp_write_config(SERIAL_DEV, 0x24, 0); - w83627ehg_enable_dev(SERIAL_DEV, TTYS0_BASE); + w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); @@ -268,7 +268,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 /* In BSP so could hold all AP until sysinfo is in RAM. */ set_sysinfo_in_ram(0); #endif diff --git a/src/mainboard/msi/ms9185/Config.lb b/src/mainboard/msi/ms9185/Config.lb index c40eb30ca3..99b86007af 100644 --- a/src/mainboard/msi/ms9185/Config.lb +++ b/src/mainboard/msi/ms9185/Config.lb @@ -22,8 +22,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -39,26 +39,26 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -68,7 +68,7 @@ end ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -85,7 +85,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -109,7 +109,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end @@ -207,10 +207,10 @@ chip northbridge/amd/amdk8/root_complex device pci 2.0 on end # USB 0x0223 device pci 2.1 on end # USB device pci 2.2 on end # USB - #when HT_CHAIN_END_UNITID_BASE (0,1) < HT_CHAIN_UNITID_BASE (6,,,,), + #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), chip drivers/pci/onboard device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address - # if HT_CHAIN_END_UNITID_BASE=0, it is 4, if HT_CHAIN_END_UNITID_BASE=1, it is 3 + # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3 register "rom_address" = "0xfff80000" end #bx_a013+ start @@ -223,7 +223,7 @@ chip northbridge/amd/amdk8/root_complex #bx_a013+ end end - #when HT_CHAIN_END_UNITID_BASE > HT_CHAIN_UNITID_BASE (6, ,,,,) + #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) # chip drivers/pci/onboard # device pci 0.0 on end # fake, will be disabled # end diff --git a/src/mainboard/msi/ms9185/Options.lb b/src/mainboard/msi/ms9185/Options.lb index 5c3073e2d2..f6567040d8 100644 --- a/src/mainboard/msi/ms9185/Options.lb +++ b/src/mainboard/msi/ms9185/Options.lb @@ -22,85 +22,85 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -112,16 +112,16 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -129,41 +129,41 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -#default HAVE_ACPI_TABLES=1 +#default CONFIG_HAVE_ACPI_TABLES=1 ## extra SSDT num -#default ACPI_SSDTX_NUM=1 +#default CONFIG_ACPI_SSDTX_NUM=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -174,41 +174,41 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -default SERIAL_CPU_INIT=0 +default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x8 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x8 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 #HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0x06 +default CONFIG_HT_CHAIN_UNITID_BASE=0x06 #real SB Unit ID, default is 0x20, mean dont touch it at last -default HT_CHAIN_END_UNITID_BASE=0x01 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x01 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -216,10 +216,10 @@ default SB_HT_CHAIN_ON_BUS0=2 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcc000 -default DCACHE_RAM_SIZE=0x04000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcc000 +default CONFIG_DCACHE_RAM_SIZE=0x04000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 ## @@ -230,37 +230,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="MS9185" -default MAINBOARD_VENDOR="MSI" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 +default CONFIG_MAINBOARD_PART_NUMBER="MS9185" +default CONFIG_MAINBOARD_VENDOR="MSI" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -274,8 +274,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -291,21 +291,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -317,17 +317,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/msi/ms9185/cache_as_ram_auto.c b/src/mainboard/msi/ms9185/cache_as_ram_auto.c index cd7a3d236d..aaedd6394b 100644 --- a/src/mainboard/msi/ms9185/cache_as_ram_auto.c +++ b/src/mainboard/msi/ms9185/cache_as_ram_auto.c @@ -157,7 +157,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/fidvid.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "northbridge/amd/amdk8/early_ht.c" @@ -215,7 +215,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -236,7 +236,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; unsigned bsp_apicid = 0; @@ -247,11 +247,11 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - pc87417_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); -// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); +// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/msi/ms9185/get_bus_conf.c b/src/mainboard/msi/ms9185/get_bus_conf.c index 43cc42fe99..e02de0dc9a 100644 --- a/src/mainboard/msi/ms9185/get_bus_conf.c +++ b/src/mainboard/msi/ms9185/get_bus_conf.c @@ -105,7 +105,7 @@ void get_bus_conf(void) dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd,0)); if(dev) { m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); m->bus_isa++; printk_debug("bus_isa=%d\n",m->bus_isa); @@ -121,7 +121,7 @@ void get_bus_conf(void) dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0)); if(dev) { m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); m->bus_isa++; printk_debug("bus_isa=%d\n",m->bus_isa); diff --git a/src/mainboard/msi/ms9282/Config.lb b/src/mainboard/msi/ms9282/Config.lb index 54727bf6ce..056f7ad16c 100644 --- a/src/mainboard/msi/ms9282/Config.lb +++ b/src/mainboard/msi/ms9282/Config.lb @@ -22,8 +22,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1 @@ -41,22 +41,22 @@ driver mainboard.o object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -66,7 +66,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -84,7 +84,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -101,7 +101,7 @@ ldscript /southbridge/nvidia/mcp55/id.lds ## ## ROMSTRAP table for MCP55 ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end @@ -116,7 +116,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/msi/ms9282/Options.lb b/src/mainboard/msi/ms9282/Options.lb index 1a686826cd..bbcd92e9ca 100644 --- a/src/mainboard/msi/ms9282/Options.lb +++ b/src/mainboard/msi/ms9282/Options.lb @@ -22,79 +22,79 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN #bx_b001- uses K8_HW_MEM_HOLE_SIZEK -uses K8_HT_FREQ_1G_SUPPORT +uses CONFIG_K8_HT_FREQ_1G_SUPPORT -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE #bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY #bx_b005+ -uses SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_ON_BUS0 # stepan 2007-04-12 uses CONFIG_COMPRESSED_PAYLOAD_LZMA @@ -102,19 +102,19 @@ uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_PRECOMPRESSED_PAYLOAD uses CONFIG_USE_PRINTK_IN_CAR -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. #512K bytes -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 #1M bytes -#bx- default ROM_SIZE=1048576 +#bx- default CONFIG_ROM_SIZE=1048576 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ### ### Build options @@ -123,36 +123,36 @@ default FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -167,22 +167,22 @@ default CONFIG_LOGICAL_CPUS=1 #bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 ##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0x0 +default CONFIG_HT_CHAIN_UNITID_BASE=0x0 ##real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x0 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0 #make the SB HT chain on bus 0, default is not (0) #bx_b001- default K8_SB_HT_CHAIN_ON_BUS0=2 ##bx_b005+ make the SB HT chain on bus 0 -default SB_HT_CHAIN_ON_BUS0=1 +default CONFIG_SB_HT_CHAIN_ON_BUS0=1 ##only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #VGA default CONFIG_CONSOLE_VGA=1 @@ -191,15 +191,15 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcc000 -default DCACHE_RAM_SIZE=0x4000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcc000 +default CONFIG_DCACHE_RAM_SIZE=0x4000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 -default ENABLE_APIC_EXT_ID=1 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=0 +default CONFIG_ENABLE_APIC_EXT_ID=1 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=0 ## ## Build code to setup a generic IOAPIC @@ -209,37 +209,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="ms9282" -default MAINBOARD_VENDOR="MSI" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282 +default CONFIG_MAINBOARD_PART_NUMBER="ms9282" +default CONFIG_MAINBOARD_VENDOR="MSI" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -253,8 +253,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -270,21 +270,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -296,17 +296,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/msi/ms9282/cache_as_ram_auto.c b/src/mainboard/msi/ms9282/cache_as_ram_auto.c index 6e8760d4bc..7fb3aba1c7 100644 --- a/src/mainboard/msi/ms9282/cache_as_ram_auto.c +++ b/src/mainboard/msi/ms9282/cache_as_ram_auto.c @@ -135,7 +135,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -208,7 +208,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -232,7 +232,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) unsigned bsp_apicid = 0; int needs_reset; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); char *p ; if (bist == 0) { @@ -240,7 +240,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } - w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/nec/powermate2000/Config.lb b/src/mainboard/nec/powermate2000/Config.lb index 55d0677c7d..118d61554c 100644 --- a/src/mainboard/nec/powermate2000/Config.lb +++ b/src/mainboard/nec/powermate2000/Config.lb @@ -18,37 +18,37 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -58,7 +58,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/nec/powermate2000/Options.lb b/src/mainboard/nec/powermate2000/Options.lb index 3985c3c067..eae7cb6444 100644 --- a/src/mainboard/nec/powermate2000/Options.lb +++ b/src/mainboard/nec/powermate2000/Options.lb @@ -18,79 +18,79 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 512 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default CONFIG_CONSOLE_VGA = 1 diff --git a/src/mainboard/nec/powermate2000/auto.c b/src/mainboard/nec/powermate2000/auto.c index 7ce77442ff..507bbbc746 100644 --- a/src/mainboard/nec/powermate2000/auto.c +++ b/src/mainboard/nec/powermate2000/auto.c @@ -45,7 +45,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE); + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/nec/powermate2000/irq_tables.c b/src/mainboard/nec/powermate2000/irq_tables.c index bc3113f5f9..b24042df63 100644 --- a/src/mainboard/nec/powermate2000/irq_tables.c +++ b/src/mainboard/nec/powermate2000/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x1f << 3) | 0x0, /* Interrupt router device */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/newisys/khepri/Config.lb b/src/mainboard/newisys/khepri/Config.lb index f5fb2f73a0..f24c351130 100644 --- a/src/mainboard/newisys/khepri/Config.lb +++ b/src/mainboard/newisys/khepri/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -13,22 +13,22 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -38,7 +38,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -56,7 +56,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -80,7 +80,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/newisys/khepri/Options.lb b/src/mainboard/newisys/khepri/Options.lb index 041762eb5f..2766076ea9 100644 --- a/src/mainboard/newisys/khepri/Options.lb +++ b/src/mainboard/newisys/khepri/Options.lb @@ -1,63 +1,63 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -66,50 +66,50 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=15 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=15 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -121,7 +121,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -131,9 +131,9 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## @@ -144,37 +144,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="Khepri" -default MAINBOARD_VENDOR="Newisys" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17c2 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0010 +default CONFIG_MAINBOARD_PART_NUMBER="Khepri" +default CONFIG_MAINBOARD_VENDOR="Newisys" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17c2 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0010 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -188,8 +188,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -206,21 +206,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -232,17 +232,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/newisys/khepri/cache_as_ram_auto.c b/src/mainboard/newisys/khepri/cache_as_ram_auto.c index 6adb906e33..2affa7fbb5 100644 --- a/src/mainboard/newisys/khepri/cache_as_ram_auto.c +++ b/src/mainboard/newisys/khepri/cache_as_ram_auto.c @@ -108,7 +108,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -164,7 +164,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -194,11 +194,11 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); -// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); +// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/nvidia/l1_2pvv/Config.lb b/src/mainboard/nvidia/l1_2pvv/Config.lb index 29725cf8a1..978e88f795 100644 --- a/src/mainboard/nvidia/l1_2pvv/Config.lb +++ b/src/mainboard/nvidia/l1_2pvv/Config.lb @@ -19,8 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -33,33 +33,33 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o object fadt.o makerule dsdt.c - depends "$(MAINBOARD)/dx/dsdt_lb.dsl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl" + depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" + action "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" action "mv dsdt_lb.hex dsdt.c" end object ./dsdt.o #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb - if ACPI_SSDTX_NUM + if CONFIG_ACPI_SSDTX_NUM makerule ssdt6.c - depends "$(MAINBOARD)/dx/pci6.asl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci6.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci6.asl" + action "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/pci6.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt6/g' pci6.hex" action "mv pci6.hex ssdt6.c" end object ./ssdt6.o makerule ssdt5.c - depends "$(MAINBOARD)/dx/pci5.asl" - action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci5.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci5.asl" + action "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/pci5.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex" action "mv pci5.hex ssdt5.c" end @@ -69,24 +69,24 @@ end if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -96,13 +96,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -121,8 +121,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -130,7 +130,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -148,13 +148,13 @@ ldscript /southbridge/nvidia/mcp55/id.lds ## ## ROMSTRAP table for MCP55 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end @@ -170,12 +170,12 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/nvidia/l1_2pvv/Options.lb b/src/mainboard/nvidia/l1_2pvv/Options.lb index 2f455f4265..4f032fb7cf 100644 --- a/src/mainboard/nvidia/l1_2pvv/Options.lb +++ b/src/mainboard/nvidia/l1_2pvv/Options.lb @@ -19,90 +19,90 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_USBDEBUG_DIRECT uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -110,9 +110,9 @@ uses CONFIG_LB_MEM_TOPK uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -121,21 +121,21 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 -#default ROM_SIZE=0x100000 +default CONFIG_ROM_SIZE=524288 +#default CONFIG_ROM_SIZE=0x100000 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE=0x3f000 #FAILOVER: 4K -default FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -143,40 +143,40 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=0 +default CONFIG_HAVE_ACPI_TABLES=0 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -187,25 +187,25 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -#default SERIAL_CPU_INIT=0 +#default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -214,16 +214,16 @@ default CONFIG_PCI_ROM_RUN=1 #default CONFIG_USBDEBUG_DIRECT=1 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default HT_CHAIN_UNITID_BASE=0 +default CONFIG_HT_CHAIN_UNITID_BASE=0 #real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x6 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -231,15 +231,15 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 default CONFIG_AP_CODE_IN_CAR=0 -default MEM_TRAIN_SEQ=1 -default WAIT_BEFORE_CPUS_INIT=1 +default CONFIG_MEM_TRAIN_SEQ=1 +default CONFIG_WAIT_BEFORE_CPUS_INIT=1 ## ## Build code to setup a generic IOAPIC @@ -249,37 +249,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="l1_2pvv" -default MAINBOARD_VENDOR="NVIDIA" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 +default CONFIG_MAINBOARD_PART_NUMBER="l1_2pvv" +default CONFIG_MAINBOARD_VENDOR="NVIDIA" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -295,8 +295,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -312,21 +312,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -338,17 +338,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/nvidia/l1_2pvv/apc_auto.c b/src/mainboard/nvidia/l1_2pvv/apc_auto.c index 91c3b5e187..525e940776 100644 --- a/src/mainboard/nvidia/l1_2pvv/apc_auto.c +++ b/src/mainboard/nvidia/l1_2pvv/apc_auto.c @@ -86,8 +86,8 @@ static void post_code(uint8_t value) { void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c b/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c index d2a357da3c..a6a586a1b3 100644 --- a/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c +++ b/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c @@ -39,7 +39,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -56,7 +56,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT @@ -79,7 +79,7 @@ #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" #include "superio/winbond/w83627ehg/w83627ehg_early_init.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" @@ -152,7 +152,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -220,7 +220,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -233,21 +233,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -260,7 +260,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; @@ -271,7 +271,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_enter_ext_func_mode(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x24, 0); - w83627ehg_enable_dev(SERIAL_DEV, TTYS0_BASE); + w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); @@ -291,7 +291,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/olpc/btest/Config.lb b/src/mainboard/olpc/btest/Config.lb index 2f054e3578..c35fb90a69 100644 --- a/src/mainboard/olpc/btest/Config.lb +++ b/src/mainboard/olpc/btest/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,29 +14,29 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -50,7 +50,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -72,7 +72,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/olpc/btest/Options.lb b/src/mainboard/olpc/btest/Options.lb index 70ee04683c..10e30df264 100644 --- a/src/mainboard/olpc/btest/Options.lb +++ b/src/mainboard/olpc/btest/Options.lb @@ -1,51 +1,51 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -54,17 +54,17 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -74,49 +74,49 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=2 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=2 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -126,21 +126,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -152,13 +152,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/olpc/rev_a/Config.lb b/src/mainboard/olpc/rev_a/Config.lb index 2f054e3578..c35fb90a69 100644 --- a/src/mainboard/olpc/rev_a/Config.lb +++ b/src/mainboard/olpc/rev_a/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -14,29 +14,29 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -50,7 +50,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -72,7 +72,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/olpc/rev_a/Options.lb b/src/mainboard/olpc/rev_a/Options.lb index 70ee04683c..10e30df264 100644 --- a/src/mainboard/olpc/rev_a/Options.lb +++ b/src/mainboard/olpc/rev_a/Options.lb @@ -1,51 +1,51 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -54,17 +54,17 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -74,49 +74,49 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=2 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=2 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -126,21 +126,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -152,13 +152,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/pcengines/alix1c/Config.lb b/src/mainboard/pcengines/alix1c/Config.lb index 54021bbccb..0580d746d9 100644 --- a/src/mainboard/pcengines/alix1c/Config.lb +++ b/src/mainboard/pcengines/alix1c/Config.lb @@ -18,8 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -34,14 +34,14 @@ arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -57,7 +57,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -79,7 +79,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds # mainboardinit ./failover.inc end diff --git a/src/mainboard/pcengines/alix1c/Options.lb b/src/mainboard/pcengines/alix1c/Options.lb index ea9f3b3a94..2696ab9b1d 100644 --- a/src/mainboard/pcengines/alix1c/Options.lb +++ b/src/mainboard/pcengines/alix1c/Options.lb @@ -18,62 +18,62 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_VIDEO_MB -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 512*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 512*1024 ### ### Build options @@ -85,17 +85,17 @@ default CONFIG_PCI_ROM_RUN=0 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## Delay timer options ## @@ -105,56 +105,56 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=5 -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=5 +default CONFIG_PIRQ_ROUTE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 default CONFIG_USE_PRINTK_IN_CAR=1 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## The Serial Console @@ -164,21 +164,21 @@ default HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -190,13 +190,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # diff --git a/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c b/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c index e7a680cd4d..472ea10c94 100644 --- a/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c +++ b/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c @@ -161,7 +161,7 @@ void cache_as_ram_main(void) * It is counting on some early MSR setup for the CS5536. */ cs5536_disable_internal_uart(); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); uart_init(); console_init(); diff --git a/src/mainboard/pcengines/alix1c/irq_tables.c b/src/mainboard/pcengines/alix1c/irq_tables.c index a7fd6deea7..be03bba2ee 100644 --- a/src/mainboard/pcengines/alix1c/irq_tables.c +++ b/src/mainboard/pcengines/alix1c/irq_tables.c @@ -73,7 +73,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -83,7 +83,7 @@ const struct irq_routing_table intel_irq_routing_table = { {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0x00, /* Checksum */ { - /* If you change the number of entries, change IRQ_SLOT_COUNT above! */ + /* If you change the number of entries, change CONFIG_IRQ_SLOT_COUNT above! */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ diff --git a/src/mainboard/rca/rm4100/Config.lb b/src/mainboard/rca/rm4100/Config.lb index e3defa9a22..ce254cd252 100644 --- a/src/mainboard/rca/rm4100/Config.lb +++ b/src/mainboard/rca/rm4100/Config.lb @@ -18,42 +18,42 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object fadt.o object dsdt.o object acpi_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -63,7 +63,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/rca/rm4100/Options.lb b/src/mainboard/rca/rm4100/Options.lb index 671114b71a..1e3835341b 100644 --- a/src/mainboard/rca/rm4100/Options.lb +++ b/src/mainboard/rca/rm4100/Options.lb @@ -31,71 +31,71 @@ uses CONFIG_ROM_PAYLOAD_START uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_UDELAY_TSC uses CONFIG_VIDEO_MB -uses CROSS_COMPILE -uses DEFAULT_CONSOLE_LOGLEVEL -uses FALLBACK_SIZE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses HAVE_FALLBACK_BOOT -uses HAVE_MP_TABLE -uses HAVE_OPTION_TABLE -uses HAVE_PIRQ_TABLE -uses HEAP_SIZE -uses HOSTCC -uses IRQ_SLOT_COUNT +uses CONFIG_CROSS_COMPILE +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_FALLBACK_SIZE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HEAP_SIZE +uses CONFIG_HOSTCC +uses CONFIG_IRQ_SLOT_COUNT uses COREBOOT_EXTRA_VERSION -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER -uses MAXIMUM_CONSOLE_LOGLEVEL -uses OBJCOPY -uses PAYLOAD_SIZE -uses _RAMBASE -uses _ROMBASE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET -uses ROM_SIZE -uses STACK_SIZE -uses TTYS0_BASE -uses TTYS0_BAUD -uses TTYS0_LCS -uses USE_FALLBACK_IMAGE -uses USE_OPTION_TABLE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_OBJCOPY +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_RAMBASE +uses CONFIG_ROMBASE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET +uses CONFIG_ROM_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_LCS +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE -default ROM_SIZE = 512 * 1024 -default ROM_IMAGE_SIZE = 128 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default FALLBACK_SIZE = 512 * 1024 +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_FALLBACK_SIZE = 512 * 1024 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 7 -default HAVE_MP_TABLE = 0 -default HAVE_ACPI_TABLES = 0 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 7 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_ACPI_TABLES = 0 default CONFIG_IOAPIC = 0 -default HAVE_OPTION_TABLE = 0 +default CONFIG_HAVE_OPTION_TABLE = 0 default CONFIG_CONSOLE_VGA = 0 default CONFIG_PCI_ROM_RUN = 0 default CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0 default CONFIG_VIDEO_MB = 0 -default STACK_SIZE = 0x2000 -default HEAP_SIZE = 0x4000 -default _RAMBASE = 0x00004000 -default USE_OPTION_TABLE = 0 +default CONFIG_STACK_SIZE = 0x2000 +default CONFIG_HEAP_SIZE = 0x4000 +default CONFIG_RAMBASE = 0x00004000 +default CONFIG_USE_OPTION_TABLE = 0 default CONFIG_ROM_PAYLOAD = 1 -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 -default MAINBOARD_VENDOR = "RCA" -default MAINBOARD_PART_NUMBER = "RM4100" +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAINBOARD_VENDOR = "RCA" +default CONFIG_MAINBOARD_PART_NUMBER = "RM4100" # # CBFS # diff --git a/src/mainboard/rca/rm4100/auto.c b/src/mainboard/rca/rm4100/auto.c index b77c05d4da..147c49fe3d 100644 --- a/src/mainboard/rca/rm4100/auto.c +++ b/src/mainboard/rca/rm4100/auto.c @@ -101,7 +101,7 @@ static void main(unsigned long bist) hard_reset(); } - smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE); + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); uart_init(); console_init(); diff --git a/src/mainboard/rca/rm4100/irq_tables.c b/src/mainboard/rca/rm4100/irq_tables.c index daec6f0274..0ec955126e 100644 --- a/src/mainboard/rca/rm4100/irq_tables.c +++ b/src/mainboard/rca/rm4100/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* there can be total 7 devices on the bus */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total 7 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb b/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb index e98657f397..e9e0af931e 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb +++ b/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb b/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb index 4813e8fdd4..9166a9042a 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb +++ b/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb @@ -18,82 +18,82 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 default CONFIG_CBFS = 0 diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/auto.c b/src/mainboard/soyo/sy-6ba-plus-iii/auto.c index c324dc1abf..36e8cd439d 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/auto.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - it8671f_enable_serial(SERIAL_DEV, TTYS0_BASE); + it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/irq_tables.c b/src/mainboard/soyo/sy-6ba-plus-iii/irq_tables.c index 751c9ee135..22f29e11c3 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/irq_tables.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x07 << 3) | 0x0, /* Interrupt router dev */ 0xc00, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/sunw/ultra40/Config.lb b/src/mainboard/sunw/ultra40/Config.lb index 78235b7e4a..450b293a1c 100644 --- a/src/mainboard/sunw/ultra40/Config.lb +++ b/src/mainboard/sunw/ultra40/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1 @@ -14,18 +14,18 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -34,7 +34,7 @@ if HAVE_PIRQ_TABLE object irq_tables.o end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -52,7 +52,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -69,7 +69,7 @@ ldscript /southbridge/nvidia/ck804/id.lds ## ## ROMSTRAP table for CK804 ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end @@ -84,7 +84,7 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/sunw/ultra40/Options.lb b/src/mainboard/sunw/ultra40/Options.lb index 4a7e48cdbf..104ff14710 100644 --- a/src/mainboard/sunw/ultra40/Options.lb +++ b/src/mainboard/sunw/ultra40/Options.lb @@ -1,90 +1,90 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses K8_HT_FREQ_1G_SUPPORT +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_K8_HT_FREQ_1G_SUPPORT -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. #512K bytes -#default ROM_SIZE=524288 +#default CONFIG_ROM_SIZE=524288 #1M bytes -default ROM_SIZE=1048576 +default CONFIG_ROM_SIZE=1048576 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ### ### Build options @@ -93,36 +93,36 @@ default FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -134,22 +134,22 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 ##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0x0 +default CONFIG_HT_CHAIN_UNITID_BASE=0x0 ##real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x0 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #VGA default CONFIG_CONSOLE_VGA=1 @@ -158,14 +158,14 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 -default ENABLE_APIC_EXT_ID=1 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=0 +default CONFIG_ENABLE_APIC_EXT_ID=1 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=0 ## @@ -176,38 +176,38 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="ultra40" -default MAINBOARD_VENDOR="sunw" +default CONFIG_MAINBOARD_PART_NUMBER="ultra40" +default CONFIG_MAINBOARD_VENDOR="sunw" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x108e -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x40 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x108e +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x40 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -221,8 +221,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -239,21 +239,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -265,17 +265,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/sunw/ultra40/cache_as_ram_auto.c b/src/mainboard/sunw/ultra40/cache_as_ram_auto.c index bac138cf1f..1514fdaf3f 100644 --- a/src/mainboard/sunw/ultra40/cache_as_ram_auto.c +++ b/src/mainboard/sunw/ultra40/cache_as_ram_auto.c @@ -114,7 +114,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -198,7 +198,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -226,7 +226,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx); } - lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE); + lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/h8dme/Config.lb b/src/mainboard/supermicro/h8dme/Config.lb index c3ad78a215..9c07ae9b6f 100644 --- a/src/mainboard/supermicro/h8dme/Config.lb +++ b/src/mainboard/supermicro/h8dme/Config.lb @@ -16,8 +16,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -30,30 +30,30 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -63,13 +63,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -88,8 +88,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -97,7 +97,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -115,13 +115,13 @@ ldscript /southbridge/nvidia/mcp55/id.lds ## ## ROMSTRAP table for MCP55 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end @@ -137,12 +137,12 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/supermicro/h8dme/Options.lb b/src/mainboard/supermicro/h8dme/Options.lb index 643cab37cb..d10e4b3304 100644 --- a/src/mainboard/supermicro/h8dme/Options.lb +++ b/src/mainboard/supermicro/h8dme/Options.lb @@ -19,91 +19,91 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses HAVE_LOW_TABLES +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_HAVE_LOW_TABLES uses CONFIG_MULTIBOOT -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -111,9 +111,9 @@ uses CONFIG_LB_MEM_TOPK uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -122,24 +122,24 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -#default ROM_SIZE=524288 -default ROM_SIZE=0x100000 +#default CONFIG_ROM_SIZE=524288 +default CONFIG_ROM_SIZE=0x100000 -default HAVE_LOW_TABLES = 0 +default CONFIG_HAVE_LOW_TABLES = 0 default CONFIG_MULTIBOOT=0 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE=0x3f000 #FAILOVER: 4K -default FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -147,40 +147,40 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=0 +default CONFIG_HAVE_ACPI_TABLES=0 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -191,41 +191,41 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -default SERIAL_CPU_INIT=0 +default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default HT_CHAIN_UNITID_BASE=0 +default CONFIG_HT_CHAIN_UNITID_BASE=0 #real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x6 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -233,15 +233,15 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 default CONFIG_AP_CODE_IN_CAR=1 -default MEM_TRAIN_SEQ=1 -default WAIT_BEFORE_CPUS_INIT=1 +default CONFIG_MEM_TRAIN_SEQ=1 +default CONFIG_WAIT_BEFORE_CPUS_INIT=1 ## ## Build code to setup a generic IOAPIC @@ -251,37 +251,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="h8dme" -default MAINBOARD_VENDOR="Supermicro" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511 +default CONFIG_MAINBOARD_PART_NUMBER="h8dme" +default CONFIG_MAINBOARD_VENDOR="Supermicro" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -297,8 +297,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -314,21 +314,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -340,17 +340,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=9 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/supermicro/h8dme/apc_auto.c b/src/mainboard/supermicro/h8dme/apc_auto.c index 099b6abd17..442945e9f2 100644 --- a/src/mainboard/supermicro/h8dme/apc_auto.c +++ b/src/mainboard/supermicro/h8dme/apc_auto.c @@ -94,8 +94,8 @@ static inline unsigned get_nodes(void) void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c b/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c index a71de8428c..606556ba73 100644 --- a/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c +++ b/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c @@ -35,7 +35,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -53,7 +53,7 @@ // for enable the FAN #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -72,7 +72,7 @@ #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" @@ -194,7 +194,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -263,7 +263,7 @@ normal_image: ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image": /* outputs */ :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ ) @@ -275,14 +275,14 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 -#if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 +#if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -293,7 +293,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #define RC0 (2<<8) #define RC1 (1<<8) -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -315,7 +315,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; struct sys_info *sysinfo = - (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; @@ -326,7 +326,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_enter_ext_func_mode(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); uart_init(); @@ -347,7 +347,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif /* dump_smbus_registers(); */ diff --git a/src/mainboard/supermicro/h8dmr/Config.lb b/src/mainboard/supermicro/h8dmr/Config.lb index 94d91d8810..b8c78b1c9d 100644 --- a/src/mainboard/supermicro/h8dmr/Config.lb +++ b/src/mainboard/supermicro/h8dmr/Config.lb @@ -19,8 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -33,30 +33,30 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -66,13 +66,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -91,8 +91,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -100,7 +100,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -118,13 +118,13 @@ ldscript /southbridge/nvidia/mcp55/id.lds ## ## ROMSTRAP table for MCP55 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end @@ -140,12 +140,12 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/supermicro/h8dmr/Options.lb b/src/mainboard/supermicro/h8dmr/Options.lb index e65dfca0ed..16c798c2f8 100644 --- a/src/mainboard/supermicro/h8dmr/Options.lb +++ b/src/mainboard/supermicro/h8dmr/Options.lb @@ -19,89 +19,89 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -109,9 +109,9 @@ uses CONFIG_LB_MEM_TOPK uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -120,21 +120,21 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -#default ROM_SIZE=524288 -default ROM_SIZE=0x100000 +#default CONFIG_ROM_SIZE=524288 +default CONFIG_ROM_SIZE=0x100000 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE=0x3f000 #FAILOVER: 4K -default FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -142,40 +142,40 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=0 +default CONFIG_HAVE_ACPI_TABLES=0 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -186,41 +186,41 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -default SERIAL_CPU_INIT=0 +default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default HT_CHAIN_UNITID_BASE=0 +default CONFIG_HT_CHAIN_UNITID_BASE=0 #real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x6 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -228,15 +228,15 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 default CONFIG_AP_CODE_IN_CAR=1 -default MEM_TRAIN_SEQ=1 -default WAIT_BEFORE_CPUS_INIT=1 +default CONFIG_MEM_TRAIN_SEQ=1 +default CONFIG_WAIT_BEFORE_CPUS_INIT=1 ## ## Build code to setup a generic IOAPIC @@ -246,37 +246,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="h8dmr" -default MAINBOARD_VENDOR="Supermicro" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511 +default CONFIG_MAINBOARD_PART_NUMBER="h8dmr" +default CONFIG_MAINBOARD_VENDOR="Supermicro" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -292,8 +292,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -309,21 +309,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -335,17 +335,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/supermicro/h8dmr/apc_auto.c b/src/mainboard/supermicro/h8dmr/apc_auto.c index 099b6abd17..442945e9f2 100644 --- a/src/mainboard/supermicro/h8dmr/apc_auto.c +++ b/src/mainboard/supermicro/h8dmr/apc_auto.c @@ -94,8 +94,8 @@ static inline unsigned get_nodes(void) void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c b/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c index c9b33877b8..34a3bb56eb 100644 --- a/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c +++ b/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c @@ -39,7 +39,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -57,7 +57,7 @@ // for enable the FAN #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -76,7 +76,7 @@ #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" @@ -141,7 +141,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -212,7 +212,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -225,21 +225,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -252,7 +252,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; @@ -263,7 +263,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_enter_ext_func_mode(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); uart_init(); @@ -278,7 +278,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/supermicro/x6dai_g/Config.lb b/src/mainboard/supermicro/x6dai_g/Config.lb index 2a144eb96a..8acd71c724 100644 --- a/src/mainboard/supermicro/x6dai_g/Config.lb +++ b/src/mainboard/supermicro/x6dai_g/Config.lb @@ -1,10 +1,10 @@ ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## @@ -18,30 +18,30 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/supermicro/x6dai_g/Options.lb b/src/mainboard/supermicro/x6dai_g/Options.lb index 576cdb8c3e..68562efad4 100644 --- a/src/mainboard/supermicro/x6dai_g/Options.lb +++ b/src/mainboard/supermicro/x6dai_g/Options.lb @@ -1,57 +1,57 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_BTEXT uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY ### @@ -59,14 +59,14 @@ uses OBJCOPY ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1048576 +default CONFIG_ROM_SIZE=1048576 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -78,31 +78,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=16 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=16 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -120,39 +120,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="X6DAI" -default MAINBOARD_VENDOR= "Supermicro" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6780 +default CONFIG_MAINBOARD_PART_NUMBER="X6DAI" +default CONFIG_MAINBOARD_VENDOR= "Supermicro" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6780 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -167,8 +167,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -183,21 +183,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -209,17 +209,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ## ## Don't enable the btext console diff --git a/src/mainboard/supermicro/x6dai_g/auto.c b/src/mainboard/supermicro/x6dai_g/auto.c index 078296df42..701fcd6484 100644 --- a/src/mainboard/supermicro/x6dai_g/auto.c +++ b/src/mainboard/supermicro/x6dai_g/auto.c @@ -84,7 +84,7 @@ static void main(unsigned long bist) outb(0x87,0x2e); outb(0x87,0x2e); pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/x6dhe_g/Config.lb b/src/mainboard/supermicro/x6dhe_g/Config.lb index d972ff1ed2..78be06df0b 100644 --- a/src/mainboard/supermicro/x6dhe_g/Config.lb +++ b/src/mainboard/supermicro/x6dhe_g/Config.lb @@ -1,10 +1,10 @@ ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## Set all of the defaults for an x86 architecture @@ -17,31 +17,31 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/supermicro/x6dhe_g/Options.lb b/src/mainboard/supermicro/x6dhe_g/Options.lb index bd31e7c14c..47eac1d624 100644 --- a/src/mainboard/supermicro/x6dhe_g/Options.lb +++ b/src/mainboard/supermicro/x6dhe_g/Options.lb @@ -1,57 +1,57 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_BTEXT uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY ### @@ -59,14 +59,14 @@ uses OBJCOPY ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1048576 +default CONFIG_ROM_SIZE=1048576 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -78,31 +78,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=16 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=16 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -120,39 +120,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="X6DHE_g" -default MAINBOARD_VENDOR= "Supermicro" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080 +default CONFIG_MAINBOARD_PART_NUMBER="X6DHE_g" +default CONFIG_MAINBOARD_VENDOR= "Supermicro" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -167,8 +167,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -183,21 +183,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -209,17 +209,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ## ## Don't enable the btext console diff --git a/src/mainboard/supermicro/x6dhe_g/auto.c b/src/mainboard/supermicro/x6dhe_g/auto.c index da340b73eb..ef99677af7 100644 --- a/src/mainboard/supermicro/x6dhe_g/auto.c +++ b/src/mainboard/supermicro/x6dhe_g/auto.c @@ -102,7 +102,7 @@ static void main(unsigned long bist) outb(0x87,0x2e); outb(0x87,0x2e); pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c index 6a284981b0..ea8f3590a5 100644 --- a/src/mainboard/supermicro/x6dhe_g/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g/mptable.c @@ -109,7 +109,7 @@ void *smp_write_config_table(void *v) } else { printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n"); - printk_debug("DEBUG: Dev= %p\n", dev); + printk_debug("CONFIG_DEBUG: Dev= %p\n", dev); } /* PXHd apic 5 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,3)); @@ -121,7 +121,7 @@ void *smp_write_config_table(void *v) } else { printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n"); - printk_debug("DEBUG: Dev= %p\n", dev); + printk_debug("CONFIG_DEBUG: Dev= %p\n", dev); } } diff --git a/src/mainboard/supermicro/x6dhe_g2/Config.lb b/src/mainboard/supermicro/x6dhe_g2/Config.lb index 7a5fcdf933..a4950d33ef 100644 --- a/src/mainboard/supermicro/x6dhe_g2/Config.lb +++ b/src/mainboard/supermicro/x6dhe_g2/Config.lb @@ -1,10 +1,10 @@ ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## Set all of the defaults for an x86 architecture @@ -17,31 +17,31 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/supermicro/x6dhe_g2/Options.lb b/src/mainboard/supermicro/x6dhe_g2/Options.lb index bd31e7c14c..47eac1d624 100644 --- a/src/mainboard/supermicro/x6dhe_g2/Options.lb +++ b/src/mainboard/supermicro/x6dhe_g2/Options.lb @@ -1,57 +1,57 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_BTEXT uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY ### @@ -59,14 +59,14 @@ uses OBJCOPY ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1048576 +default CONFIG_ROM_SIZE=1048576 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -78,31 +78,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=16 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=16 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -120,39 +120,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="X6DHE_g" -default MAINBOARD_VENDOR= "Supermicro" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080 +default CONFIG_MAINBOARD_PART_NUMBER="X6DHE_g" +default CONFIG_MAINBOARD_VENDOR= "Supermicro" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -167,8 +167,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -183,21 +183,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -209,17 +209,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ## ## Don't enable the btext console diff --git a/src/mainboard/supermicro/x6dhe_g2/auto.c b/src/mainboard/supermicro/x6dhe_g2/auto.c index 0622ab7ade..4a3029f9aa 100644 --- a/src/mainboard/supermicro/x6dhe_g2/auto.c +++ b/src/mainboard/supermicro/x6dhe_g2/auto.c @@ -103,7 +103,7 @@ static void main(unsigned long bist) outb(0x87,0x2e); outb(0x87,0x2e); pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - pc87427_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/x6dhe_g2/auto.updated.c b/src/mainboard/supermicro/x6dhe_g2/auto.updated.c index fcf8b76c19..8de5a2723b 100644 --- a/src/mainboard/supermicro/x6dhe_g2/auto.updated.c +++ b/src/mainboard/supermicro/x6dhe_g2/auto.updated.c @@ -103,7 +103,7 @@ static void main(unsigned long bist) outb(0x87,0x2e); outb(0x87,0x2e); pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c index 6a284981b0..ea8f3590a5 100644 --- a/src/mainboard/supermicro/x6dhe_g2/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c @@ -109,7 +109,7 @@ void *smp_write_config_table(void *v) } else { printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n"); - printk_debug("DEBUG: Dev= %p\n", dev); + printk_debug("CONFIG_DEBUG: Dev= %p\n", dev); } /* PXHd apic 5 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,3)); @@ -121,7 +121,7 @@ void *smp_write_config_table(void *v) } else { printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n"); - printk_debug("DEBUG: Dev= %p\n", dev); + printk_debug("CONFIG_DEBUG: Dev= %p\n", dev); } } diff --git a/src/mainboard/supermicro/x6dhr_ig/Config.lb b/src/mainboard/supermicro/x6dhr_ig/Config.lb index 837beb45f4..7d70dcf5db 100644 --- a/src/mainboard/supermicro/x6dhr_ig/Config.lb +++ b/src/mainboard/supermicro/x6dhr_ig/Config.lb @@ -1,10 +1,10 @@ ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## @@ -18,30 +18,30 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/supermicro/x6dhr_ig/Options.lb b/src/mainboard/supermicro/x6dhr_ig/Options.lb index 808fe21018..b6f853242a 100644 --- a/src/mainboard/supermicro/x6dhr_ig/Options.lb +++ b/src/mainboard/supermicro/x6dhr_ig/Options.lb @@ -1,57 +1,57 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_BTEXT uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY ### @@ -59,14 +59,14 @@ uses OBJCOPY ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1048576 +default CONFIG_ROM_SIZE=1048576 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -78,31 +78,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=16 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=16 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -120,39 +120,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="X6DHR" -default MAINBOARD_VENDOR= "Supermicro" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 +default CONFIG_MAINBOARD_PART_NUMBER="X6DHR" +default CONFIG_MAINBOARD_VENDOR= "Supermicro" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -167,8 +167,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -183,21 +183,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -209,17 +209,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ## ## Don't enable the btext console diff --git a/src/mainboard/supermicro/x6dhr_ig/auto.c b/src/mainboard/supermicro/x6dhr_ig/auto.c index 92020189d2..722157b454 100644 --- a/src/mainboard/supermicro/x6dhr_ig/auto.c +++ b/src/mainboard/supermicro/x6dhr_ig/auto.c @@ -103,7 +103,7 @@ static void main(unsigned long bist) outb(0x87,0x2e); outb(0x87,0x2e); pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/x6dhr_ig2/Config.lb b/src/mainboard/supermicro/x6dhr_ig2/Config.lb index b223a37523..4aab4fb04b 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/Config.lb +++ b/src/mainboard/supermicro/x6dhr_ig2/Config.lb @@ -1,10 +1,10 @@ ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 128 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb ## @@ -18,30 +18,30 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/supermicro/x6dhr_ig2/Options.lb b/src/mainboard/supermicro/x6dhr_ig2/Options.lb index 808fe21018..b6f853242a 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/Options.lb +++ b/src/mainboard/supermicro/x6dhr_ig2/Options.lb @@ -1,57 +1,57 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_LOGICAL_CPUS uses CONFIG_MAX_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_BTEXT uses CC -uses HOSTCC -uses CROSS_COMPILE -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_CROSS_COMPILE +uses CONFIG_OBJCOPY ### @@ -59,14 +59,14 @@ uses OBJCOPY ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1048576 +default CONFIG_ROM_SIZE=1048576 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Delay timer options @@ -78,31 +78,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=16 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=16 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -120,39 +120,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="X6DHR" -default MAINBOARD_VENDOR= "Supermicro" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 +default CONFIG_MAINBOARD_PART_NUMBER="X6DHR" +default CONFIG_MAINBOARD_VENDOR= "Supermicro" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -167,8 +167,8 @@ default CONFIG_ROM_PAYLOAD=1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -183,21 +183,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -209,17 +209,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ## ## Don't enable the btext console diff --git a/src/mainboard/supermicro/x6dhr_ig2/auto.c b/src/mainboard/supermicro/x6dhr_ig2/auto.c index 7be6250650..97eaca3a63 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/auto.c +++ b/src/mainboard/supermicro/x6dhr_ig2/auto.c @@ -103,7 +103,7 @@ static void main(unsigned long bist) outb(0x87,0x2e); outb(0x87,0x2e); pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/technexion/tim8690/Config.lb b/src/mainboard/technexion/tim8690/Config.lb index 8c2f6bc0cb..9ee9be4289 100644 --- a/src/mainboard/technexion/tim8690/Config.lb +++ b/src/mainboard/technexion/tim8690/Config.lb @@ -19,8 +19,8 @@ ## ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -33,18 +33,18 @@ driver mainboard.o #dir /drivers/si/3114 -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object get_bus_conf.o object irq_tables.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o object fadt.o makerule dsdt.c - depends "$(MAINBOARD)/acpi/*.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl" + depends "$(CONFIG_MAINBOARD)/acpi/*.asl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o @@ -55,15 +55,15 @@ end if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -87,7 +87,7 @@ ldscript /cpu/x86/16bit/entry16.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -111,7 +111,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/technexion/tim8690/Options.lb b/src/mainboard/technexion/tim8690/Options.lb index d4300898ec..0f8753254d 100644 --- a/src/mainboard/technexion/tim8690/Options.lb +++ b/src/mainboard/technexion/tim8690/Options.lb @@ -19,133 +19,133 @@ ## ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_USE_PRINTK_IN_CAR uses CONFIG_VIDEO_MB uses CONFIG_GFXUMA -uses HAVE_MAINBOARD_RESOURCES +uses CONFIG_HAVE_MAINBOARD_RESOURCES ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default CONFIG_HAVE_OPTION_TABLE=0 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -159,7 +159,7 @@ default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -167,23 +167,23 @@ default CONFIG_PCI_ROM_RUN=1 # BTDC: Only one HT device on Herring. #HT Unit ID offset -#default HT_CHAIN_UNITID_BASE=0x6 -default HT_CHAIN_UNITID_BASE=0x0 +#default CONFIG_HT_CHAIN_UNITID_BASE=0x6 +default CONFIG_HT_CHAIN_UNITID_BASE=0x0 #real SB Unit ID -default HT_CHAIN_END_UNITID_BASE=0x1 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1 #make the SB HT chain on bus 0 -default SB_HT_CHAIN_ON_BUS0=1 +default CONFIG_SB_HT_CHAIN_ON_BUS0=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x8000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x8000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 ## @@ -194,39 +194,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="tim8690" -default MAINBOARD_VENDOR="technexion" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 +default CONFIG_MAINBOARD_PART_NUMBER="tim8690" +default CONFIG_MAINBOARD_VENDOR="technexion" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 ## ## coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -240,8 +240,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -259,21 +259,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -285,21 +285,21 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" default CONFIG_VIDEO_MB=1 default CONFIG_GFXUMA=1 -default HAVE_MAINBOARD_RESOURCES=1 +default CONFIG_HAVE_MAINBOARD_RESOURCES=1 ### End Options.lb end diff --git a/src/mainboard/technexion/tim8690/acpi_tables.c b/src/mainboard/technexion/tim8690/acpi_tables.c index 9aaede4b8d..3829a7a082 100644 --- a/src/mainboard/technexion/tim8690/acpi_tables.c +++ b/src/mainboard/technexion/tim8690/acpi_tables.c @@ -59,7 +59,7 @@ static void dump_mem(u32 start, u32 end) extern u8 AmlCode[]; -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 extern u8 AmlCode_ssdt2[]; extern u8 AmlCode_ssdt3[]; extern u8 AmlCode_ssdt4[]; @@ -201,7 +201,7 @@ unsigned long write_acpi_tables(unsigned long start) current += ssdt->length; acpi_add_table(rsdt, ssdt); -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */ diff --git a/src/mainboard/technexion/tim8690/cache_as_ram_auto.c b/src/mainboard/technexion/tim8690/cache_as_ram_auto.c index 7d60c2703c..3f5ac57fa2 100644 --- a/src/mainboard/technexion/tim8690/cache_as_ram_auto.c +++ b/src/mainboard/technexion/tim8690/cache_as_ram_auto.c @@ -100,7 +100,7 @@ static inline int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_fxx/fidvid.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "northbridge/amd/amdk8/early_ht.c" @@ -139,14 +139,14 @@ normal_image: fallback_image: post_code(0x25); } -#endif /* USE_FALLBACK_IMAGE == 1 */ +#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -159,7 +159,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; - struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); if (bist == 0) { @@ -170,7 +170,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) sb600_lpc_init(); /* it8712f_enable_serial does not use its 1st parameter. */ - it8712f_enable_serial(0, TTYS0_BASE); + it8712f_enable_serial(0, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); uart_init(); console_init(); diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c index 9a953ef90d..fb990fd9df 100644 --- a/src/mainboard/technexion/tim8690/mptable.c +++ b/src/mainboard/technexion/tim8690/mptable.c @@ -142,7 +142,7 @@ void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if HAVE_ACPI_TABLES == 0 +#if CONFIG_HAVE_ACPI_TABLES == 0 #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else diff --git a/src/mainboard/technologic/ts5300/Config.lb b/src/mainboard/technologic/ts5300/Config.lb index 6d2635770c..525f82e3ef 100644 --- a/src/mainboard/technologic/ts5300/Config.lb +++ b/src/mainboard/technologic/ts5300/Config.lb @@ -1,8 +1,8 @@ -default ROM_SIZE = 128 * 1024 -default FALLBACK_SIZE = 0x10000 +default CONFIG_ROM_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = 0x10000 -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 32 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 32 * 1024 include /config/nofailovercalculation.lb ## @@ -16,29 +16,29 @@ arch i386 end ## driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -52,7 +52,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -74,7 +74,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/technologic/ts5300/Options.lb b/src/mainboard/technologic/ts5300/Options.lb index 7f2ad59503..461264a474 100644 --- a/src/mainboard/technologic/ts5300/Options.lb +++ b/src/mainboard/technologic/ts5300/Options.lb @@ -1,75 +1,75 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_COMPRESS uses CONFIG_ROM_PAYLOAD uses CONFIG_USE_INIT -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_CONSOLE_SERIAL8250 -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x2f8 +default CONFIG_TTYS0_BASE=0x2f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 -default DEFAULT_CONSOLE_LOGLEVEL=9 -default MAXIMUM_CONSOLE_LOGLEVEL=9 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -78,63 +78,63 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=7 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=7 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" # # CBFS diff --git a/src/mainboard/technologic/ts5300/mainboard.c b/src/mainboard/technologic/ts5300/mainboard.c index 3ce22f0e9e..343dbdf73c 100644 --- a/src/mainboard/technologic/ts5300/mainboard.c +++ b/src/mainboard/technologic/ts5300/mainboard.c @@ -142,7 +142,7 @@ static void enable_dev(struct device *dev) { /* hack for IDIOTIC need to fix rom_start */ printk_err("Patching rom_start due to sc520 limits\n"); rom_start = 0x09400000 + 0xe0000; - rom_end = rom_start + PAYLOAD_SIZE - 1; + rom_end = rom_start + CONFIG_PAYLOAD_SIZE - 1; printk_err("TS5300 EXIT %s\n", __func__); diff --git a/src/mainboard/televideo/tc7020/Config.lb b/src/mainboard/televideo/tc7020/Config.lb index 8d552d6992..66b1914ef7 100644 --- a/src/mainboard/televideo/tc7020/Config.lb +++ b/src/mainboard/televideo/tc7020/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/televideo/tc7020/Options.lb b/src/mainboard/televideo/tc7020/Options.lb index f215c5a622..96f8739ccc 100644 --- a/src/mainboard/televideo/tc7020/Options.lb +++ b/src/mainboard/televideo/tc7020/Options.lb @@ -18,45 +18,45 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 @@ -64,7 +64,7 @@ uses CONFIG_VIDEO_MB uses CONFIG_SPLASH_GRAPHIC uses CONFIG_GX1_VIDEO uses CONFIG_GX1_VIDEOMODE -uses PIRQ_ROUTE +uses CONFIG_PIRQ_ROUTE ## Enable VGA with a splash screen (only 640x480 to run on most monitors). ## We want to support up to 1024x768@16 so we need 2MiB video memory. @@ -73,36 +73,36 @@ default CONFIG_GX1_VIDEO = 1 default CONFIG_GX1_VIDEOMODE = 0 default CONFIG_SPLASH_GRAPHIC = 1 default CONFIG_VIDEO_MB = 2 -default HAVE_PIRQ_TABLE=0 -default PIRQ_ROUTE=1 +default CONFIG_HAVE_PIRQ_TABLE=0 +default CONFIG_PIRQ_ROUTE=1 -default ROM_SIZE = 256 * 1024 -default MAINBOARD_VENDOR = "TeleVideo" -default MAINBOARD_PART_NUMBER = "TC7020" -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_MAINBOARD_VENDOR = "TeleVideo" +default CONFIG_MAINBOARD_PART_NUMBER = "TC7020" +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 3 # Soldered NIC, internal USB, mini PCI slot -default HAVE_OPTION_TABLE = 0 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 3 # Soldered NIC, internal USB, mini PCI slot +default CONFIG_HAVE_OPTION_TABLE = 0 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc " -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc " +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 6 -default MAXIMUM_CONSOLE_LOGLEVEL = 6 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6 # # CBFS diff --git a/src/mainboard/televideo/tc7020/auto.c b/src/mainboard/televideo/tc7020/auto.c index 9880011670..51d847b976 100644 --- a/src/mainboard/televideo/tc7020/auto.c +++ b/src/mainboard/televideo/tc7020/auto.c @@ -38,7 +38,7 @@ static void main(unsigned long bist) { /* Initialize the serial console. */ - pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/televideo/tc7020/irq_tables.c b/src/mainboard/televideo/tc7020/irq_tables.c index d31fa17700..f8af382b22 100644 --- a/src/mainboard/televideo/tc7020/irq_tables.c +++ b/src/mainboard/televideo/tc7020/irq_tables.c @@ -48,7 +48,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* There can be a total of IRQ_SLOT_COUNT devices on the bus */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be a total of CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ EXCLUSIVE_PCI_IRQS, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/thomson/ip1000/Config.lb b/src/mainboard/thomson/ip1000/Config.lb index 8177b80e5f..59e4f7705c 100644 --- a/src/mainboard/thomson/ip1000/Config.lb +++ b/src/mainboard/thomson/ip1000/Config.lb @@ -18,42 +18,42 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end # object reset.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object fadt.o object dsdt.o object acpi_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -63,7 +63,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/thomson/ip1000/Options.lb b/src/mainboard/thomson/ip1000/Options.lb index 2efa484bbf..b80c53f2d8 100644 --- a/src/mainboard/thomson/ip1000/Options.lb +++ b/src/mainboard/thomson/ip1000/Options.lb @@ -31,71 +31,71 @@ uses CONFIG_ROM_PAYLOAD_START uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_UDELAY_TSC uses CONFIG_VIDEO_MB -uses CROSS_COMPILE -uses DEFAULT_CONSOLE_LOGLEVEL -uses FALLBACK_SIZE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses HAVE_FALLBACK_BOOT -uses HAVE_MP_TABLE -uses HAVE_OPTION_TABLE -uses HAVE_PIRQ_TABLE -uses HEAP_SIZE -uses HOSTCC -uses IRQ_SLOT_COUNT +uses CONFIG_CROSS_COMPILE +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_FALLBACK_SIZE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HEAP_SIZE +uses CONFIG_HOSTCC +uses CONFIG_IRQ_SLOT_COUNT uses COREBOOT_EXTRA_VERSION -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER -uses MAXIMUM_CONSOLE_LOGLEVEL -uses OBJCOPY -uses PAYLOAD_SIZE -uses _RAMBASE -uses _ROMBASE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET -uses ROM_SIZE -uses STACK_SIZE -uses TTYS0_BASE -uses TTYS0_BAUD -uses TTYS0_LCS -uses USE_FALLBACK_IMAGE -uses USE_OPTION_TABLE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_OBJCOPY +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_RAMBASE +uses CONFIG_ROMBASE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET +uses CONFIG_ROM_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_LCS +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE -default ROM_SIZE = 512 * 1024 -default ROM_IMAGE_SIZE = 128 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default FALLBACK_SIZE = 256 * 1024 +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_FALLBACK_SIZE = 256 * 1024 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 7 -default HAVE_MP_TABLE = 0 -default HAVE_ACPI_TABLES = 0 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 7 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_ACPI_TABLES = 0 default CONFIG_IOAPIC = 0 -default HAVE_OPTION_TABLE = 0 +default CONFIG_HAVE_OPTION_TABLE = 0 default CONFIG_CONSOLE_VGA = 0 default CONFIG_PCI_ROM_RUN = 0 default CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0 default CONFIG_VIDEO_MB = 0 -default STACK_SIZE = 0x2000 -default HEAP_SIZE = 0x4000 -default _RAMBASE = 0x00004000 -default USE_OPTION_TABLE = 0 +default CONFIG_STACK_SIZE = 0x2000 +default CONFIG_HEAP_SIZE = 0x4000 +default CONFIG_RAMBASE = 0x00004000 +default CONFIG_USE_OPTION_TABLE = 0 default CONFIG_ROM_PAYLOAD = 1 -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 -default MAINBOARD_VENDOR = "THOMSON" -default MAINBOARD_PART_NUMBER = "IP1000" +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAINBOARD_VENDOR = "THOMSON" +default CONFIG_MAINBOARD_PART_NUMBER = "IP1000" # # CBFS # diff --git a/src/mainboard/thomson/ip1000/auto.c b/src/mainboard/thomson/ip1000/auto.c index 8760f89d6f..9c31db5bcd 100644 --- a/src/mainboard/thomson/ip1000/auto.c +++ b/src/mainboard/thomson/ip1000/auto.c @@ -101,7 +101,7 @@ static void main(unsigned long bist) hard_reset(); } - smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE); + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); uart_init(); console_init(); diff --git a/src/mainboard/thomson/ip1000/irq_tables.c b/src/mainboard/thomson/ip1000/irq_tables.c index daec6f0274..0ec955126e 100644 --- a/src/mainboard/thomson/ip1000/irq_tables.c +++ b/src/mainboard/thomson/ip1000/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* there can be total 7 devices on the bus */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total 7 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/totalimpact/briq/Config.lb b/src/mainboard/totalimpact/briq/Config.lb index 968471c553..c380a86848 100644 --- a/src/mainboard/totalimpact/briq/Config.lb +++ b/src/mainboard/totalimpact/briq/Config.lb @@ -46,4 +46,4 @@ end ## Build the objects we have code for in this directory. ## -addaction coreboot.a "$(CROSS_COMPILE)ranlib coreboot.a" +addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a" diff --git a/src/mainboard/totalimpact/briq/Options.lb b/src/mainboard/totalimpact/briq/Options.lb index 3a06b57be5..07c18e1eed 100644 --- a/src/mainboard/totalimpact/briq/Options.lb +++ b/src/mainboard/totalimpact/briq/Options.lb @@ -2,77 +2,77 @@ ## Config file for the Total Impact briQ ## -uses TTYS0_DIV +uses CONFIG_TTYS0_DIV uses CONFIG_CBFS uses CONFIG_ARCH_X86 -uses TTYS0_BASE +uses CONFIG_TTYS0_BASE uses CONFIG_BRIQ_750FX uses CONFIG_BRIQ_7400 -uses ISA_IO_BASE -uses ISA_MEM_BASE -uses PCIC0_CFGADDR -uses PCIC0_CFGDATA -uses _IO_BASE -uses HAVE_OPTION_TABLE +uses CONFIG_ISA_IO_BASE +uses CONFIG_ISA_MEM_BASE +uses CONFIG_PCIC0_CFGADDR +uses CONFIG_PCIC0_CFGDATA +uses CONFIG_IO_BASE +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_COMPRESS -uses DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_USE_INIT -uses NO_POST +uses CONFIG_NO_POST uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_IDE_PAYLOAD uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses IDE_BOOT_DRIVE -uses IDE_SWAB IDE_OFFSET -uses ROM_SIZE -uses ROM_IMAGE_SIZE -uses _RESET -uses _EXCEPTION_VECTORS -uses _ROMBASE -uses _ROMSTART -uses _RAMBASE -uses _RAMSTART -uses STACK_SIZE -uses HEAP_SIZE +uses CONFIG_IDE_BOOT_DRIVE +uses CONFIG_IDE_SWAB CONFIG_IDE_OFFSET +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_RESET +uses CONFIG_EXCEPTION_VECTORS +uses CONFIG_ROMBASE +uses CONFIG_ROMSTART +uses CONFIG_RAMBASE +uses CONFIG_RAMSTART +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE uses CONFIG_BRIQ_750FX uses CONFIG_BRIQ_7400 uses CONFIG_SYS_CLK_FREQ -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY ## ## Set memory map ## -default ISA_IO_BASE=0x80000000 -default ISA_MEM_BASE=0xc0000000 -default PCIC0_CFGADDR=0xff5f8000 -default PCIC0_CFGDATA=0xff5f8010 -default _IO_BASE=ISA_IO_BASE +default CONFIG_ISA_IO_BASE=0x80000000 +default CONFIG_ISA_MEM_BASE=0xc0000000 +default CONFIG_PCIC0_CFGADDR=0xff5f8000 +default CONFIG_PCIC0_CFGDATA=0xff5f8010 +default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE ## ## The briQ uses weird clocking, 4 = 115200 ## -default TTYS0_DIV=4 +default CONFIG_TTYS0_DIV=4 ## ## Set UART base address ## -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc" +default CONFIG_HOSTCC="gcc" ## use a cross compiler -#default CROSS_COMPILE="powerpc-eabi-" -#default CROSS_COMPILE="ppc_74xx-" +#default CONFIG_CROSS_COMPILE="powerpc-eabi-" +#default CONFIG_CROSS_COMPILE="ppc_74xx-" default CONFIG_ARCH_X86=0 ## Use stage 1 initialization code @@ -82,24 +82,24 @@ default CONFIG_USE_INIT=1 default CONFIG_COMPRESS=0 ## Turn off POST codes -default NO_POST=1 +default CONFIG_NO_POST=1 ## Enable serial console -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 default CONFIG_CONSOLE_SERIAL8250=1 ## Boot linux from IDE default CONFIG_IDE_PAYLOAD=1 -default IDE_BOOT_DRIVE=0 -default IDE_SWAB=1 -default IDE_OFFSET=0 +default CONFIG_IDE_BOOT_DRIVE=0 +default CONFIG_IDE_SWAB=1 +default CONFIG_IDE_OFFSET=0 # ROM is 1Mb -default ROM_SIZE=1048576 +default CONFIG_ROM_SIZE=1048576 # Set stack and heap sizes (stage 2) -default STACK_SIZE=0x10000 -default HEAP_SIZE=0x10000 +default CONFIG_STACK_SIZE=0x10000 +default CONFIG_HEAP_SIZE=0x10000 ## ## System clock @@ -108,21 +108,21 @@ default CONFIG_SYS_CLK_FREQ=33 # Sandpoint Demo Board ## Base of ROM -default _ROMBASE=0xfff00000 +default CONFIG_ROMBASE=0xfff00000 ## Sandpoint reset vector -default _RESET=_ROMBASE+0x100 +default CONFIG_RESET=CONFIG_ROMBASE+0x100 ## Exception vectors (other than reset vector) -default _EXCEPTION_VECTORS=_RESET+0x100 +default CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100 ## Start of coreboot in the boot rom -## = _RESET + exeception vector table size -default _ROMSTART=_RESET+0x3100 +## = CONFIG_RESET + exeception vector table size +default CONFIG_ROMSTART=CONFIG_RESET+0x3100 ## Coreboot C code runs at this location in RAM -default _RAMBASE=0x00100000 -default _RAMSTART=0x00100000 +default CONFIG_RAMBASE=0x00100000 +default CONFIG_RAMSTART=0x00100000 default CONFIG_BRIQ_750FX=1 #default CONFIG_BRIQ_7400=1 diff --git a/src/mainboard/totalimpact/briq/init.c b/src/mainboard/totalimpact/briq/init.c index fd9283d37a..b7edf0b7e9 100644 --- a/src/mainboard/totalimpact/briq/init.c +++ b/src/mainboard/totalimpact/briq/init.c @@ -41,7 +41,7 @@ board_init2(void) /* * Enable UART */ - uart8250_init(TTYS0_BASE, TTYS0_DIV, TTYS0_LCS); + uart8250_init(CONFIG_TTYS0_BASE, CONFIG_TTYS0_DIV, CONFIG_TTYS0_LCS); printk_info("briQ initialized...\n"); } diff --git a/src/mainboard/tyan/s1846/Config.lb b/src/mainboard/tyan/s1846/Config.lb index 1cfed3286a..828db296ed 100644 --- a/src/mainboard/tyan/s1846/Config.lb +++ b/src/mainboard/tyan/s1846/Config.lb @@ -18,38 +18,38 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -59,7 +59,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/tyan/s1846/Options.lb b/src/mainboard/tyan/s1846/Options.lb index e5ebc85be6..9f3680c391 100644 --- a/src/mainboard/tyan/s1846/Options.lb +++ b/src/mainboard/tyan/s1846/Options.lb @@ -18,83 +18,83 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -default ROM_SIZE = 256 * 1024 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 -default HAVE_HARD_RESET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_PIRQ_TABLE = 0 -default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. -default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -default HAVE_OPTION_TABLE = 0 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_PIRQ_TABLE = 0 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 # 8n1 -default DEFAULT_CONSOLE_LOGLEVEL = 9 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 diff --git a/src/mainboard/tyan/s1846/auto.c b/src/mainboard/tyan/s1846/auto.c index 17ab6b02ed..5720e6709d 100644 --- a/src/mainboard/tyan/s1846/auto.c +++ b/src/mainboard/tyan/s1846/auto.c @@ -54,7 +54,7 @@ static void main(unsigned long bist) if (bist == 0) early_mtrr_init(); - pc87309_enable_serial(SERIAL_DEV, TTYS0_BASE); + pc87309_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2735/Config.lb b/src/mainboard/tyan/s2735/Config.lb index f051c5f352..9cc0bc3aea 100644 --- a/src/mainboard/tyan/s2735/Config.lb +++ b/src/mainboard/tyan/s2735/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1 @@ -10,21 +10,21 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end object reset.o if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -49,7 +49,7 @@ ldscript /cpu/x86/16bit/entry16.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -73,7 +73,7 @@ mainboardinit cpu/x86/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s2735/Options.lb b/src/mainboard/tyan/s2735/Options.lb index b52c94b734..7a5d39b0a5 100644 --- a/src/mainboard/tyan/s2735/Options.lb +++ b/src/mainboard/tyan/s2735/Options.lb @@ -1,82 +1,82 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_USE_INIT uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_BTEXT -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. #512K bytes -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 #1M bytes -#default ROM_SIZE=1048576 +#default CONFIG_ROM_SIZE=1048576 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE=131072 ### ### Build options @@ -85,12 +85,12 @@ default FALLBACK_SIZE=131072 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## Delay timer options ## @@ -100,26 +100,26 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=15 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=15 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -130,7 +130,7 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -default SERIAL_CPU_INIT=0 +default CONFIG_SERIAL_CPU_INIT=0 #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 @@ -142,10 +142,10 @@ default SERIAL_CPU_INIT=0 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -#default DCACHE_RAM_BASE=0xF2000000 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +#default CONFIG_DCACHE_RAM_BASE=0xF2000000 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_PRINTK_IN_CAR=1 @@ -157,37 +157,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2735" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2735 +default CONFIG_MAINBOARD_PART_NUMBER="s2735" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2735 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -201,8 +201,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -217,21 +217,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -243,17 +243,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2735/cache_as_ram_auto.c b/src/mainboard/tyan/s2735/cache_as_ram_auto.c index 8c4a0370e0..427b070bdb 100644 --- a/src/mainboard/tyan/s2735/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2735/cache_as_ram_auto.c @@ -79,7 +79,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/x86/car/copy_and_run.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/intel/i82801er/cmos_failover.c" @@ -147,7 +147,7 @@ void amd64_main(unsigned long bist) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -228,10 +228,10 @@ cpu_reset_x: } __asm__ volatile ( - /* set new esp */ /* before _RAMBASE */ + /* set new esp */ /* before CONFIG_RAMBASE */ "subl %0, %%ebp\n\t" "subl %0, %%esp\n\t" - ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE ) + ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE ) ); { diff --git a/src/mainboard/tyan/s2850/Config.lb b/src/mainboard/tyan/s2850/Config.lb index 84bb7084eb..59dcd8e557 100644 --- a/src/mainboard/tyan/s2850/Config.lb +++ b/src/mainboard/tyan/s2850/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -12,21 +12,21 @@ driver mainboard.o #dir /drivers/si/3114 -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -35,7 +35,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -53,7 +53,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s2850/Options.lb b/src/mainboard/tyan/s2850/Options.lb index f9317f7bd2..37814240be 100644 --- a/src/mainboard/tyan/s2850/Options.lb +++ b/src/mainboard/tyan/s2850/Options.lb @@ -1,64 +1,64 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -67,50 +67,50 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=12 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=12 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -122,7 +122,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -132,9 +132,9 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## @@ -145,37 +145,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="S2850" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2850 +default CONFIG_MAINBOARD_PART_NUMBER="S2850" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2850 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -189,8 +189,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -207,21 +207,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -233,17 +233,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2850/cache_as_ram_auto.c b/src/mainboard/tyan/s2850/cache_as_ram_auto.c index 373e0a6192..378c05a723 100644 --- a/src/mainboard/tyan/s2850/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2850/cache_as_ram_auto.c @@ -94,7 +94,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -150,7 +150,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -179,7 +179,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s2875/Config.lb b/src/mainboard/tyan/s2875/Config.lb index bb3393fe3c..73481883f8 100644 --- a/src/mainboard/tyan/s2875/Config.lb +++ b/src/mainboard/tyan/s2875/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -12,21 +12,21 @@ driver mainboard.o #dir /drivers/si/3114 -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -35,7 +35,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -53,7 +53,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s2875/Options.lb b/src/mainboard/tyan/s2875/Options.lb index 01daaa4e6f..5eaa91acc6 100644 --- a/src/mainboard/tyan/s2875/Options.lb +++ b/src/mainboard/tyan/s2875/Options.lb @@ -1,64 +1,64 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -67,51 +67,51 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=13 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=13 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -123,7 +123,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -133,9 +133,9 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## @@ -146,37 +146,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2875" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2875 +default CONFIG_MAINBOARD_PART_NUMBER="s2875" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2875 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -190,8 +190,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -208,21 +208,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -234,17 +234,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2875/cache_as_ram_auto.c b/src/mainboard/tyan/s2875/cache_as_ram_auto.c index 893635b9f8..1912beeeb8 100644 --- a/src/mainboard/tyan/s2875/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2875/cache_as_ram_auto.c @@ -85,7 +85,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -138,7 +138,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -176,7 +176,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) init_cpus(cpu_init_detectedx); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb index 85ade62c85..3ca46b67bb 100644 --- a/src/mainboard/tyan/s2880/Config.lb +++ b/src/mainboard/tyan/s2880/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -12,21 +12,21 @@ driver mainboard.o #dir /drivers/si/3114 -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -35,7 +35,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -53,7 +53,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s2880/Options.lb b/src/mainboard/tyan/s2880/Options.lb index 8b37f911db..0a1c746f20 100644 --- a/src/mainboard/tyan/s2880/Options.lb +++ b/src/mainboard/tyan/s2880/Options.lb @@ -1,64 +1,64 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -67,50 +67,50 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=13 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=13 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -122,7 +122,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=0 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -132,9 +132,9 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## @@ -145,37 +145,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="S2880" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2880 +default CONFIG_MAINBOARD_PART_NUMBER="S2880" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2880 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -189,8 +189,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -207,21 +207,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -233,17 +233,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2880/cache_as_ram_auto.c b/src/mainboard/tyan/s2880/cache_as_ram_auto.c index eb4bcae466..bfb89116c6 100644 --- a/src/mainboard/tyan/s2880/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2880/cache_as_ram_auto.c @@ -86,7 +86,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -138,7 +138,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -177,7 +177,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s2881/Config.lb b/src/mainboard/tyan/s2881/Config.lb index f9ac2a2570..6480067300 100644 --- a/src/mainboard/tyan/s2881/Config.lb +++ b/src/mainboard/tyan/s2881/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -12,21 +12,21 @@ driver mainboard.o #dir /drivers/si/3114 object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -35,7 +35,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -53,7 +53,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s2881/Options.lb b/src/mainboard/tyan/s2881/Options.lb index d83638715b..18087be3d3 100644 --- a/src/mainboard/tyan/s2881/Options.lb +++ b/src/mainboard/tyan/s2881/Options.lb @@ -1,69 +1,69 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -72,50 +72,50 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=9 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -127,19 +127,19 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 ##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0x0a +default CONFIG_HT_CHAIN_UNITID_BASE=0x0a ##real SB Unit ID, default is 0x20, mean dont touch it at last -default HT_CHAIN_END_UNITID_BASE=0x06 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x06 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=0 +default CONFIG_SB_HT_CHAIN_ON_BUS0=0 ##only offset for SB chain?, default is yes(1) -#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -149,9 +149,9 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## @@ -162,37 +162,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2881" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2881 +default CONFIG_MAINBOARD_PART_NUMBER="s2881" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2881 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -206,8 +206,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -224,21 +224,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -250,17 +250,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2881/cache_as_ram_auto.c b/src/mainboard/tyan/s2881/cache_as_ram_auto.c index 0f853b8af1..9beb7afaeb 100644 --- a/src/mainboard/tyan/s2881/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2881/cache_as_ram_auto.c @@ -99,7 +99,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -155,7 +155,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -185,7 +185,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s2881/get_bus_conf.c b/src/mainboard/tyan/s2881/get_bus_conf.c index d4c01675ab..1ed1e0dbaa 100644 --- a/src/mainboard/tyan/s2881/get_bus_conf.c +++ b/src/mainboard/tyan/s2881/get_bus_conf.c @@ -82,7 +82,7 @@ void get_bus_conf(void) dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); @@ -105,7 +105,7 @@ void get_bus_conf(void) dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0)); if (dev) { bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); diff --git a/src/mainboard/tyan/s2882/Config.lb b/src/mainboard/tyan/s2882/Config.lb index c61a0f3291..687169622a 100644 --- a/src/mainboard/tyan/s2882/Config.lb +++ b/src/mainboard/tyan/s2882/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -12,21 +12,21 @@ driver mainboard.o #dir /drivers/si/3114 -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -35,7 +35,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -53,7 +53,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s2882/Options.lb b/src/mainboard/tyan/s2882/Options.lb index 9e6b36db70..cfa2b679b9 100644 --- a/src/mainboard/tyan/s2882/Options.lb +++ b/src/mainboard/tyan/s2882/Options.lb @@ -1,64 +1,64 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -67,50 +67,50 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=15 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=15 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -122,7 +122,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -132,9 +132,9 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 ## @@ -145,37 +145,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="S2882" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2882 +default CONFIG_MAINBOARD_PART_NUMBER="S2882" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2882 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -189,8 +189,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -207,21 +207,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -233,17 +233,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2882/cache_as_ram_auto.c b/src/mainboard/tyan/s2882/cache_as_ram_auto.c index a249fa1a8d..62d9a69d10 100644 --- a/src/mainboard/tyan/s2882/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2882/cache_as_ram_auto.c @@ -89,7 +89,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -141,7 +141,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -180,7 +180,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb index 9ee230a90e..74f9c53e65 100644 --- a/src/mainboard/tyan/s2885/Config.lb +++ b/src/mainboard/tyan/s2885/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end @@ -12,21 +12,21 @@ driver mainboard.o #dir /drivers/si/3114 object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -35,7 +35,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -53,7 +53,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -77,7 +77,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s2885/Options.lb b/src/mainboard/tyan/s2885/Options.lb index 88e7bf2790..2bb6681057 100644 --- a/src/mainboard/tyan/s2885/Options.lb +++ b/src/mainboard/tyan/s2885/Options.lb @@ -1,75 +1,75 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_LB_MEM_TOPK @@ -78,50 +78,50 @@ uses CONFIG_LB_MEM_TOPK ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -133,19 +133,19 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 ##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0x0a +default CONFIG_HT_CHAIN_UNITID_BASE=0x0a ##real SB Unit ID, default is 0x20, mean dont touch it at last -default HT_CHAIN_END_UNITID_BASE=0x06 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x06 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) -#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -155,14 +155,14 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 -default ENABLE_APIC_EXT_ID=1 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=0 +default CONFIG_ENABLE_APIC_EXT_ID=1 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=0 ## ## Build code to setup a generic IOAPIC @@ -172,37 +172,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2885" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2885 +default CONFIG_MAINBOARD_PART_NUMBER="s2885" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2885 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -216,8 +216,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -234,21 +234,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -260,17 +260,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2885/cache_as_ram_auto.c b/src/mainboard/tyan/s2885/cache_as_ram_auto.c index 711afbc645..c2f97df8ae 100644 --- a/src/mainboard/tyan/s2885/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2885/cache_as_ram_auto.c @@ -99,7 +99,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -155,7 +155,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -185,11 +185,11 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); -// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); +// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2885/get_bus_conf.c b/src/mainboard/tyan/s2885/get_bus_conf.c index b50f671f9b..eaf77cd569 100644 --- a/src/mainboard/tyan/s2885/get_bus_conf.c +++ b/src/mainboard/tyan/s2885/get_bus_conf.c @@ -85,7 +85,7 @@ void get_bus_conf(void) dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); @@ -108,7 +108,7 @@ void get_bus_conf(void) dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0)); if (dev) { bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; // printk_debug("bus_isa=%d\n",bus_isa); diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb index d1a3874435..f14894d23e 100644 --- a/src/mainboard/tyan/s2891/Config.lb +++ b/src/mainboard/tyan/s2891/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1 @@ -16,15 +16,15 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o makerule dsdt.c - depends "$(MAINBOARD)/dsdt.dsl" - action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.dsl" + depends "$(CONFIG_MAINBOARD)/dsdt.dsl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o @@ -34,13 +34,13 @@ end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -49,7 +49,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -67,7 +67,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -84,7 +84,7 @@ ldscript /southbridge/nvidia/ck804/id.lds ## ## ROMSTRAP table for CK804 ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end @@ -99,7 +99,7 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s2891/Options.lb b/src/mainboard/tyan/s2891/Options.lb index ed514efc1d..d3cc2c2eff 100644 --- a/src/mainboard/tyan/s2891/Options.lb +++ b/src/mainboard/tyan/s2891/Options.lb @@ -1,96 +1,96 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses HAVE_LOW_TABLES +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_HAVE_LOW_TABLES uses CONFIG_MULTIBOOT -uses HAVE_SMI_HANDLER -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_HAVE_SMI_HANDLER +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_CONSOLE_BTEXT -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_VGA_ROM_RUN uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_LB_MEM_TOPK -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE=512*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE=512*1024 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ### ### Build options @@ -99,48 +99,48 @@ default FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build SMI handler ## -default HAVE_SMI_HANDLER=0 +default CONFIG_HAVE_SMI_HANDLER=0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to provide ACPI support ## -default HAVE_ACPI_TABLES=1 -default HAVE_LOW_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_LOW_TABLES=1 default CONFIG_MULTIBOOT=0 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -157,19 +157,19 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 ##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0x0 +default CONFIG_HT_CHAIN_UNITID_BASE=0x0 ##real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x0 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) -#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 @@ -181,14 +181,14 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=0 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=0 #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -201,37 +201,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2891" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891 +default CONFIG_MAINBOARD_PART_NUMBER="s2891" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -245,8 +245,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -263,21 +263,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -289,17 +289,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2891/cache_as_ram_auto.c b/src/mainboard/tyan/s2891/cache_as_ram_auto.c index 6cf98abeb5..fd6c1c5236 100644 --- a/src/mainboard/tyan/s2891/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2891/cache_as_ram_auto.c @@ -77,7 +77,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -165,7 +165,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -195,7 +195,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s2892/Config.lb b/src/mainboard/tyan/s2892/Config.lb index 45672e99c6..04a53b57be 100644 --- a/src/mainboard/tyan/s2892/Config.lb +++ b/src/mainboard/tyan/s2892/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1 @@ -17,15 +17,15 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o makerule dsdt.c - depends "$(MAINBOARD)/dsdt.dsl" - action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.dsl" + depends "$(CONFIG_MAINBOARD)/dsdt.dsl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o @@ -35,13 +35,13 @@ end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -50,7 +50,7 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -68,7 +68,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -85,7 +85,7 @@ ldscript /southbridge/nvidia/ck804/id.lds ## ## ROMSTRAP table for CK804 ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end @@ -100,7 +100,7 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s2892/Options.lb b/src/mainboard/tyan/s2892/Options.lb index 0cfbcd5c56..efc4cba7a5 100644 --- a/src/mainboard/tyan/s2892/Options.lb +++ b/src/mainboard/tyan/s2892/Options.lb @@ -1,90 +1,90 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses HAVE_LOW_TABLES +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_HAVE_LOW_TABLES uses CONFIG_MULTIBOOT -uses HAVE_SMI_HANDLER -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_HAVE_SMI_HANDLER +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_CONSOLE_BTEXT -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_VGA_ROM_RUN uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_LB_MEM_TOPK -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE=1024*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE=1024*1024 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ### ### Build options @@ -93,48 +93,48 @@ default FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build SMI handler ## -default HAVE_SMI_HANDLER=0 +default CONFIG_HAVE_SMI_HANDLER=0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to provide ACPI support ## -default HAVE_ACPI_TABLES=1 -default HAVE_LOW_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_LOW_TABLES=1 default CONFIG_MULTIBOOT=0 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -151,19 +151,19 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 ##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0x0 +default CONFIG_HT_CHAIN_UNITID_BASE=0x0 ##real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x0 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 @@ -175,9 +175,9 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 @@ -189,37 +189,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2892" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2892 +default CONFIG_MAINBOARD_PART_NUMBER="s2892" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2892 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -233,8 +233,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -251,21 +251,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -277,17 +277,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2892/cache_as_ram_auto.c b/src/mainboard/tyan/s2892/cache_as_ram_auto.c index bafd6e9c9b..97f0660096 100644 --- a/src/mainboard/tyan/s2892/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2892/cache_as_ram_auto.c @@ -83,7 +83,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -155,7 +155,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -185,7 +185,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s2895/Config.lb b/src/mainboard/tyan/s2895/Config.lb index a8023fe0c7..3bf256f3e3 100644 --- a/src/mainboard/tyan/s2895/Config.lb +++ b/src/mainboard/tyan/s2895/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -12,15 +12,15 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o makerule dsdt.c - depends "$(MAINBOARD)/dsdt.dsl" - action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.dsl" + depends "$(CONFIG_MAINBOARD)/dsdt.dsl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o @@ -30,13 +30,13 @@ end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -45,13 +45,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -70,8 +70,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -79,7 +79,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -97,13 +97,13 @@ ldscript /southbridge/nvidia/ck804/id.lds ## ## ROMSTRAP table for CK804 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end @@ -119,12 +119,12 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb index 19c7cdfd73..58878494cd 100644 --- a/src/mainboard/tyan/s2895/Options.lb +++ b/src/mainboard/tyan/s2895/Options.lb @@ -1,103 +1,103 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses USE_FAILOVER_IMAGE -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses HAVE_LOW_TABLES +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_HAVE_LOW_TABLES uses CONFIG_MULTIBOOT -uses HAVE_SMI_HANDLER -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_HAVE_SMI_HANDLER +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_VGA_ROM_RUN uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses K8_HT_FREQ_1G_SUPPORT +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_K8_HT_FREQ_1G_SUPPORT -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_LB_MEM_TOPK -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE=1024*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE=1024*1024 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE=0x3f000 #FAILOVER: 4K -default FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -105,49 +105,49 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build SMI handler ## -default HAVE_SMI_HANDLER=0 +default CONFIG_HAVE_SMI_HANDLER=0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to provide ACPI support ## -default HAVE_ACPI_TABLES=1 -default HAVE_LOW_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_LOW_TABLES=1 default CONFIG_MULTIBOOT=0 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -163,25 +163,25 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -default SERIAL_CPU_INIT=0 +default CONFIG_SERIAL_CPU_INIT=0 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 ##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0x0 +default CONFIG_HT_CHAIN_UNITID_BASE=0x0 ##real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x0 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -190,14 +190,14 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=0 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=0 ## @@ -208,37 +208,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="s2895" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895 +default CONFIG_MAINBOARD_PART_NUMBER="s2895" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -252,8 +252,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -270,21 +270,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -296,17 +296,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2895/cache_as_ram_auto.c b/src/mainboard/tyan/s2895/cache_as_ram_auto.c index 43a6cf089e..2da764f24e 100644 --- a/src/mainboard/tyan/s2895/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2895/cache_as_ram_auto.c @@ -21,7 +21,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" @@ -44,7 +44,7 @@ #define SUPERIO_GPIO_IO_BASE 0x400 -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" @@ -120,7 +120,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -197,7 +197,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) fallback_image: // post_code(0x25); -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -211,21 +211,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -250,7 +250,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE); + lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s2912/Config.lb b/src/mainboard/tyan/s2912/Config.lb index 34638892ae..c8f3a8f041 100644 --- a/src/mainboard/tyan/s2912/Config.lb +++ b/src/mainboard/tyan/s2912/Config.lb @@ -19,8 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -33,30 +33,30 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -66,13 +66,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -91,8 +91,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -100,7 +100,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -118,13 +118,13 @@ ldscript /southbridge/nvidia/mcp55/id.lds ## ## ROMSTRAP table for MCP55 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end @@ -140,12 +140,12 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/tyan/s2912/Options.lb b/src/mainboard/tyan/s2912/Options.lb index 7222788349..a2166dd8b0 100644 --- a/src/mainboard/tyan/s2912/Options.lb +++ b/src/mainboard/tyan/s2912/Options.lb @@ -19,90 +19,90 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_USBDEBUG_DIRECT uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC +uses CONFIG_K8_HT_FREQ_1G_SUPPORT + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM @@ -110,9 +110,9 @@ uses CONFIG_LB_MEM_TOPK uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR @@ -121,21 +121,21 @@ uses CONFIG_USE_PRINTK_IN_CAR ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 -#default ROM_SIZE=0x100000 +default CONFIG_ROM_SIZE=524288 +#default CONFIG_ROM_SIZE=0x100000 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE=0x3f000 #FAILOVER: 4K -default FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -143,42 +143,42 @@ default CONFIG_LB_MEM_TOPK=2048 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=0 +default CONFIG_HAVE_ACPI_TABLES=0 ## extra SSDT num -default ACPI_SSDTX_NUM=3 +default CONFIG_ACPI_SSDTX_NUM=3 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -189,25 +189,25 @@ default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 -#default SERIAL_CPU_INIT=0 +#default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=0 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -216,16 +216,16 @@ default CONFIG_PCI_ROM_RUN=1 #default CONFIG_USBDEBUG_DIRECT=1 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default HT_CHAIN_UNITID_BASE=0 +default CONFIG_HT_CHAIN_UNITID_BASE=0 #real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x6 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -233,15 +233,15 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 default CONFIG_AP_CODE_IN_CAR=0 -default MEM_TRAIN_SEQ=1 -default WAIT_BEFORE_CPUS_INIT=1 +default CONFIG_MEM_TRAIN_SEQ=1 +default CONFIG_WAIT_BEFORE_CPUS_INIT=1 ## ## Build code to setup a generic IOAPIC @@ -251,37 +251,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="S2912" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912 +default CONFIG_MAINBOARD_PART_NUMBER="S2912" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0x8000 +default CONFIG_HEAP_SIZE=0x8000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00100000 +default CONFIG_RAMBASE=0x00100000 ## ## Load the payload from the ROM @@ -297,8 +297,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -314,21 +314,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -340,17 +340,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2912/apc_auto.c b/src/mainboard/tyan/s2912/apc_auto.c index d15f5ac346..8985b7affd 100644 --- a/src/mainboard/tyan/s2912/apc_auto.c +++ b/src/mainboard/tyan/s2912/apc_auto.c @@ -75,8 +75,8 @@ void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/tyan/s2912/cache_as_ram_auto.c b/src/mainboard/tyan/s2912/cache_as_ram_auto.c index 7c387b9bd0..5be6d82e9b 100644 --- a/src/mainboard/tyan/s2912/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2912/cache_as_ram_auto.c @@ -39,7 +39,7 @@ //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1 -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -56,7 +56,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT @@ -79,7 +79,7 @@ #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" @@ -150,7 +150,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -219,7 +219,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -232,21 +232,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -259,7 +259,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif }; - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; @@ -268,7 +268,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); @@ -287,7 +287,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/tyan/s2912_fam10/Config.lb b/src/mainboard/tyan/s2912_fam10/Config.lb index 2e66e5a470..26977d657d 100644 --- a/src/mainboard/tyan/s2912_fam10/Config.lb +++ b/src/mainboard/tyan/s2912_fam10/Config.lb @@ -19,8 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -33,30 +33,30 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -66,13 +66,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -91,8 +91,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -100,7 +100,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -118,13 +118,13 @@ ldscript /southbridge/nvidia/mcp55/id.lds ## ## ROMSTRAP table for MCP55 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end @@ -140,12 +140,12 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/tyan/s2912_fam10/Options.lb b/src/mainboard/tyan/s2912_fam10/Options.lb index 0f77329e6b..5d250e82a4 100644 --- a/src/mainboard/tyan/s2912_fam10/Options.lb +++ b/src/mainboard/tyan/s2912_fam10/Options.lb @@ -19,125 +19,125 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_USBDEBUG_DIRECT uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM uses CONFIG_LB_MEM_TOPK -uses PCI_BUS_SEGN_BITS +uses CONFIG_PCI_BUS_SEGN_BITS uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_AMDMCT uses CONFIG_USE_PRINTK_IN_CAR -uses CAR_FAM10 -uses AMD_UCODE_PATCH_FILE +uses CONFIG_CAR_FAM10 +uses CONFIG_AMD_UCODE_PATCH_FILE ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1024*1024 -#default ROM_SIZE=0x100000 +default CONFIG_ROM_SIZE=1024*1024 +#default CONFIG_ROM_SIZE=0x100000 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 -default FALLBACK_SIZE=0x3f000 -default FAILOVER_SIZE=0x01000 +default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=16384 @@ -145,42 +145,42 @@ default CONFIG_LB_MEM_TOPK=16384 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=0 +default CONFIG_HAVE_ACPI_TABLES=0 ## extra SSDT num -default ACPI_SSDTX_NUM=31 +default CONFIG_ACPI_SSDTX_NUM=31 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -191,22 +191,22 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS default CONFIG_LOGICAL_CPUS=1 -#default SERIAL_CPU_INIT=0 +#default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=1 -default APIC_ID_OFFSET=0x00 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=1 +default CONFIG_APIC_ID_OFFSET=0x00 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -215,16 +215,16 @@ default CONFIG_PCI_ROM_RUN=1 #default CONFIG_USBDEBUG_DIRECT=1 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default HT_CHAIN_UNITID_BASE=1 +default CONFIG_HT_CHAIN_UNITID_BASE=1 #real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x6 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -232,14 +232,14 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc4000 -default DCACHE_RAM_SIZE=0x0c000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc4000 +default CONFIG_DCACHE_RAM_SIZE=0x0c000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000 default CONFIG_USE_INIT=0 -default MEM_TRAIN_SEQ=2 -default WAIT_BEFORE_CPUS_INIT=0 +default CONFIG_MEM_TRAIN_SEQ=2 +default CONFIG_WAIT_BEFORE_CPUS_INIT=0 default CONFIG_AMDMCT = 1 ## @@ -250,10 +250,10 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="S2912 (Fam10)" -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912 +default CONFIG_MAINBOARD_PART_NUMBER="S2912 (Fam10)" +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912 ## ## Set microcode patch file name @@ -263,34 +263,34 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912 ## Barcelona rev DR-B2, B3: "mc_patch_01000095.h" ## Shanghai rev DA-C2: "mc_patch_0100009f.h" ## -default AMD_UCODE_PATCH_FILE="mc_patch_01000095.h" +default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000095.h" ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 32K heap ## -default HEAP_SIZE=0xc0000 +default CONFIG_HEAP_SIZE=0xc0000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00200000 +default CONFIG_RAMBASE=0x00200000 ## ## Load the payload from the ROM @@ -306,8 +306,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -323,21 +323,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -349,17 +349,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s2912_fam10/apc_auto.c b/src/mainboard/tyan/s2912_fam10/apc_auto.c index d15f5ac346..8985b7affd 100644 --- a/src/mainboard/tyan/s2912_fam10/apc_auto.c +++ b/src/mainboard/tyan/s2912_fam10/apc_auto.c @@ -75,8 +75,8 @@ void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c b/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c index 8121d34bf7..ffdf04a92b 100644 --- a/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c @@ -53,7 +53,7 @@ static void post_code(u8 value) { outb(value, 0x80); } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT @@ -75,7 +75,7 @@ static void post_code(u8 value) { #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" @@ -145,7 +145,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -215,7 +215,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) ); fallback_image: -#if HAVE_FAILOVER_BOOT==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -228,28 +228,28 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE==0 +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); u32 bsp_apicid = 0; u32 val; @@ -264,7 +264,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); printk_debug("\n"); diff --git a/src/mainboard/tyan/s2912_fam10/irq_tables.c b/src/mainboard/tyan/s2912_fam10/irq_tables.c index 86fa65f2c2..ea870a147b 100644 --- a/src/mainboard/tyan/s2912_fam10/irq_tables.c +++ b/src/mainboard/tyan/s2912_fam10/irq_tables.c @@ -111,11 +111,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info++; slot_num++; } -#if CBB - write_pirq_info(pirq_info, CBB, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +#if CONFIG_CBB + write_pirq_info(pirq_info, CONFIG_CBB, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; if(sysconf.nodes>32) { - write_pirq_info(pirq_info, CBB-1, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + write_pirq_info(pirq_info, CONFIG_CBB-1, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; } #endif diff --git a/src/mainboard/tyan/s2912_fam10/resourcemap.c b/src/mainboard/tyan/s2912_fam10/resourcemap.c index 73d3d43014..b638d4f718 100644 --- a/src/mainboard/tyan/s2912_fam10/resourcemap.c +++ b/src/mainboard/tyan/s2912_fam10/resourcemap.c @@ -49,14 +49,14 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CBB, CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CBB, CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CBB, CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CBB, CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CBB, CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CBB, CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CBB, CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 @@ -88,14 +88,14 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CBB, CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -129,14 +129,14 @@ static void setup_mb_resource_map(void) * This field defines the upp adddress bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CBB, CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CBB, CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -164,14 +164,14 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CBB, CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CBB, CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -198,10 +198,10 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CBB, CDB, 1, 0xC4), 0xFE000FC8, 0x00007000, -// PCI_ADDR(CBB, CDB, 1, 0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset - PCI_ADDR(CBB, CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00007000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -228,10 +228,10 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CBB, CDB, 1, 0xC0), 0xFE000FCC, 0x00000033, -// PCI_ADDR(CBB, CDB, 1, 0xC8), 0xFE000FCC, 0x00008033, - PCI_ADDR(CBB, CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000033, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00008033, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -269,10 +269,10 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ -// PCI_ADDR(CBB, CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */ -// PCI_ADDR(CBB, CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */ - PCI_ADDR(CBB, CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/tyan/s4880/Config.lb b/src/mainboard/tyan/s4880/Config.lb index eacd638313..c85db4b9b2 100644 --- a/src/mainboard/tyan/s4880/Config.lb +++ b/src/mainboard/tyan/s4880/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1 @@ -11,21 +11,21 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -34,7 +34,7 @@ if HAVE_PIRQ_TABLE object irq_tables.o end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -52,7 +52,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -76,7 +76,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s4880/Options.lb b/src/mainboard/tyan/s4880/Options.lb index 485ab8397b..05760e668c 100644 --- a/src/mainboard/tyan/s4880/Options.lb +++ b/src/mainboard/tyan/s4880/Options.lb @@ -1,120 +1,120 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=22 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=22 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -126,7 +126,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=4 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 @@ -136,14 +136,14 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 -default ENABLE_APIC_EXT_ID=1 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=0 +default CONFIG_ENABLE_APIC_EXT_ID=1 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=0 ## @@ -154,37 +154,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PART_NUMBER="s4880" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4880 +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PART_NUMBER="s4880" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4880 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -198,8 +198,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -216,21 +216,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -242,17 +242,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s4880/cache_as_ram_auto.c b/src/mainboard/tyan/s4880/cache_as_ram_auto.c index d7226afcef..0f403ab6ba 100644 --- a/src/mainboard/tyan/s4880/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s4880/cache_as_ram_auto.c @@ -112,7 +112,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -164,7 +164,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -226,7 +226,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) init_cpus(cpu_init_detectedx); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb index 97bf1e06b6..7da0a6773a 100644 --- a/src/mainboard/tyan/s4882/Config.lb +++ b/src/mainboard/tyan/s4882/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1 @@ -11,21 +11,21 @@ arch i386 end ## driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -34,7 +34,7 @@ if HAVE_PIRQ_TABLE object irq_tables.o end ## ## Build our 16 bit and 32 bit coreboot entry code ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -52,7 +52,7 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -76,7 +76,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end diff --git a/src/mainboard/tyan/s4882/Options.lb b/src/mainboard/tyan/s4882/Options.lb index e5eadf414f..3ae897bb7c 100644 --- a/src/mainboard/tyan/s4882/Options.lb +++ b/src/mainboard/tyan/s4882/Options.lb @@ -1,120 +1,120 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=524288 +default CONFIG_ROM_SIZE=524288 ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=131072 #256K -default FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=22 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=22 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -126,7 +126,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=4 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console #default CONFIG_CONSOLE_VGA=1 @@ -136,14 +136,14 @@ default HW_MEM_HOLE_SIZEK=0x100000 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xcf000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xcf000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 -default ENABLE_APIC_EXT_ID=1 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=0 +default CONFIG_ENABLE_APIC_EXT_ID=1 +default CONFIG_APIC_ID_OFFSET=0x10 +default CONFIG_LIFT_BSP_APIC_ID=0 ## ## Build code to setup a generic IOAPIC @@ -153,37 +153,37 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_VENDOR="Tyan" -default MAINBOARD_PART_NUMBER="s4882" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4882 +default CONFIG_MAINBOARD_VENDOR="Tyan" +default CONFIG_MAINBOARD_PART_NUMBER="s4882" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4882 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00002000 +default CONFIG_RAMBASE=0x00002000 ## ## Load the payload from the ROM @@ -197,8 +197,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -215,21 +215,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -241,17 +241,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/tyan/s4882/cache_as_ram_auto.c b/src/mainboard/tyan/s4882/cache_as_ram_auto.c index cdc1d2645f..b45e1dc467 100644 --- a/src/mainboard/tyan/s4882/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s4882/cache_as_ram_auto.c @@ -119,7 +119,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -171,7 +171,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -206,7 +206,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/via/epia-cn/Config.lb b/src/mainboard/via/epia-cn/Config.lb index c2f5a4ebc0..5e3149eb7e 100644 --- a/src/mainboard/via/epia-cn/Config.lb +++ b/src/mainboard/via/epia-cn/Config.lb @@ -19,40 +19,40 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_MP_TABLE object mptable.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_ACPI_TABLES object fadt.o object dsdt.o object acpi_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -62,7 +62,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/via/epia-cn/Options.lb b/src/mainboard/via/epia-cn/Options.lb index 77ec483dd7..b80f2a3277 100644 --- a/src/mainboard/via/epia-cn/Options.lb +++ b/src/mainboard/via/epia-cn/Options.lb @@ -19,83 +19,83 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_PCI_ROM_RUN uses CONFIG_CONSOLE_VGA uses CONFIG_MAX_PCI_BUSES -uses TTYS0_BAUD +uses CONFIG_TTYS0_BAUD uses CONFIG_VIDEO_MB uses CONFIG_IOAPIC -default ROM_SIZE = 512 * 1024 +default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_IOAPIC = 0 default CONFIG_VIDEO_MB = 32 default CONFIG_CONSOLE_SERIAL8250 = 1 default CONFIG_PCI_ROM_RUN = 0 default CONFIG_CONSOLE_VGA = 0 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_HARD_RESET = 0 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 9 -default HAVE_ACPI_TABLES = 0 -default HAVE_OPTION_TABLE = 1 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = ROM_SIZE -default USE_FALLBACK_IMAGE = 1 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 9 +default CONFIG_HAVE_ACPI_TABLES = 0 +default CONFIG_HAVE_OPTION_TABLE = 1 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE +default CONFIG_USE_FALLBACK_IMAGE = 1 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector" +default CONFIG_HOSTCC = "gcc" ## ## Set this to the max PCI bus number you would ever use for PCI config I/O. diff --git a/src/mainboard/via/epia-cn/irq_tables.c b/src/mainboard/via/epia-cn/irq_tables.c index fc63ff1c32..2b6607b1ec 100644 --- a/src/mainboard/via/epia-cn/irq_tables.c +++ b/src/mainboard/via/epia-cn/irq_tables.c @@ -24,7 +24,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x11 << 3) | 0x0, /* Interrupt router device */ 0xc20, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/via/epia-m/Config.lb b/src/mainboard/via/epia-m/Config.lb index 228a0265ba..8bb51b639b 100644 --- a/src/mainboard/via/epia-m/Config.lb +++ b/src/mainboard/via/epia-m/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -13,11 +13,11 @@ arch i386 end ## driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o object vgabios.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object fadt.o object dsdt.o object acpi_tables.o @@ -27,22 +27,22 @@ end ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -56,7 +56,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -78,7 +78,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/via/epia-m/Options.lb b/src/mainboard/via/epia-m/Options.lb index 5781156c49..aeb9521c0b 100644 --- a/src/mainboard/via/epia-m/Options.lb +++ b/src/mainboard/via/epia-m/Options.lb @@ -1,54 +1,54 @@ -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_PCI_ROM_RUN uses CONFIG_CONSOLE_VGA uses CONFIG_MAX_PCI_BUSES -uses TTYS0_BAUD +uses CONFIG_TTYS0_BAUD -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -59,12 +59,12 @@ default CONFIG_CONSOLE_VGA=0 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Use TSC for udelay. @@ -75,60 +75,60 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=5 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=5 ## ## Build code to load acpi tables ## -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Set this to the max PCI bus number you @@ -139,8 +139,8 @@ default HOSTCC="gcc" ## default CONFIG_MAX_PCI_BUSES = 5 -default MAXIMUM_CONSOLE_LOGLEVEL=8 -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 default CONFIG_CONSOLE_SERIAL8250=1 diff --git a/src/mainboard/via/epia-m700/Config.lb b/src/mainboard/via/epia-m700/Config.lb index 70f669ef62..33006e4963 100644 --- a/src/mainboard/via/epia-m700/Config.lb +++ b/src/mainboard/via/epia-m700/Config.lb @@ -18,16 +18,16 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o driver wakeup.o -if HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_MP_TABLE object mptable.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_ACPI_TABLES object fadt.o object dsdt.o # object ssdt.o @@ -35,23 +35,23 @@ if HAVE_ACPI_TABLES end # These lines maybe noused. makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" - action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" - action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end -if USE_DCACHE_RAM +if CONFIG_USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" action "perl -e 's/.rodata/.rom.data/g' -pi $@" action "perl -e 's/.text/.section .rom.text/g' -pi $@" end @@ -65,7 +65,7 @@ ldscript /northbridge/via/vx800/romstrap.lds mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -81,11 +81,11 @@ end mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM +if CONFIG_USE_DCACHE_RAM mainboardinit cpu/via/car/cache_as_ram.inc end -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds # failover.inc need definition in cpu_reset.inc, but we do not include # cpu_reset.inc,so ... @@ -94,7 +94,7 @@ end # mainboardinit cpu/x86/fpu/enable_fpu.inc # mainboardinit cpu/x86/mmx/enable_mmx.inc -if USE_DCACHE_RAM +if CONFIG_USE_DCACHE_RAM if CONFIG_USE_INIT initobject cache_as_ram_auto.o else diff --git a/src/mainboard/via/epia-m700/Options.lb b/src/mainboard/via/epia-m700/Options.lb index 5fe9240778..c0fc338df5 100644 --- a/src/mainboard/via/epia-m700/Options.lb +++ b/src/mainboard/via/epia-m700/Options.lb @@ -18,59 +18,59 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses HAVE_ACPI_TABLES -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_PCI_ROM_RUN uses CONFIG_CONSOLE_VGA uses CONFIG_MAX_PCI_BUSES -uses TTYS0_BAUD +uses CONFIG_TTYS0_BAUD uses CONFIG_VIDEO_MB uses CONFIG_IOAPIC ## New options -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT #uses MAX_RAM_SLOTS #uses USB_ENABLE @@ -85,11 +85,11 @@ uses CONFIG_USE_INIT #uses VIACONFIG_VGA_PCI_14 ## New options -default USE_DCACHE_RAM = 1 -default DCACHE_RAM_BASE = 0xffef0000 -# default DCACHE_RAM_BASE = 0xffbf0000 -# default DCACHE_RAM_BASE = 0xfec00000 # HPET may use this. -default DCACHE_RAM_SIZE = 8 * 1024 +default CONFIG_USE_DCACHE_RAM = 1 +default CONFIG_DCACHE_RAM_BASE = 0xffef0000 +# default CONFIG_DCACHE_RAM_BASE = 0xffbf0000 +# default CONFIG_DCACHE_RAM_BASE = 0xfec00000 # HPET may use this. +default CONFIG_DCACHE_RAM_SIZE = 8 * 1024 default CONFIG_USE_INIT = 0 #default MAX_RAM_SLOTS = 2 #default USB_ENABLE = 1 @@ -104,7 +104,7 @@ default CONFIG_USE_INIT = 0 #default VIACONFIG_VGA_PCI_10 = 0xf8000008 #default VIACONFIG_VGA_PCI_14 = 0xfc000000 -default ROM_SIZE = 512 * 1024 +default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_IOAPIC = 1 # Define framebuffer size of VX800's integrated graphics card. @@ -114,27 +114,27 @@ default CONFIG_VIDEO_MB = 64 default CONFIG_CONSOLE_SERIAL8250 = 1 default CONFIG_PCI_ROM_RUN = 0 default CONFIG_CONSOLE_VGA = 0 -default HAVE_FALLBACK_BOOT = 1 -default HAVE_MP_TABLE = 0 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_HARD_RESET = 0 -default HAVE_PIRQ_TABLE = 0 -default IRQ_SLOT_COUNT = 14 -default HAVE_ACPI_TABLES = 1 -default HAVE_OPTION_TABLE = 1 -default ROM_IMAGE_SIZE = 128 * 1024 -default FALLBACK_SIZE = ROM_SIZE -default USE_FALLBACK_IMAGE = 1 -default STACK_SIZE = 16 * 1024 -default HEAP_SIZE = 20 * 1024 -# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_HAVE_PIRQ_TABLE = 0 +default CONFIG_IRQ_SLOT_COUNT = 14 +default CONFIG_HAVE_ACPI_TABLES = 1 +default CONFIG_HAVE_OPTION_TABLE = 1 +default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE +default CONFIG_USE_FALLBACK_IMAGE = 1 +default CONFIG_STACK_SIZE = 16 * 1024 +default CONFIG_HEAP_SIZE = 20 * 1024 +# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC = "gcc" default CONFIG_CBFS = 0 ## diff --git a/src/mainboard/via/epia-m700/acpi_tables.c b/src/mainboard/via/epia-m700/acpi_tables.c index 54480cdff5..709af4b65e 100644 --- a/src/mainboard/via/epia-m700/acpi_tables.c +++ b/src/mainboard/via/epia-m700/acpi_tables.c @@ -43,9 +43,9 @@ extern u8 acpi_sleep_type; /* * These four macros are copied from <arch/smp/mpspec.h>, I have to do this - * since the "default HAVE_MP_TABLE = 0" in Options.lb, and also since + * since the "default CONFIG_HAVE_MP_TABLE = 0" in Options.lb, and also since * mainboard/via/... have no mptable.c (so that I can not set - * HAVE_MP_TABLE = 1) as many other mainboards. + * CONFIG_HAVE_MP_TABLE = 1) as many other mainboards. * So I have to copy these four to here. acpi_fill_madt() needs this. */ #define MP_IRQ_POLARITY_HIGH 0x1 diff --git a/src/mainboard/via/epia-m700/cache_as_ram_auto.c b/src/mainboard/via/epia-m700/cache_as_ram_auto.c index 82683a5bdc..de5acb90bd 100644 --- a/src/mainboard/via/epia-m700/cache_as_ram_auto.c +++ b/src/mainboard/via/epia-m700/cache_as_ram_auto.c @@ -708,7 +708,7 @@ void amd64_main(unsigned long bist) * around CLEAR_FIRST_1M_RAM and #include "cpu/x86/car/cache_as_ram_post.c". * The CLEAR_FIRST_1M_RAM seems to make cpu/x86/car/cache_as_ram_post.c stop * at somewhere, and cpu/x86/car/cache_as_ram_post.c do not cache my - * $XIP_ROM_BASE+SIZE area. + * $CONFIG_XIP_ROM_BASE+SIZE area. * * Use #include "cpu/via/car/cache_as_ram_post.c". This version post.c have * some diff with x86-version. @@ -772,10 +772,10 @@ cpu_reset_x: #include "cpu/via/car/cache_as_ram_post.c" /* #include "cpu/x86/car/cache_as_ram_post.c" */ __asm__ volatile ( - /* Set new esp *//* before _RAMBASE */ + /* Set new esp *//* before CONFIG_RAMBASE */ "subl %0, %%ebp\n\t" "subl %0, %%esp\n\t":: - "a" ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE) - _RAMBASE) + "a" ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - CONFIG_RAMBASE) ); { diff --git a/src/mainboard/via/epia-m700/irq_tables.c b/src/mainboard/via/epia-m700/irq_tables.c index cb841bf1e4..817b4d6130 100644 --- a/src/mainboard/via/epia-m700/irq_tables.c +++ b/src/mainboard/via/epia-m700/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x11 << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0xc20, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/via/epia/Config.lb b/src/mainboard/via/epia/Config.lb index 47b957608a..40d88f943e 100644 --- a/src/mainboard/via/epia/Config.lb +++ b/src/mainboard/via/epia/Config.lb @@ -1,5 +1,5 @@ -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -13,29 +13,29 @@ arch i386 end ## driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -49,7 +49,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -71,7 +71,7 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end @@ -132,7 +132,7 @@ chip northbridge/via/vt8601 irq 0x70 = 1 irq 0x72 = 12 end - register "com1" = "{TTYS0_BAUD}" + register "com1" = "{CONFIG_TTYS0_BAUD}" end device pnp 2e.6 off end # CIR device pnp 2e.7 off end # GAME_MIDI_GIPO1 diff --git a/src/mainboard/via/epia/Options.lb b/src/mainboard/via/epia/Options.lb index 6e4856c543..dd1bfb0753 100644 --- a/src/mainboard/via/epia/Options.lb +++ b/src/mainboard/via/epia/Options.lb @@ -1,70 +1,70 @@ -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CBFS -uses DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET uses CONFIG_UDELAY_IO uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY # logging -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL # logging -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 +default CONFIG_TTYS0_BAUD=115200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -73,17 +73,17 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## ## use io based udelay function @@ -96,49 +96,49 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=5 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=5 #object irq_tables.o ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" diff --git a/src/mainboard/via/pc2500e/Config.lb b/src/mainboard/via/pc2500e/Config.lb index 405863a456..93ea99b489 100644 --- a/src/mainboard/via/pc2500e/Config.lb +++ b/src/mainboard/via/pc2500e/Config.lb @@ -18,40 +18,40 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_MP_TABLE object mptable.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_ACPI_TABLES object fadt.o object dsdt.o object acpi_tables.o end makerule ./failover.E - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -61,7 +61,7 @@ end mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end diff --git a/src/mainboard/via/pc2500e/Options.lb b/src/mainboard/via/pc2500e/Options.lb index c19f2cd529..ee217383e5 100644 --- a/src/mainboard/via/pc2500e/Options.lb +++ b/src/mainboard/via/pc2500e/Options.lb @@ -20,97 +20,97 @@ uses CONFIG_SMP uses CONFIG_CBFS -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_PCI_ROM_RUN uses CONFIG_CONSOLE_VGA uses CONFIG_MAX_PCI_BUSES -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_VIDEO_MB uses CONFIG_IOAPIC -default ROM_SIZE = 512 * 1024 -default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = ROM_SIZE +default CONFIG_ROM_SIZE = 512 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE default CONFIG_IOAPIC = 0 default CONFIG_VIDEO_MB = 32 default CONFIG_CONSOLE_SERIAL8250 = 1 default CONFIG_PCI_ROM_RUN = 0 default CONFIG_CONSOLE_VGA = 0 -default HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_FALLBACK_BOOT = 1 default CONFIG_SMP = 1 -default HAVE_MP_TABLE = 1 +default CONFIG_HAVE_MP_TABLE = 1 default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default HAVE_HARD_RESET = 0 -default HAVE_PIRQ_TABLE = 1 -default IRQ_SLOT_COUNT = 10 -default HAVE_ACPI_TABLES = 0 -default HAVE_OPTION_TABLE = 1 -default USE_FALLBACK_IMAGE = 1 -default MAINBOARD_VENDOR = "VIA" -default MAINBOARD_PART_NUMBER = "pc2500e" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0xaa51 -default STACK_SIZE = 8 * 1024 -default HEAP_SIZE = 16 * 1024 -# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 1 -default _RAMBASE = 0x00004000 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 10 +default CONFIG_HAVE_ACPI_TABLES = 0 +default CONFIG_HAVE_OPTION_TABLE = 1 +default CONFIG_USE_FALLBACK_IMAGE = 1 +default CONFIG_MAINBOARD_VENDOR = "VIA" +default CONFIG_MAINBOARD_PART_NUMBER = "pc2500e" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0xaa51 +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 1 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 -default CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector" -default HOSTCC = "gcc" +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector" +default CONFIG_HOSTCC = "gcc" default CONFIG_MAX_PCI_BUSES = 3 default CONFIG_CONSOLE_SERIAL8250 = 1 -default TTYS0_BAUD = 115200 -default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 -default MAXIMUM_CONSOLE_LOGLEVEL = 9 -default DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 # diff --git a/src/mainboard/via/pc2500e/auto.c b/src/mainboard/via/pc2500e/auto.c index dbc6720607..f11dacd778 100644 --- a/src/mainboard/via/pc2500e/auto.c +++ b/src/mainboard/via/pc2500e/auto.c @@ -65,7 +65,7 @@ static void main(unsigned long bist) /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - it8716f_enable_serial(SERIAL_DEV, TTYS0_BASE); + it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/via/pc2500e/irq_tables.c b/src/mainboard/via/pc2500e/irq_tables.c index a9f39ac54d..71d7ba0ef8 100644 --- a/src/mainboard/via/pc2500e/irq_tables.c +++ b/src/mainboard/via/pc2500e/irq_tables.c @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x11 << 3) | 0x0, /* Interrupt router device */ 0x828, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/mainboard/via/vt8454c/Config.lb b/src/mainboard/via/vt8454c/Config.lb index 534f910b19..9860ba6676 100644 --- a/src/mainboard/via/vt8454c/Config.lb +++ b/src/mainboard/via/vt8454c/Config.lb @@ -19,8 +19,8 @@ ## MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## @@ -35,20 +35,20 @@ arch i386 end driver mainboard.o -if HAVE_MP_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object fadt.o object acpi_tables.o makerule dsdt.c - depends "$(MAINBOARD)/dsdt.dsl" - action "iasl -p dsdt -tc $(MAINBOARD)/dsdt.dsl" + depends "$(CONFIG_MAINBOARD)/dsdt.dsl" + action "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl" action "mv dsdt.hex dsdt.c" end object ./dsdt.o @@ -58,8 +58,8 @@ end ## Romcc output ## makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -75,7 +75,7 @@ ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where coreboot is entered) ## -if USE_FALLBACK_IMAGE +if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else diff --git a/src/mainboard/via/vt8454c/Options.lb b/src/mainboard/via/vt8454c/Options.lb index 3f1bdb768b..d9ba74c01b 100644 --- a/src/mainboard/via/vt8454c/Options.lb +++ b/src/mainboard/via/vt8454c/Options.lb @@ -19,57 +19,57 @@ ## MA 02110-1301 USA ## -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses IRQ_SLOT_COUNT -uses HAVE_ACPI_TABLES -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE -uses HAVE_LOW_TABLES - -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_HAVE_LOW_TABLES + +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_COMPRESS uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE +uses CONFIG_PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE uses CONFIG_CBFS # compiler specifics -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY # Console specifics -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 @@ -81,19 +81,19 @@ uses CONFIG_IOAPIC uses CONFIG_GDB_STUB -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_PRINTK_IN_CAR -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xffef0000 -#default DCACHE_RAM_BASE=0xffbf0000 -#default DCACHE_RAM_BASE=0xfec00000 -default DCACHE_RAM_SIZE=0x8000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xffef0000 +#default CONFIG_DCACHE_RAM_BASE=0xffbf0000 +#default CONFIG_DCACHE_RAM_BASE=0xfec00000 +default CONFIG_DCACHE_RAM_SIZE=0x8000 default CONFIG_USE_PRINTK_IN_CAR=1 ### @@ -105,7 +105,7 @@ default CONFIG_CONSOLE_VGA=0 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Use TSC for udelay. @@ -116,34 +116,34 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## ## Build code to reset the motherboard from linuxBIOS ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=15 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=15 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to load acpi tables ## -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Build code to fill in tables both in low and high memory ## -default HAVE_LOW_TABLES=1 +default CONFIG_HAVE_LOW_TABLES=1 ## @@ -156,36 +156,36 @@ default CONFIG_IOAPIC=1 ### LinuxBIOS layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = ROM_IMAGE_SIZE +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CONFIG_CROSS_COMPILE="" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Set this to the max PCI bus number you @@ -209,21 +209,21 @@ default CONFIG_GDB_STUB=0 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ## Select the coreboot loglevel @@ -235,13 +235,13 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=5 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=5 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5 # # CBFS diff --git a/src/mainboard/via/vt8454c/irq_tables.c b/src/mainboard/via/vt8454c/irq_tables.c index 40d1ebb691..fffce3170d 100644 --- a/src/mainboard/via/vt8454c/irq_tables.c +++ b/src/mainboard/via/vt8454c/irq_tables.c @@ -24,7 +24,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT, /* There can be total 15 devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* There can be total 15 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x11 << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0xc20, /* IRQs devoted exclusively to PCI usage */ diff --git a/src/northbridge/amd/amdfam10/Config.lb b/src/northbridge/amd/amdfam10/Config.lb index 4f84115d77..f217fcdd3c 100644 --- a/src/northbridge/amd/amdfam10/Config.lb +++ b/src/northbridge/amd/amdfam10/Config.lb @@ -17,19 +17,19 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -uses AGP_APERTURE_SIZE -uses HAVE_ACPI_TABLES -uses HAVE_HIGH_TABLES +uses CONFIG_AGP_APERTURE_SIZE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_HIGH_TABLES -default AGP_APERTURE_SIZE=0x4000000 -default HAVE_HIGH_TABLES=1 +default CONFIG_AGP_APERTURE_SIZE=0x4000000 +default CONFIG_HAVE_HIGH_TABLES=1 config chip.h driver northbridge.o driver misc_control.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object amdfam10_acpi.o makerule ssdt.c depends "$(TOP)/src/northbridge/amd/amdfam10/ssdt.dsl" diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index d3fb11e349..4cca443716 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -958,9 +958,9 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #ifdef __ROMCC__ #if NODE_NUMS==64 - #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CBB,(CDB+x),fn)):(PCI_DEV((CBB-1),(CDB+x-32),fn))) + #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) #else - #define NODE_PCI(x, fn) PCI_DEV(CBB,(CDB+x),fn) + #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) #endif #endif @@ -1025,7 +1025,7 @@ struct nodes_info_t { //#define MEM_CS_COPY 1 #define MEM_CS_COPY NODE_NUMS -#if MEM_TRAIN_SEQ == 0 +#if CONFIG_MEM_TRAIN_SEQ == 0 #define DQS_DELAY_COPY NODE_NUMS #else // #define DQS_DELAY_COPY 1 diff --git a/src/northbridge/amd/amdfam10/amdfam10_acpi.c b/src/northbridge/amd/amdfam10/amdfam10_acpi.c index 4651b17157..f902d6ee98 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_acpi.c +++ b/src/northbridge/amd/amdfam10/amdfam10_acpi.c @@ -134,7 +134,7 @@ unsigned long acpi_fill_slit(unsigned long current) /* fill the first 8 byte with that num */ /* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */ - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); u8 *ln = sysinfox->ln; @@ -190,7 +190,7 @@ void update_ssdt(void *ssdt) u8 *CBST; u8 *CBBX; u8 *CBS2; - u8 *CBB2; + u8 *CONFIG_CBB2; int i; @@ -208,7 +208,7 @@ void update_ssdt(void *ssdt) HCDN = ssdt+0x57a; //+5 will be next HCDN CBBX = ssdt+0x61f; // CBST = ssdt+0x626; - CBB2 = ssdt+0x62d; // + CONFIG_CBB2 = ssdt+0x62d; // CBS2 = ssdt+0x634; for(i=0;i<HC_NUMS;i++) { @@ -245,9 +245,9 @@ void update_ssdt(void *ssdt) int_to_stream(0x20202020, HCDN + i*5); } - *CBBX = (u8)(CBB); + *CBBX = (u8)(CONFIG_CBB); - if(CBB == 0xff) { + if(CONFIG_CBB == 0xff) { *CBST = (u8) (0x0f); } else { if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0 @@ -258,12 +258,12 @@ void update_ssdt(void *ssdt) } } - if((CBB == 0xff) && (sysconf.nodes>32)) { + if((CONFIG_CBB == 0xff) && (sysconf.nodes>32)) { *CBS2 = 0x0f; - *CBB2 = (u8)(CBB-1); + *CONFIG_CBB2 = (u8)(CONFIG_CBB-1); } else { *CBS2 = 0x00; - *CBB2 = 0x00; + *CONFIG_CBB2 = 0x00; } } diff --git a/src/northbridge/amd/amdfam10/amdfam10_conf.c b/src/northbridge/amd/amdfam10/amdfam10_conf.c index f7c6a3d3be..cd958c5216 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_conf.c +++ b/src/northbridge/amd/amdfam10/amdfam10_conf.c @@ -33,12 +33,12 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) device_t dev; struct dram_base_mask_t d; #if defined(__ROMCC__) - dev = PCI_DEV(CBB, CDB, 1); + dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); #else dev = __f1_dev[0]; #endif -#if EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT == 1 // I will use ext space only for simple pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8] d.mask = pci_read_config32(dev, 0x114); // enable is bit 0 @@ -65,7 +65,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes) { u32 i; device_t dev; -#if EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT == 1 // I will use ext space only for simple u32 d_base_i, d_base_d, d_mask_i, d_mask_d; d_base_i = nodeid | (0<<28); @@ -94,7 +94,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes) dev = __f1_dev[i]; #endif -#if EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT == 1 // I will use ext space only for simple pci_write_config32(dev, 0x110, d_base_i); pci_write_config32(dev, 0x114, d_base_d); //[47:27] at [28:8]; @@ -232,7 +232,7 @@ static u32 get_one_DCT(struct mem_info *meminfo) return one_DCT; } #endif -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes) { @@ -316,7 +316,7 @@ static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes) #endif -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) @@ -388,7 +388,7 @@ static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, busn_min>>=segbit; busn_max>>=segbit; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT if(ht_c_index < 4) { #endif tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24); @@ -400,7 +400,7 @@ static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, #endif pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg); } -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT return; } @@ -429,7 +429,7 @@ static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 i; device_t dev; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif for(i=0; i<nodes; i++) { @@ -440,7 +440,7 @@ static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, #endif pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); } -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT return; } @@ -458,7 +458,7 @@ static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, } -#if PCI_BUS_SEGN_BITS +#if CONFIG_PCI_BUS_SEGN_BITS static u32 check_segn(device_t dev, u32 segbusn, u32 nodes, sys_info_conf_t *sysinfo) { @@ -488,7 +488,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 tempreg; device_t dev; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif /* io range allocation */ @@ -510,7 +510,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, #endif pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); } -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT return; } @@ -541,7 +541,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, { u32 i; device_t dev; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif /* io range allocation */ @@ -554,7 +554,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0); pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0); } -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT return; } // : if hc_c_index > 3, We should use io_min, io_max to clear extend space @@ -592,7 +592,7 @@ static void re_set_all_config_map_reg(u32 nodes, u32 segbit, pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); } } -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT u32 j; // clear the extend space for(j = 0; j< nodes; j++) { @@ -624,7 +624,7 @@ static u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) tempreg = 3 | ((nodeid & 0xf) <<4) | ((nodeid & 0x30)<<(12-4)) | (linkn<<8); for(ht_c_index=0;ht_c_index<4; ht_c_index++) { - reg = pci_read_config32(PCI_DEV(CBB, CDB, 1), 0xe0 + ht_c_index * 4); + reg = pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), 0xe0 + ht_c_index * 4); if(((reg & 0xffff) == 0x0000)) { /*found free*/ break; } @@ -660,7 +660,7 @@ static void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, static void set_BusSegmentEn(u32 node, u32 segbit) { -#if PCI_BUS_SEGN_BITS +#if CONFIG_PCI_BUS_SEGN_BITS u32 dword; device_t dev; @@ -715,12 +715,12 @@ static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 io_min, u32 io_max) { u32 val; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT if(reg!=0x110) { #endif /* io range allocation */ index = (reg-0xc0)>>3; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT } else { index+=4; } @@ -740,12 +740,12 @@ static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max) { u32 val; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT if(reg!=0x110) { #endif /* io range allocation */ index = (reg-0x80)>>3; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT } else { index+=8; } @@ -767,7 +767,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 i; u32 tempreg; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT if(reg!=0x110) { #endif /* io range allocation */ @@ -789,7 +789,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, #endif for(i=0; i<sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT return; } @@ -816,7 +816,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 i; u32 tempreg; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT if(reg!=0x110) { #endif /* io range allocation */ @@ -826,7 +826,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); for(i=0; i<sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT return; } diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index a8b93b1818..b0aee4bccc 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -34,7 +34,7 @@ static void print_debug_addr(const char *str, void *val) static void print_debug_pci_dev(u32 dev) { -#if PCI_BUS_SEGN_BITS==0 +#if CONFIG_PCI_BUS_SEGN_BITS==0 printk_debug("PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); #else printk_debug("PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index 43774ded3e..b1c21f2dd3 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -21,7 +21,7 @@ // mmconf is not ready yet static void set_bsp_node_CHtExtNodeCfgEn(void) { -#if EXT_RT_TBL_SUPPORT == 1 +#if CONFIG_EXT_RT_TBL_SUPPORT == 1 u32 dword; dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68); dword |= (1<<27) | (1<<25); @@ -34,14 +34,14 @@ static void set_bsp_node_CHtExtNodeCfgEn(void) /* CHtExtAddrEn */ pci_io_write_config32(PCI_DEV(0, 0x18, 0), 0x68, dword); - // CPU on bus 0xff and 0xfe now. For now on we can use CBB and CDB. + // CPU on bus 0xff and 0xfe now. For now on we can use CONFIG_CBB and CONFIG_CDB. #endif } static void enumerate_ht_chain(void) { -#if HT_CHAIN_UNITID_BASE != 0 -/* HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), +#if CONFIG_HT_CHAIN_UNITID_BASE != 0 +/* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */ /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. @@ -50,16 +50,16 @@ static void enumerate_ht_chain(void) * links needs to be programed to point at bus 0. */ unsigned next_unitid, last_unitid = 0; -#if HT_CHAIN_END_UNITID_BASE != 0x20 +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 // let't record the device of last ht device, So we can set the - // Unitid to HT_CHAIN_END_UNITID_BASE + // Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE unsigned real_last_unitid = 0; u8 real_last_pos = 0; int ht_dev_num = 0; // except host_bridge u8 end_used = 0; #endif - next_unitid = HT_CHAIN_UNITID_BASE; + next_unitid = CONFIG_HT_CHAIN_UNITID_BASE; do { u32 id; u8 hdr_type, pos; @@ -99,10 +99,10 @@ static void enumerate_ht_chain(void) unsigned ctrl, ctrl_off; device_t devx; -#if HT_CHAIN_END_UNITID_BASE != 0x20 +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if(next_unitid>=0x18) { if(!end_used) { - next_unitid = HT_CHAIN_END_UNITID_BASE; + next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; } else { goto out; @@ -112,7 +112,7 @@ static void enumerate_ht_chain(void) real_last_pos = pos; ht_dev_num++ ; #endif - #if HT_CHAIN_END_UNITID_BASE == 0 + #if CONFIG_HT_CHAIN_END_UNITID_BASE == 0 if (!next_unitid) goto out; #endif @@ -161,12 +161,12 @@ static void enumerate_ht_chain(void) } while(last_unitid != next_unitid); out: ; -#if HT_CHAIN_END_UNITID_BASE != 0x20 - if((ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used) { +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + if((ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { u16 flags; flags = pci_io_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; - flags |= HT_CHAIN_END_UNITID_BASE & 0x1f; + flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; pci_io_write_config16(PCI_DEV(0, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags); } #endif diff --git a/src/northbridge/amd/amdfam10/get_pci1234.c b/src/northbridge/amd/amdfam10/get_pci1234.c index 1217a8be6b..f6a196aabf 100644 --- a/src/northbridge/amd/amdfam10/get_pci1234.c +++ b/src/northbridge/amd/amdfam10/get_pci1234.c @@ -49,7 +49,7 @@ * reset HC_POSSIBLE_NUM and update ssdt.dsl (hcdn, hclk) * * Put all the possible ht node/link to the list tp pci1234[] in get_bus_conf.c - * on MB dir. Also, don't forget to increase the ACPI_SSDTX_NUM etc if you have + * on MB dir. Also, don't forget to increase the CONFIG_ACPI_SSDTX_NUM etc if you have * too much SSDT. How about co-processor on socket 1 on 2 way system. * or socket 2, and socket3 on 4 way system? treat that as one hc too! * diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 634fec53ce..a321a656d2 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -59,7 +59,7 @@ static void mcf3_read_resources(device_t dev) pci_dev_read_resources(dev); /* If we are not the first processor don't allocate the gart apeture */ - if (dev->path.pci.devfn != PCI_DEVFN(CDB, 3)) { + if (dev->path.pci.devfn != PCI_DEVFN(CONFIG_CDB, 3)) { return; } @@ -69,7 +69,7 @@ static void mcf3_read_resources(device_t dev) if (iommu) { /* Add a Gart apeture resource */ resource = new_resource(dev, 0x94); - resource->size = iommu?AGP_APERTURE_SIZE:1; + resource->size = iommu?CONFIG_AGP_APERTURE_SIZE:1; resource->align = log2(resource->size); resource->gran = log2(resource->size); resource->limit = 0xffffffff; /* 4G */ diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 6a9504ccc1..fa7cb6db00 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -42,7 +42,7 @@ #include "amdfam10.h" -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 #include <cpu/amd/model_10xxx_rev.h> #endif @@ -60,13 +60,13 @@ device_t get_node_pci(u32 nodeid, u32 fn) { #if NODE_NUMS == 64 if(nodeid<32) { - return dev_find_slot(CBB, PCI_DEVFN(CDB + nodeid, fn)); + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); } else { - return dev_find_slot(CBB-1, PCI_DEVFN(CDB + nodeid - 32, fn)); + return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); } #else - return dev_find_slot(CBB, PCI_DEVFN(CDB + nodeid, fn)); + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); #endif } @@ -83,7 +83,7 @@ static void get_fx_devs(void) __f4_dev[i] = get_node_pci(i, 4); } if (!__f1_dev[0]) { - printk_err("Cannot find %02x:%02x.1", CBB, CDB); + printk_err("Cannot find %02x:%02x.1", CONFIG_CBB, CONFIG_CDB); die("Cannot go on\n"); } } @@ -113,14 +113,14 @@ static u32 amdfam10_nodeid(device_t dev) #if NODE_NUMS == 64 unsigned busn; busn = dev->bus->secondary; - if(busn != CBB) { - return (dev->path.pci.devfn >> 3) - CDB + 32; + if(busn != CONFIG_CBB) { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; } else { - return (dev->path.pci.devfn >> 3) - CDB; + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; } #else - return (dev->path.pci.devfn >> 3) - CDB; + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; #endif } @@ -156,7 +156,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, u32 busn = max&0xff; u32 max_devfn; -#if HT3_SUPPORT==1 +#if CONFIG_HT3_SUPPORT==1 if(is_sublink1) { u32 regpos; u32 reg; @@ -187,7 +187,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, */ ht_c_index = get_ht_c_index(nodeid, link, &sysconf); -#if EXT_CONF_SUPPORT == 0 +#if CONFIG_EXT_CONF_SUPPORT == 0 if(ht_c_index>=4) return max; #endif @@ -196,12 +196,12 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, * so we set the subordinate bus number to 0xff for the moment. */ -#if SB_HT_CHAIN_ON_BUS0 > 0 +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 // first chain will on bus 0 if((nodeid == 0) && (sblink==link)) { // actually max is 0 here min_bus = max; } - #if SB_HT_CHAIN_ON_BUS0 > 1 + #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 // second chain will be on 0x40, third 0x80, forth 0xc0 // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0 // >4 will use more segments, We can have 16 segmment and every segment have 256 bus, For that case need the kernel support mmio pci config. @@ -295,9 +295,9 @@ static u32 amdfam10_scan_chains(device_t dev, u32 max) // Put sb chain in bus 0 -#if SB_HT_CHAIN_ON_BUS0 > 0 +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 if(nodeid==0) { - #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) offset_unitid = 1; #endif max = amdfam10_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 @@ -305,18 +305,18 @@ static u32 amdfam10_scan_chains(device_t dev, u32 max) #endif -#if PCI_BUS_SEGN_BITS +#if CONFIG_PCI_BUS_SEGN_BITS max = check_segn(dev, max, sysconf.nodes, &sysconf); #endif for(link = 0; link < dev->links; link++) { -#if SB_HT_CHAIN_ON_BUS0 > 0 +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 if( (nodeid == 0) && (sblink == link) ) continue; //already done #endif offset_unitid = 0; - #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) + #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 if((nodeid == 0) && (sblink == link)) #endif offset_unitid = 1; @@ -434,7 +434,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) resource = amdfam10_find_iopair(dev, nodeid, link); if (resource) { u32 align; -#if EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT == 1 if((resource->index & 0x1fff) == 0x1110) { // ext align = 8; } @@ -464,7 +464,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) IORESOURCE_MEM | IORESOURCE_PREFETCH, IORESOURCE_MEM | IORESOURCE_PREFETCH); -#if EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT == 1 if((resource->index & 0x1fff) == 0x1110) { // ext normalize_resource(resource); } @@ -485,7 +485,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) IORESOURCE_MEM | IORESOURCE_PREFETCH, IORESOURCE_MEM); -#if EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT == 1 if((resource->index & 0x1fff) == 0x1110) { // ext normalize_resource(resource); } @@ -774,7 +774,7 @@ static u32 find_pci_tolm(struct bus *bus, u32 tolm) #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH) #endif -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned hole_startk; @@ -786,7 +786,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) struct hw_mem_hole_info mem_hole; int i; - mem_hole.hole_startk = HW_MEM_HOLE_SIZEK; + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; for (i = 0; i < sysconf.nodes; i++) { @@ -840,7 +840,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int i) u32 hole_sizek; u32 one_DCT; - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct mem_info *meminfo; meminfo = &sysinfox->meminfo[i]; @@ -911,7 +911,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int i) #endif -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -926,7 +926,7 @@ static void pci_domain_set_resources(device_t dev) u32 pci_tolm; int i, idx; u32 link; -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; u32 reset_memhole = 1; #endif @@ -1003,7 +1003,7 @@ static void pci_domain_set_resources(device_t dev) /* Round the mmio hold to 64M */ mmio_basek &= ~((64*1024) - 1); -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* if the hw mem hole is already set in raminit stage, here we will compare * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will * use hole_basek as mmio_basek and we don't need to reset hole. @@ -1023,7 +1023,7 @@ static void pci_domain_set_resources(device_t dev) if(reset_memhole) { if(mem_hole.node_id!=-1) { - /* We need to select HW_MEM_HOLE_SIZEK for raminit, it can not + /* We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too! We need to reset our Mem Hole, because We want more big HOLE than we already set @@ -1033,7 +1033,7 @@ static void pci_domain_set_resources(device_t dev) disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); } - #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 + #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1 // We need to double check if the mmio_basek is valid for hole // setting, if it is equal to basek, we need to decrease it some resource_t basek_pri; @@ -1089,7 +1089,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; @@ -1100,9 +1100,9 @@ static void pci_domain_set_resources(device_t dev) #endif } #if CONFIG_AMDMCT == 0 - #if HW_MEM_HOLE_SIZEK != 0 + #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) { - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct mem_info *meminfo; meminfo = &sysinfox->meminfo[i]; sizek += hoist_memory(mmio_basek,i, get_one_DCT(meminfo), sysconf.nodes); @@ -1122,7 +1122,7 @@ static void pci_domain_set_resources(device_t dev) } ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); if (i==0 && high_tables_base==0) { @@ -1150,7 +1150,7 @@ static u32 pci_domain_scan_bus(device_t dev, u32 max) for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } -#if EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT == 1 // all nodes for(i = 0; i< sysconf.nodes; i++) { int index; @@ -1164,7 +1164,7 @@ static u32 pci_domain_scan_bus(device_t dev, u32 max) for(i=0;i<dev->links;i++) { - max = pci_scan_bus(&dev->link[i], PCI_DEVFN(CDB, 0), 0xff, max); + max = pci_scan_bus(&dev->link[i], PCI_DEVFN(CONFIG_CDB, 0), 0xff, max); } /* Tune the hypertransport transaction for best performance. @@ -1197,7 +1197,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, -#if MMCONF_SUPPORT_DEFAULT +#if CONFIG_MMCONF_SUPPORT_DEFAULT .ops_pci_bus = &pci_ops_mmconf, #else .ops_pci_bus = &pci_cf8_conf1, @@ -1228,16 +1228,16 @@ static void sysconf_init(device_t dev) // first node sysconf.bsp_apicid = lapicid(); sysconf.apicid_offset = sysconf.bsp_apicid; -#if (ENABLE_APIC_EXT_ID == 1) +#if (CONFIG_ENABLE_APIC_EXT_ID == 1) if (pci_read_config32(dev, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST)) { sysconf.enabled_apic_ext_id = 1; } - #if (APIC_ID_OFFSET>0) + #if (CONFIG_APIC_ID_OFFSET>0) if(sysconf.enabled_apic_ext_id) { if(sysconf.bsp_apicid == 0) { /* bsp apic id is not changed */ - sysconf.apicid_offset = APIC_ID_OFFSET; + sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET; } else { sysconf.lift_bsp_apicid = 1; } @@ -1281,14 +1281,14 @@ static u32 cpu_bus_scan(device_t dev, u32 max) nb_cfg_54 = read_nb_cfg_54(); -#if CBB - dev_mc = dev_find_slot(0, PCI_DEVFN(CDB, 0)); //0x00 +#if CONFIG_CBB + dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00 if(dev_mc && dev_mc->bus) { printk_debug("%s found", dev_path(dev_mc)); pci_domain = dev_mc->bus->dev; if(pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { printk_debug("\n%s move to ",dev_path(dev_mc)); - dev_mc->bus->secondary = CBB; // move to 0xff + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff printk_debug("%s",dev_path(dev_mc)); } else { @@ -1297,7 +1297,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk_debug("\n"); } - dev_mc = dev_find_slot(CBB, PCI_DEVFN(CDB, 0)); + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); if(!dev_mc) { dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); if (dev_mc && dev_mc->bus) { @@ -1306,7 +1306,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) if(pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { if((pci_domain->links==1) && (pci_domain->link[0].children == dev_mc)) { printk_debug("%s move to ",dev_path(dev_mc)); - dev_mc->bus->secondary = CBB; // move to 0xff + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff printk_debug("%s\n",dev_path(dev_mc)); while(dev_mc){ printk_debug("%s move to ",dev_path(dev_mc)); @@ -1321,9 +1321,9 @@ static u32 cpu_bus_scan(device_t dev, u32 max) #endif - dev_mc = dev_find_slot(CBB, PCI_DEVFN(CDB, 0)); + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); if (!dev_mc) { - printk_err("%02x:%02x.0 not found", CBB, CDB); + printk_err("%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); die(""); } @@ -1331,7 +1331,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) nodes = sysconf.nodes; -#if CBB && (NODE_NUMS > 32) +#if CONFIG_CBB && (NODE_NUMS > 32) if(nodes>32) { // need to put node 32 to node 63 to bus 0xfe if(pci_domain->links==1) { pci_domain->links++; // from 1 to 2 @@ -1340,7 +1340,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) pci_domain->link[1].children = 0; printk_debug("%s links increase to %d\n", dev_path(pci_domain), pci_domain->links); } - pci_domain->link[1].secondary = CBB - 1; + pci_domain->link[1].secondary = CONFIG_CBB - 1; } #endif /* Find which cpus are present */ @@ -1351,10 +1351,10 @@ static u32 cpu_bus_scan(device_t dev, u32 max) unsigned busn, devn; struct bus *pbus; - busn = CBB; - devn = CDB+i; + busn = CONFIG_CBB; + devn = CONFIG_CDB+i; pbus = dev_mc->bus; -#if CBB && (NODE_NUMS > 32) +#if CONFIG_CBB && (NODE_NUMS > 32) if(i>=32) { busn--; devn-=32; @@ -1381,7 +1381,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) */ int j; int linknum; -#if HT3_SUPPORT==1 +#if CONFIG_HT3_SUPPORT==1 linknum = 8; #else linknum = 4; @@ -1440,7 +1440,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) if (cpu) { cpu->path.apic.node_id = i; cpu->path.apic.core_id = j; - #if (ENABLE_APIC_EXT_ID == 1) && (APIC_ID_OFFSET>0) + #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET>0) if(sysconf.enabled_apic_ext_id) { if(sysconf.lift_bsp_apicid) { cpu->path.apic.apic_id += sysconf.apicid_offset; diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index e446b54e6b..2d3a621b40 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -21,7 +21,7 @@ #define RAMINIT_H #if 0 -#if DIMM_SUPPORT==0x0110 +#if CONFIG_DIMM_SUPPORT==0x0110 //FBDIMM REG /* each channel can have 8 fbdimm */ #define DIMM_SOCKETS 8 @@ -42,7 +42,7 @@ struct mem_controller { #endif #endif -//#if (DIMM_SUPPORT & 0x00ff)==0x0004 +//#if (CONFIG_DIMM_SUPPORT & 0x00ff)==0x0004 //DDR2 REG and unbuffered : Socket F 1027 and AM3 /* every channel have 4 DDR2 DIMM for socket F * 2 for socket M2/M3 diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index fd967b5ebf..3ea22c5e4c 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -84,7 +84,7 @@ int mctRead_SPD(u32 smaddr, u32 reg) void mctSMBhub_Init(u32 node) { - struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); struct mem_controller *ctrl = &( sysinfo->ctrl[node] ); activate_spd_rom(ctrl); } @@ -93,7 +93,7 @@ void mctSMBhub_Init(u32 node) void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node) { int j; - struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); struct mem_controller *ctrl = &( sysinfo->ctrl[node] ); for(j=0;j<DIMM_SOCKETS;j++) { diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c index 389d8e60a9..69869bf48c 100644 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ b/src/northbridge/amd/amdfam10/reset_test.c @@ -43,7 +43,7 @@ static u32 cpu_init_detected(u8 nodeid) static u32 bios_reset_detected(void) { u32 htic; - htic = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), HT_INIT_CONTROL); + htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); } @@ -51,7 +51,7 @@ static u32 bios_reset_detected(void) static u32 cold_reset_detected(void) { u32 htic; - htic = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), HT_INIT_CONTROL); + htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); return !(htic & HTIC_ColdR_Detect); } @@ -59,7 +59,7 @@ static u32 cold_reset_detected(void) static u32 other_reset_detected(void) // other warm reset not started by BIOS { u32 htic; - htic = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), HT_INIT_CONTROL); + htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && (htic & HTIC_BIOSR_Detect); } @@ -91,7 +91,7 @@ static void set_bios_reset(void) device_t dev; int i; - nodes = ((pci_read_config32(PCI_DEV(CBB, CDB, 0), 0x60) >> 4) & 7) + 1; + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; for(i = 0; i < nodes; i++) { dev = NODE_PCI(i,0); @@ -115,7 +115,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b for(reg = 0xE0; reg < 0xF0; reg += 0x04) { u32 config_map; - config_map = pci_io_read_config32(PCI_DEV(CBB, CDB, 1), reg); + config_map = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), reg); if ((config_map & 3) != 3) { continue; } @@ -126,7 +126,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b } } -#if EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT == 1 // let's check that in extend space // use the nodeid extend space to find out the bus for the linkn u32 tempreg; @@ -157,8 +157,8 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b static u32 get_sblk(void) { u32 reg; - /* read PCI_DEV(CBB,CDB,0) 0x64 bit [8:9] to find out SbLink m */ - reg = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), 0x64); + /* read PCI_DEV(CONFIG_CBB,CONFIG_CDB,0) 0x64 bit [8:9] to find out SbLink m */ + reg = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x64); return ((reg>>8) & 3) ; } diff --git a/src/northbridge/amd/amdfam10/resourcemap.c b/src/northbridge/amd/amdfam10/resourcemap.c index 49d546861c..4bfe03cf45 100644 --- a/src/northbridge/amd/amdfam10/resourcemap.c +++ b/src/northbridge/amd/amdfam10/resourcemap.c @@ -49,14 +49,14 @@ static void setup_default_resource_map(void) * This field defines the upper address bits of a 40 bit * address that define the end of the DRAM region. */ - PCI_ADDR(CBB, CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CBB, CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CBB, CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CBB, CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CBB, CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CBB, CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CBB, CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ static void setup_default_resource_map(void) * This field defines the upper address bits of a 40-bit * address that define the start of the DRAM region. */ - PCI_ADDR(CBB, CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -129,14 +129,14 @@ static void setup_default_resource_map(void) * address that defines the end of a memory-mapped * I/O region n */ - PCI_ADDR(CBB, CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -165,14 +165,14 @@ static void setup_default_resource_map(void) * address that defines the start of memory-mapped * I/O region i */ - PCI_ADDR(CBB, CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -199,10 +199,10 @@ static void setup_default_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CBB, CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CBB, CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -231,10 +231,10 @@ static void setup_default_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CBB, CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CBB, CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -274,10 +274,10 @@ static void setup_default_resource_map(void) * This field defines the highest bus number in * configuration regin i */ - PCI_ADDR(CBB, CDB, 1, 0xE0), 0x0000FC88, 0xff000003, - PCI_ADDR(CBB, CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, }; u32 max; diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index ce3da289c5..906f155598 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -66,7 +66,7 @@ static u32 get_nodes(void) device_t dev; u32 nodes; - dev = PCI_DEV(CBB, CDB, 0); + dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0); nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) ; #if CONFIG_MAX_PHYSICAL_CPUS > 8 nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3); @@ -116,9 +116,9 @@ void AMD_CB_EventNotify (u8 evtClass, u16 event, u8 *pEventData0) */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u16 link, u8 **List) { - const u8 swaplist[] = { 0xFF, HT_CHAIN_UNITID_BASE, HT_CHAIN_END_UNITID_BASE, 0xFF }; + const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((HT_CHAIN_UNITID_BASE != 0) && (HT_CHAIN_END_UNITID_BASE != 0)) { + if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { printk_debug("AMD_CB_ManualBUIDSwapList()\n"); if ((node == 0) && (link == 0)) { /* BSP SB link */ *List = swaplist; diff --git a/src/northbridge/amd/amdk8/Config.lb b/src/northbridge/amd/amdk8/Config.lb index bb38d7319a..40de82e04d 100644 --- a/src/northbridge/amd/amdk8/Config.lb +++ b/src/northbridge/amd/amdk8/Config.lb @@ -1,22 +1,22 @@ -uses AGP_APERTURE_SIZE -uses HAVE_ACPI_TABLES -uses HAVE_HIGH_TABLES -uses K8_REV_F_SUPPORT +uses CONFIG_AGP_APERTURE_SIZE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_HIGH_TABLES +uses CONFIG_K8_REV_F_SUPPORT -default AGP_APERTURE_SIZE=0x4000000 -default HAVE_HIGH_TABLES=1 +default CONFIG_AGP_APERTURE_SIZE=0x4000000 +default CONFIG_HAVE_HIGH_TABLES=1 config chip.h driver northbridge.o driver misc_control.o -if K8_REV_F_SUPPORT +if CONFIG_K8_REV_F_SUPPORT makerule raminit_test depends "$(TOP)/src/northbridge/amd/amdk8/raminit_test.c" depends "$(TOP)/src/northbridge/amd/amdk8/raminit_f.c" - action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" + action "$(CONFIG_HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" end else @@ -24,13 +24,13 @@ else makerule raminit_test depends "$(TOP)/src/northbridge/amd/amdk8/raminit_test.c" depends "$(TOP)/src/northbridge/amd/amdk8/raminit.c" - action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" + action "$(CONFIG_HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" end end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object amdk8_acpi.o end diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 5af58dea45..f03b93c9b5 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -2,7 +2,7 @@ #define AMDK8_H -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #include "amdk8_f.h" #else #include "amdk8_pre_f.h" diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index d24a83c68f..bb5b2f7dd2 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -88,8 +88,8 @@ #define TRY_HIGH_FIRST 0 #endif -#ifndef K8_HT_FREQ_1G_SUPPORT - #define K8_HT_FREQ_1G_SUPPORT 0 +#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT + #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0 #endif #ifndef K8_HT_CHECK_PENDING_LINK @@ -104,8 +104,8 @@ #define CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED 0 #endif -#ifndef ENABLE_APIC_EXT_ID - #define ENABLE_APIC_EXT_ID 0 +#ifndef CONFIG_ENABLE_APIC_EXT_ID + #define CONFIG_ENABLE_APIC_EXT_ID 0 #endif @@ -161,7 +161,7 @@ static void disable_probes(void) static void enable_apic_ext_id(u8 node) { -#if ENABLE_APIC_EXT_ID==1 +#if CONFIG_ENABLE_APIC_EXT_ID==1 #warning "FIXME Is the right place to enable apic ext id here?" u32 val; @@ -284,8 +284,8 @@ static uint16_t read_freq_cap(device_t dev, uint8_t pos) freq_cap = pci_read_config16(dev, pos); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ -#if K8_HT_FREQ_1G_SUPPORT == 1 - #if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1 + #if CONFIG_K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) #endif { @@ -1591,13 +1591,13 @@ static unsigned verify_dualcore(unsigned nodes) static void coherent_ht_finalize(unsigned nodes) { unsigned node; -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 int rev_a0; #endif #if CONFIG_LOGICAL_CPUS==1 unsigned total_cpus; - if ((!HAVE_OPTION_TABLE) || + if ((!CONFIG_HAVE_OPTION_TABLE) || read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */ total_cpus = verify_dualcore(nodes); } @@ -1613,7 +1613,7 @@ static void coherent_ht_finalize(unsigned nodes) */ print_spew("coherent_ht_finalize\r\n"); -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 rev_a0 = is_cpu_rev_a0(); #endif for (node = 0; node < nodes; node++) { @@ -1644,7 +1644,7 @@ static void coherent_ht_finalize(unsigned nodes) (3 << HTTC_HI_PRI_BYP_CNT_SHIFT); pci_write_config32(dev, HT_TRANSACTION_CONTROL, val); -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 if (rev_a0) { pci_write_config32(dev, 0x94, 0); pci_write_config32(dev, 0xb4, 0); @@ -1664,7 +1664,7 @@ static int apply_cpu_errata_fixes(unsigned nodes) device_t dev; uint32_t cmd; dev = NODE_MC(node); -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 if (is_cpu_pre_c0()) { /* Errata 66 diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c index 4ed376ae07..a445f253c7 100644 --- a/src/northbridge/amd/amdk8/debug.c +++ b/src/northbridge/amd/amdk8/debug.c @@ -91,7 +91,7 @@ static void dump_pci_device(unsigned dev) print_debug("\r\n"); } -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index); static void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) { diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index 6cfecbddf7..bf80ef833e 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -4,8 +4,8 @@ // only for sb ht chain static void enumerate_ht_chain(void) { -#if HT_CHAIN_UNITID_BASE != 0 -/* HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */ +#if CONFIG_HT_CHAIN_UNITID_BASE != 0 +/* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */ /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. * On most boards this just happens. If a cpu has multiple @@ -14,8 +14,8 @@ static void enumerate_ht_chain(void) */ unsigned next_unitid, last_unitid; device_t dev; -#if HT_CHAIN_END_UNITID_BASE != 0x20 - //let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE unsigned real_last_unitid; uint8_t real_last_pos; int ht_dev_num = 0; // except host_bridge @@ -23,7 +23,7 @@ static void enumerate_ht_chain(void) #endif dev = PCI_DEV(0,0,0); - next_unitid = HT_CHAIN_UNITID_BASE; + next_unitid = CONFIG_HT_CHAIN_UNITID_BASE; do { uint32_t id; uint8_t hdr_type, pos; @@ -63,10 +63,10 @@ static void enumerate_ht_chain(void) unsigned ctrl, ctrl_off; device_t devx; -#if HT_CHAIN_END_UNITID_BASE != 0x20 +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if(next_unitid>=0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f. if(!end_used) { - next_unitid = HT_CHAIN_END_UNITID_BASE; + next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; } else { goto out; @@ -126,13 +126,13 @@ static void enumerate_ht_chain(void) out: ; -#if HT_CHAIN_END_UNITID_BASE != 0x20 - if((ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used) { +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + if((ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { uint16_t flags; dev = PCI_DEV(0,real_last_unitid, 0); flags = pci_read_config16(dev, real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; - flags |= HT_CHAIN_END_UNITID_BASE & 0x1f; + flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; pci_write_config16(dev, real_last_pos + PCI_CAP_FLAGS, flags); } #endif diff --git a/src/northbridge/amd/amdk8/exit_from_self.c b/src/northbridge/amd/amdk8/exit_from_self.c index f8c6744ed1..5c7ba00ff9 100644 --- a/src/northbridge/amd/amdk8/exit_from_self.c +++ b/src/northbridge/amd/amdk8/exit_from_self.c @@ -156,7 +156,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl, printk_debug(" done\n"); } -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* init hw mem hole here */ /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */ set_hw_mem_hole(controllers, ctrl); diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c index 85dd403a43..737f33b48d 100644 --- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c +++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c @@ -176,7 +176,7 @@ unsigned node_link_to_bus(unsigned node, unsigned link) * Just put all the possible HT Node/link to the list tp pci1234[] in * src/mainboard/<vendor>/<mainboard>get_bus_conf.c * - * Also don't forget to increase the ACPI_SSDTX_NUM etc (FIXME what else) if + * Also don't forget to increase the CONFIG_ACPI_SSDTX_NUM etc (FIXME what else) if * you have too many SSDTs * * What about co-processor in socket 1 on a 2 way system? Or socket 2 and diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index 74c9f4fe4f..4c30a098e1 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -7,8 +7,8 @@ #include <device/pci_ids.h> #include <device/hypertransport_def.h> -#ifndef K8_HT_FREQ_1G_SUPPORT - #define K8_HT_FREQ_1G_SUPPORT 0 +#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT + #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0 #endif #ifndef RAMINIT_SYSINFO @@ -85,14 +85,14 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid device_t dev; //actually, only for one HT device HT chain, and unitid is 0 -#if HT_CHAIN_UNITID_BASE == 0 +#if CONFIG_HT_CHAIN_UNITID_BASE == 0 if(offset_unitid) { return; } #endif /* Check if is already collapsed */ - if((!offset_unitid) || (offset_unitid && (!((HT_CHAIN_END_UNITID_BASE == 0) && (HT_CHAIN_END_UNITID_BASE <HT_CHAIN_UNITID_BASE))))) { + if((!offset_unitid) || (offset_unitid && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE <CONFIG_HT_CHAIN_UNITID_BASE))))) { uint32_t id; dev = PCI_DEV(bus, 0, 0); id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -154,8 +154,8 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos) /* AMD K8 Unsupported 1Ghz? */ if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) { - #if K8_HT_FREQ_1G_SUPPORT == 1 - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1 + #if CONFIG_K8_REV_F_SUPPORT == 0 if (is_cpu_pre_e0()) { // only E0 later support 1GHz freq_cap &= ~(1 << HT_FREQ_1000Mhz); } @@ -303,7 +303,7 @@ static int ht_optimize_link( return needs_reset; } -#if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) +#if (CONFIG_USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) #if RAMINIT_SYSINFO == 1 static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo); @@ -425,7 +425,7 @@ static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned o static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid) #endif { - //even HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link + //even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link uint8_t next_unitid, last_unitid; unsigned uoffs; @@ -434,8 +434,8 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of int reset_needed = 0; #endif -#if HT_CHAIN_END_UNITID_BASE != 0x20 - //let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE unsigned real_last_unitid; uint8_t real_last_pos; int ht_dev_num = 0; @@ -443,7 +443,7 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of #endif uoffs = PCI_HT_HOST_OFFS; - next_unitid = (offset_unitid) ? HT_CHAIN_UNITID_BASE:1; + next_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE:1; do { uint32_t id; @@ -500,11 +500,11 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of } -#if HT_CHAIN_END_UNITID_BASE != 0x20 +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if(offset_unitid) { if(next_unitid>= (bus ? 0x20:0x18) ) { if(!end_used) { - next_unitid = HT_CHAIN_END_UNITID_BASE; + next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; } else { goto out; @@ -560,18 +560,18 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of } while (last_unitid != next_unitid ); -#if HT_CHAIN_END_UNITID_BASE != 0x20 +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 out: #endif end_of_chain: ; -#if HT_CHAIN_END_UNITID_BASE != 0x20 - if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used ) { +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) { uint16_t flags; int i; flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; - flags |= HT_CHAIN_END_UNITID_BASE & 0x1f; + flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags); #if RAMINIT_SYSINFO == 1 @@ -580,11 +580,11 @@ end_of_chain: ; { struct link_pair_st *link_pair = &sysinfo->link_pair[i]; if(link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) { - link_pair->udev = PCI_DEV(bus, HT_CHAIN_END_UNITID_BASE, 0); + link_pair->udev = PCI_DEV(bus, CONFIG_HT_CHAIN_END_UNITID_BASE, 0); continue; } if(link_pair->dev == PCI_DEV(bus, real_last_unitid, 0)) { - link_pair->dev = PCI_DEV(bus, HT_CHAIN_END_UNITID_BASE, 0); + link_pair->dev = PCI_DEV(bus, CONFIG_HT_CHAIN_END_UNITID_BASE, 0); } } #endif @@ -605,7 +605,7 @@ static int ht_setup_chain(device_t udev, unsigned upos) #endif { unsigned offset_unitid = 0; -#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) +#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) offset_unitid = 1; #endif @@ -618,7 +618,7 @@ static int ht_setup_chain(device_t udev, unsigned upos) /* Make certain the HT bus is not enumerated */ ht_collapse_previous_enumeration(0, 0); -#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) +#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) offset_unitid = 1; #endif @@ -666,11 +666,11 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num) uint8_t val; unsigned devn = 1; - #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) + #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 if(i==0) // to check if it is sb ht chain #endif - devn = HT_CHAIN_UNITID_BASE; + devn = CONFIG_HT_CHAIN_UNITID_BASE; #endif reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); @@ -781,7 +781,7 @@ static int ht_setup_chains(uint8_t ht_c_num) unsigned regpos; uint32_t dword; uint8_t busn; - #if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) + #if (CONFIG_USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) unsigned bus; #endif unsigned offset_unitid = 0; @@ -799,8 +799,8 @@ static int ht_setup_chains(uint8_t ht_c_num) pci_write_config32( PCI_DEV(0, devpos,0), regpos , dword); - #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) + #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 if(i==0) // to check if it is sb ht chain #endif offset_unitid = 1; @@ -818,7 +818,7 @@ static int ht_setup_chains(uint8_t ht_c_num) reset_needed |= ht_setup_chainx(udev,upos,busn, offset_unitid); //all not #endif - #if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) + #if (CONFIG_USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) /* You can use use this in romcc, because there is function call in romcc, recursive will kill you */ bus = busn; // we need 32 bit #if RAMINIT_SYSINFO == 1 diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index 1090d61b07..7c35082705 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -53,7 +53,7 @@ static void mcf3_read_resources(device_t dev) if (iommu) { /* Add a Gart apeture resource */ resource = new_resource(dev, 0x94); - resource->size = iommu?AGP_APERTURE_SIZE:1; + resource->size = iommu?CONFIG_AGP_APERTURE_SIZE:1; resource->align = log2(resource->size); resource->gran = log2(resource->size); resource->limit = 0xffffffff; /* 4G */ @@ -121,7 +121,7 @@ static void misc_control_init(struct device *dev) cmd = pci_read_config32(dev, 0x44); cmd |= (1<<6) | (1<<25); pci_write_config32(dev, 0x44, cmd ); -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 if (is_cpu_pre_c0()) { /* Errata 58 diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index b6c0f7c8c0..c51bc21b03 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -155,12 +155,12 @@ static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned lin * We have no idea how many busses are behind this bridge yet, * so we set the subordinate bus number to 0xff for the moment. */ -#if SB_HT_CHAIN_ON_BUS0 > 0 +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 // first chain will on bus 0 if((nodeid == 0) && (sblink==link)) { // actually max is 0 here min_bus = max; } - #if SB_HT_CHAIN_ON_BUS0 > 1 + #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 // second chain will be on 0x40, third 0x80, forth 0xc0 else { min_bus = ((max>>6) + 1) * 0x40; @@ -257,8 +257,8 @@ static unsigned int amdk8_scan_chains(device_t dev, unsigned int max) if(nodeid==0) { sblink = (pci_read_config32(dev, 0x64)>>8) & 3; -#if SB_HT_CHAIN_ON_BUS0 > 0 - #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) offset_unitid = 1; #endif max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 @@ -266,12 +266,12 @@ static unsigned int amdk8_scan_chains(device_t dev, unsigned int max) } for(link = 0; link < dev->links; link++) { -#if SB_HT_CHAIN_ON_BUS0 > 0 +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 if( (nodeid == 0) && (sblink == link) ) continue; //already done #endif offset_unitid = 0; - #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) + #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 if((nodeid == 0) && (sblink == link)) #endif offset_unitid = 1; @@ -743,7 +743,7 @@ static uint32_t find_pci_tolm(struct bus *bus) #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH) #endif -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned hole_startk; @@ -755,7 +755,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) struct hw_mem_hole_info mem_hole; int i; - mem_hole.hole_startk = HW_MEM_HOLE_SIZEK; + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; for (i = 0; i < FX_DEVS; i++) { @@ -893,7 +893,7 @@ static uint32_t hoist_memory(unsigned long hole_startk, int i) } #endif -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -907,7 +907,7 @@ static void pci_domain_set_resources(device_t dev) unsigned long mmio_basek; uint32_t pci_tolm; int i, idx; -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; unsigned reset_memhole = 1; #endif @@ -991,12 +991,12 @@ static void pci_domain_set_resources(device_t dev) mmio_basek &= ~((64*1024) - 1); #endif -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole. * otherwise We reset the hole to the mmio_basek */ - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) { #endif @@ -1010,13 +1010,13 @@ static void pci_domain_set_resources(device_t dev) //mmio_basek = 3*1024*1024; // for debug to meet boundary if(reset_memhole) { - if(mem_hole.node_id!=-1) { // We need to select HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....! + if(mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....! // We need to reset our Mem Hole, because We want more big HOLE than we already set //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); } - #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 + #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1 //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some uint32_t basek_pri; for (i = 0; i < FX_DEVS; i++) { @@ -1037,7 +1037,7 @@ static void pci_domain_set_resources(device_t dev) #endif } -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 } // is_cpu_pre_e0 #endif @@ -1077,7 +1077,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; @@ -1087,9 +1087,9 @@ static void pci_domain_set_resources(device_t dev) } #endif } - #if HW_MEM_HOLE_SIZEK != 0 + #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 if(!is_cpu_pre_e0() ) #endif sizek += hoist_memory(mmio_basek,i); @@ -1111,7 +1111,7 @@ static void pci_domain_set_resources(device_t dev) if (sizek) ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); if (i==0 && high_tables_base==0) { @@ -1211,7 +1211,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max) sysconf.enabled_apic_ext_id = 1; if(bsp_apicid == 0) { /* bsp apic id is not changed */ - sysconf.apicid_offset = APIC_ID_OFFSET; + sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET; } else { sysconf.lift_bsp_apicid = 1; @@ -1263,7 +1263,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max) // That is the typical case if(j == 0 ){ - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 e0_later_single_core = is_e0_later_in_bsp(i); // single core #else e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index e55f4b898f..83ae83032a 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -553,7 +553,7 @@ static void hw_enable_ecc(const struct mem_controller *ctrl) if (nbcap & NBCAP_ECC) { dcl |= DCL_DimmEccEn; } - if (HAVE_OPTION_TABLE && + if (CONFIG_HAVE_OPTION_TABLE && read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { dcl &= ~DCL_DimmEccEn; } @@ -867,7 +867,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) * so I can see my rom chip and other I/O devices. */ if (tom_k >= 0x003f0000) { -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 if (hole_startk != 0) { tom_k = hole_startk; } else @@ -1104,7 +1104,7 @@ static void order_dimms(const struct mem_controller *ctrl) { unsigned long tom_k, base_k; - if ((!HAVE_OPTION_TABLE) || + if ((!CONFIG_HAVE_OPTION_TABLE) || read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) { tom_k = interleave_chip_selects(ctrl); } else { @@ -1408,7 +1408,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; bios_cycle_time = min_cycle_times[ read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)]; - if (HAVE_OPTION_TABLE && bios_cycle_time > min_cycle_time) { + if (CONFIG_HAVE_OPTION_TABLE && bios_cycle_time > min_cycle_time) { min_cycle_time = bios_cycle_time; } min_latency = 2; @@ -2111,7 +2111,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) return; } -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i) { int ii; @@ -2170,10 +2170,10 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) uint32_t hole_startk; int i; - hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK; + hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK; printk_spew("Handling memory hole at 0x%08x (default)\n", hole_startk); -#if HW_MEM_HOLE_SIZE_AUTO_INC == 1 +#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1 /* We need to double check if hole_startk is valid. * If it is equal to the dram base address in K (base_k), * we need to decrease it. @@ -2328,7 +2328,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) printk_debug(" done\n"); } -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 // init hw mem hole here /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */ if (!is_cpu_pre_e0()) diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 37398a8d23..0ad5e4758a 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -882,11 +882,11 @@ static void set_dimm_size(const struct mem_controller *ctrl, if (base0) { uint32_t dword; uint32_t ClkDis0; -#if CPU_SOCKET_TYPE == 0x10 /* L1 */ +#if CONFIG_CPU_SOCKET_TYPE == 0x10 /* L1 */ ClkDis0 = DTL_MemClkDis0; -#elif CPU_SOCKET_TYPE == 0x11 /* AM2 */ +#elif CONFIG_CPU_SOCKET_TYPE == 0x11 /* AM2 */ ClkDis0 = DTL_MemClkDis0_AM2; -#elif CPU_SOCKET_TYPE == 0x12 /* S1G1 */ +#elif CONFIG_CPU_SOCKET_TYPE == 0x12 /* S1G1 */ ClkDis0 = DTL_MemClkDis0_S1g1; #endif @@ -1066,7 +1066,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) * so I can see my rom chip and other I/O devices. */ if (tom_k >= 0x003f0000) { -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 if (hole_startk != 0) { tom_k = hole_startk; } else @@ -1452,7 +1452,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i u8 common_cl; /* S1G1 and AM2 sockets are Mod64BitMux capable. */ -#if CPU_SOCKET_TYPE == 0x11 || CPU_SOCKET_TYPE == 0x12 +#if CONFIG_CPU_SOCKET_TYPE == 0x11 || CONFIG_CPU_SOCKET_TYPE == 0x12 u8 mux_cap = 1; #else u8 mux_cap = 0; @@ -2341,7 +2341,7 @@ static void set_DramTerm(const struct mem_controller *ctrl, } -#if DIMM_SUPPORT == 0x0204 +#if CONFIG_DIMM_SUPPORT == 0x0204 odt = 0x2; /* 150 ohms */ #endif @@ -2512,7 +2512,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * long dimm_mask = meminfo->dimm_mask & 0x0f; -#if DIMM_SUPPORT==0x0104 /* DDR2 and REG */ +#if CONFIG_DIMM_SUPPORT==0x0104 /* DDR2 and REG */ /* for REG DIMM */ dword = 0x00111222; dwordx = 0x002f0000; @@ -2536,7 +2536,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * #endif -#if DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */ +#if CONFIG_DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */ dword = 0x00111222; dwordx = 0x002F2F00; @@ -2576,7 +2576,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * } #endif -#if DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */ +#if CONFIG_DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */ /* for UNBUF DIMM */ dword = 0x00111222; dwordx = 0x002f2f00; @@ -2658,7 +2658,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * printk_raminit("\tAddr Timing= %08x\n", dwordx); #endif -#if (DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ +#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ if (SlowAccessMode) { set_SlowAccessMode(ctrl); } @@ -2689,7 +2689,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * static void set_RDqsEn(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) { -#if CPU_SOCKET_TYPE==0x10 +#if CONFIG_CPU_SOCKET_TYPE==0x10 //only need to set for reg and x8 uint32_t dch; @@ -2880,7 +2880,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, #include "raminit_f_dqs.c" -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i) { int ii; @@ -2941,10 +2941,10 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) uint32_t hole_startk; int i; - hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK; + hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK; printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk); -#if HW_MEM_HOLE_SIZE_AUTO_INC == 1 +#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1 /* We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some */ uint32_t basek_pri; @@ -3143,7 +3143,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, printk_debug(" done\n"); } -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* init hw mem hole here */ /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */ set_hw_mem_hole(controllers, ctrl); @@ -3175,7 +3175,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, } -#if MEM_TRAIN_SEQ == 0 +#if CONFIG_MEM_TRAIN_SEQ == 0 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 dqs_timing(controllers, ctrl, tsc0, sysinfo); #else @@ -3183,7 +3183,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, #endif #else -#if MEM_TRAIN_SEQ == 2 +#if CONFIG_MEM_TRAIN_SEQ == 2 /* need to enable mtrr, so dqs training could access the test address */ setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k); #endif @@ -3195,18 +3195,18 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, dqs_timing(i, &ctrl[i], sysinfo, 1); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 break; // only train the first node with ram #endif } -#if MEM_TRAIN_SEQ == 2 +#if CONFIG_MEM_TRAIN_SEQ == 2 clear_mtrr_dqs(sysinfo->tom2_k); #endif #endif -#if MEM_TRAIN_SEQ != 1 +#if CONFIG_MEM_TRAIN_SEQ != 1 wait_all_core0_mem_trained(sysinfo); #endif diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index e58a63053d..2764e606be 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -78,7 +78,7 @@ static unsigned Get_MCTSysAddr(const struct mem_controller *ctrl, unsigned cs_i uint32_t mem_base; unsigned nodeid = ctrl->node_id; -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 uint32_t hole_reg; #endif @@ -91,7 +91,7 @@ static unsigned Get_MCTSysAddr(const struct mem_controller *ctrl, unsigned cs_i mem_base &= 0xffff0000; dword += mem_base; -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 hole_reg = sysinfo->hole_reg[nodeid]; if(hole_reg & 1) { unsigned hole_startk; @@ -855,7 +855,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st //restore SSE2 setting disable_sse2(); -#if MEM_TRAIN_SEQ != 1 +#if CONFIG_MEM_TRAIN_SEQ != 1 /* We need tidy output for type 1 */ printk_debug(" CTLRMaxDelay=%02x\n", CTLRMaxDelay); #endif @@ -1702,7 +1702,7 @@ static unsigned int range_to_mtrr(unsigned int reg, align = max_align; } sizek = 1 << align; -#if MEM_TRAIN_SEQ != 1 +#if CONFIG_MEM_TRAIN_SEQ != 1 printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n", reg, range_startk >>10, sizek >> 10, (type==MTRR_TYPE_UNCACHEABLE)?"UC": @@ -1921,7 +1921,7 @@ static void dqs_restore_MC_NVRAM(unsigned int dev) pci_write_config32(dev, DRAM_CONFIG_HIGH, reg); } -#if MEM_TRAIN_SEQ == 0 +#if CONFIG_MEM_TRAIN_SEQ == 0 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 static void dqs_timing(int controllers, const struct mem_controller *ctrl, tsc_t *tsc0, struct sys_info *sysinfo) #else @@ -2007,7 +2007,7 @@ out: #endif -#if MEM_TRAIN_SEQ > 0 +#if CONFIG_MEM_TRAIN_SEQ > 0 static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info *sysinfo, unsigned v) { @@ -2018,7 +2018,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info if(sysinfo->mem_trained[i] != 0x80) return; -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 //need to enable mtrr, so dqs training could access the test address setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k); #endif @@ -2064,7 +2064,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info } out: -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 clear_mtrr_dqs(sysinfo->tom2_k); #endif @@ -2081,7 +2081,7 @@ out: } #endif -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info *sysinfox) { dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo, 0); // keep the output tidy @@ -2094,7 +2094,7 @@ static void copy_and_run_ap_code_in_car(unsigned ret_addr); static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) { if(coreid) return; // only do it on core0 - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); wait_till_sysinfo_in_ram(); // use pci to get it if(sysinfox->mem_trained[nodeid] == 0x80) { @@ -2105,7 +2105,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid]; memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid], sizeof(struct mem_controller)); #else - memcpy(sysinfo, sysinfox, DCACHE_RAM_GLOBAL_VAR_SIZE); + memcpy(sysinfo, sysinfox, CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); #endif set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's #if CONFIG_AP_CODE_IN_CAR == 0 diff --git a/src/northbridge/amd/gx1/Config.lb b/src/northbridge/amd/gx1/Config.lb index adb96c3c64..18b426d3b9 100644 --- a/src/northbridge/amd/gx1/Config.lb +++ b/src/northbridge/amd/gx1/Config.lb @@ -1,4 +1,4 @@ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index 63cc003df0..2c578d0671 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -126,7 +126,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -174,7 +174,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/amd/gx2/Config.lb b/src/northbridge/amd/gx2/Config.lb index 342dac967c..169db63065 100644 --- a/src/northbridge/amd/gx2/Config.lb +++ b/src/northbridge/amd/gx2/Config.lb @@ -1,7 +1,7 @@ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o object northbridgeinit.o object chipsetinit.o object grphinit.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index bfcef1af47..f3a638ca5a 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -501,7 +501,7 @@ static struct device_operations cpu_bus_ops = { void chipsetInit (void); -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -531,7 +531,7 @@ static void enable_dev(struct device *dev) dev->ops = &pci_domain_ops; pci_set_method(dev); tomk = ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE; -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/amd/lx/Config.lb b/src/northbridge/amd/lx/Config.lb index b9388893ab..340d3df9cb 100644 --- a/src/northbridge/amd/lx/Config.lb +++ b/src/northbridge/amd/lx/Config.lb @@ -1,6 +1,6 @@ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o object northbridgeinit.o object grphinit.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 390c94cf78..c765377054 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -125,7 +125,7 @@ struct msr_defaults { */ void print_conf(void) { -#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR int i; unsigned long iol; msr_t msr; @@ -266,7 +266,7 @@ void print_conf(void) iol = inl(GPIO_MAPPER_X); printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X, iol); -#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR +#endif //CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR } /* todo: add a resource record. We don't do this here because this may be called when @@ -415,7 +415,7 @@ static void ram_resource(device_t dev, unsigned long index, IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -436,7 +436,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 1024, tomk - 1024); // Systop - 1 MB -> KB -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/ibm/cpc710/cpc710_pci.c b/src/northbridge/ibm/cpc710/cpc710_pci.c index 233e119baf..2b6024e5b9 100644 --- a/src/northbridge/ibm/cpc710/cpc710_pci.c +++ b/src/northbridge/ibm/cpc710/cpc710_pci.c @@ -45,7 +45,7 @@ cpc710_pci_init(void) setCPC710_PCI32(CPC710_PCIL0_MSIZE, CPC710_PCI32_MEM_SIZE); setCPC710_PCI32(CPC710_PCIL0_IOSIZE, CPC710_PCI32_IO_SIZE); setCPC710_PCI32(CPC710_PCIL0_SMBAR, CPC710_PCI32_MEM_BASE); - setCPC710_PCI32(CPC710_PCIL0_SIBAR, CPC710_PCI32_IO_BASE); + setCPC710_PCI32(CPC710_PCIL0_SIBAR, CPC710_PCI32CONFIG_IO_BASE); setCPC710_PCI32(CPC710_PCIL0_CTLRW, 0x00000000); setCPC710_PCI32(CPC710_PCIL0_PSSIZE, 0x00000080); setCPC710_PCI32(CPC710_PCIL0_BARPS, 0x00000000); @@ -94,7 +94,7 @@ cpc710_pci_init(void) setCPC710_PCI64(CPC710_PCIL0_MSIZE, CPC710_PCI64_MEM_SIZE); setCPC710_PCI64(CPC710_PCIL0_IOSIZE, CPC710_PCI64_IO_SIZE); setCPC710_PCI64(CPC710_PCIL0_SMBAR, CPC710_PCI64_MEM_BASE); - setCPC710_PCI64(CPC710_PCIL0_SIBAR, CPC710_PCI64_IO_BASE); + setCPC710_PCI64(CPC710_PCIL0_SIBAR, CPC710_PCI64CONFIG_IO_BASE); setCPC710_PCI64(CPC710_PCIL0_CTLRW, 0x02000000); setCPC710_PCI64(CPC710_PCIL0_PSSIZE, 0x00000080); diff --git a/src/northbridge/ibm/cpc710/cpc710_pci.h b/src/northbridge/ibm/cpc710/cpc710_pci.h index 51aaa22049..0b3374ebd4 100644 --- a/src/northbridge/ibm/cpc710/cpc710_pci.h +++ b/src/northbridge/ibm/cpc710/cpc710_pci.h @@ -24,17 +24,17 @@ #ifndef _CPC710_PCI_H_ #define _CPC710_PCI_H_ -#define CPC710_PCI32_CONFIG (PCIC0_CFGADDR & 0xfff00000) +#define CPC710_PCI32_CONFIG (CONFIG_PCIC0_CFGADDR & 0xfff00000) #define CPC710_PCI32_MEM_SIZE 0xf8000000 #define CPC710_PCI32_MEM_BASE 0xc0000000 #define CPC710_PCI32_IO_SIZE 0xf8000000 -#define CPC710_PCI32_IO_BASE 0x80000000 +#define CPC710_PCI32CONFIG_IO_BASE 0x80000000 //#define CPC710_PCI64_CONFIG 0xff400000 //#define CPC710_PCI64_MEM_SIZE 0xf8000000 //#define CPC710_PCI64_MEM_BASE 0xc8000000 //#define CPC710_PCI64_IO_SIZE 0xf8000000 -//#define CPC710_PCI64_IO_BASE 0x88000000 +//#define CPC710_PCI64CONFIG_IO_BASE 0x88000000 #define CPC710_PCIL0_PSEA 0xf6110 #define CPC710_PCIL0_PCIDG 0xf6120 diff --git a/src/northbridge/intel/e7501/Config.lb b/src/northbridge/intel/e7501/Config.lb index 2a8095f692..72e903b9b1 100644 --- a/src/northbridge/intel/e7501/Config.lb +++ b/src/northbridge/intel/e7501/Config.lb @@ -1,7 +1,7 @@ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h object northbridge.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index 7168bf3112..06a68e1e47 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -65,7 +65,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -146,7 +146,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/intel/e7520/Config.lb b/src/northbridge/intel/e7520/Config.lb index 03a78974d4..dbbd3aae24 100644 --- a/src/northbridge/intel/e7520/Config.lb +++ b/src/northbridge/intel/e7520/Config.lb @@ -1,4 +1,4 @@ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o @@ -7,10 +7,10 @@ driver pciexp_porta1.o driver pciexp_portb.o driver pciexp_portc.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 makerule raminit_test depends "$(TOP)/src/northbridge/intel/e7520/raminit_test.c" depends "$(TOP)/src/northbridge/intel/e7520/raminit.c" - action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" + action "$(CONFIG_HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" end diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index f2b2a0f3a0..47e6266aa6 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -76,7 +76,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -169,7 +169,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/intel/e7525/Config.lb b/src/northbridge/intel/e7525/Config.lb index 07930ff434..fc3253d0ff 100644 --- a/src/northbridge/intel/e7525/Config.lb +++ b/src/northbridge/intel/e7525/Config.lb @@ -1,4 +1,4 @@ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o @@ -7,10 +7,10 @@ driver pciexp_porta1.o driver pciexp_portb.o driver pciexp_portc.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 makerule raminit_test depends "$(TOP)/src/northbridge/intel/e7525/raminit_test.c" depends "$(TOP)/src/northbridge/intel/e7525/raminit.c" - action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" + action "$(CONFIG_HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" end diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index 7900129ec2..65404d6bf3 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -76,7 +76,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -169,7 +169,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/intel/i3100/Config.lb b/src/northbridge/intel/i3100/Config.lb index 1534605dc0..6d0fa6f5be 100644 --- a/src/northbridge/intel/i3100/Config.lb +++ b/src/northbridge/intel/i3100/Config.lb @@ -17,11 +17,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o driver pciexp_porta.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 928fe94c73..205e47db50 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -97,7 +97,7 @@ static u32 find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -190,7 +190,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/intel/i440bx/Config.lb b/src/northbridge/intel/i440bx/Config.lb index c9a26b08b3..a27625ee41 100644 --- a/src/northbridge/intel/i440bx/Config.lb +++ b/src/northbridge/intel/i440bx/Config.lb @@ -18,10 +18,10 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 31b5dc0575..34c868e0f3 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -90,7 +90,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -131,7 +131,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/intel/i82810/Config.lb b/src/northbridge/intel/i82810/Config.lb index 04375d89c1..2cc66fc2c0 100644 --- a/src/northbridge/intel/i82810/Config.lb +++ b/src/northbridge/intel/i82810/Config.lb @@ -18,10 +18,10 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 40c8ee0e69..4b3c321963 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -122,7 +122,7 @@ static int translate_i82810_to_mb[] = { /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, }; -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -172,7 +172,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/intel/i82830/Config.lb b/src/northbridge/intel/i82830/Config.lb index 863c867666..c6b7afd3d1 100644 --- a/src/northbridge/intel/i82830/Config.lb +++ b/src/northbridge/intel/i82830/Config.lb @@ -18,11 +18,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o driver vga.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index bf79ecdca1..9f6ba71d41 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -107,7 +107,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -149,7 +149,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 1024, tolmk - 1024); -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/intel/i855gme/Config.lb b/src/northbridge/intel/i855gme/Config.lb index 83edd47783..04634806ab 100644 --- a/src/northbridge/intel/i855gme/Config.lb +++ b/src/northbridge/intel/i855gme/Config.lb @@ -18,10 +18,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h object northbridge.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/i855gme/northbridge.c b/src/northbridge/intel/i855gme/northbridge.c index ec42c6eb73..ad48ee11de 100644 --- a/src/northbridge/intel/i855gme/northbridge.c +++ b/src/northbridge/intel/i855gme/northbridge.c @@ -88,7 +88,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -147,7 +147,7 @@ static void pci_domain_set_resources(device_t dev) /* ram_resource(dev, idx++, 1024, tolmk - 1024); */ ram_resource(dev, idx++, 768, tolmk - 768); -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/intel/i855pm/Config.lb b/src/northbridge/intel/i855pm/Config.lb index 2a8095f692..72e903b9b1 100644 --- a/src/northbridge/intel/i855pm/Config.lb +++ b/src/northbridge/intel/i855pm/Config.lb @@ -1,7 +1,7 @@ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h object northbridge.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/i855pm/northbridge.c b/src/northbridge/intel/i855pm/northbridge.c index 4fbd3b3cec..ce655a9f0d 100644 --- a/src/northbridge/intel/i855pm/northbridge.c +++ b/src/northbridge/intel/i855pm/northbridge.c @@ -66,7 +66,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -114,7 +114,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/intel/i945/Config.lb b/src/northbridge/intel/i945/Config.lb index 72f620e5ba..6b74fbe7c1 100644 --- a/src/northbridge/intel/i945/Config.lb +++ b/src/northbridge/intel/i945/Config.lb @@ -17,9 +17,9 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 config chip.h driver northbridge.o diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 81fd58e07f..b0ddbda7e4 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -93,7 +93,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -177,7 +177,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(&dev->link[0]); -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; @@ -199,7 +199,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, -#if MMCONF_SUPPORT_DEFAULT +#if CONFIG_MMCONF_SUPPORT_DEFAULT .ops_pci_bus = &pci_ops_mmconf, #else .ops_pci_bus = &pci_cf8_conf1, diff --git a/src/northbridge/via/cn700/Config.lb b/src/northbridge/via/cn700/Config.lb index b824a17b75..e79e0e02e1 100644 --- a/src/northbridge/via/cn700/Config.lb +++ b/src/northbridge/via/cn700/Config.lb @@ -18,7 +18,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h @@ -28,4 +28,4 @@ driver northbridge.o driver agp.o driver vga.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index 2d3adf1288..dc421d3e51 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -163,7 +163,7 @@ static u32 find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* maximum size of high tables in KB */ #define HIGH_TABLES_SIZE 64 extern uint64_t high_tables_base, high_tables_size; @@ -206,7 +206,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } -#if HAVE_HIGH_TABLES == 1 +#if CONFIG_HAVE_HIGH_TABLES == 1 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE* 1024; printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c index 6cc885fd4b..3c8fb61ce6 100644 --- a/src/northbridge/via/cn700/vga.c +++ b/src/northbridge/via/cn700/vga.c @@ -49,10 +49,10 @@ static void vga_init(device_t dev) print_debug("Copying BOCHS BIOS to 0xf000\n"); /* - * Copy BOCHS BIOS from 4G-ROM_SIZE-64k (in flash) to 0xf0000 (in RAM) + * Copy BOCHS BIOS from 4G-CONFIG_ROM_SIZE-64k (in flash) to 0xf0000 (in RAM) * This is for compatibility with the VGA ROM's BIOS callbacks. */ - memcpy(0xf0000, (0xffffffff - ROM_SIZE - 0xffff), 0x10000); + memcpy(0xf0000, (0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000); printk_debug("Initializing VGA\n"); diff --git a/src/northbridge/via/cx700/Config.lb b/src/northbridge/via/cx700/Config.lb index 44299ba729..8f87759bce 100644 --- a/src/northbridge/via/cx700/Config.lb +++ b/src/northbridge/via/cx700/Config.lb @@ -15,7 +15,7 @@ ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h @@ -28,4 +28,4 @@ driver cx700_lpc.o driver cx700_sata.o driver cx700_vga.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index c7bbb8bf85..7c09b9495b 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -87,7 +87,7 @@ static u32 find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* maximum size of high tables in KB */ #define HIGH_TABLES_SIZE 64 extern uint64_t high_tables_base, high_tables_size; @@ -131,7 +131,7 @@ static void pci_domain_set_resources(device_t dev) tolmk -= 1024; // TOP 1M SM Memory } -#if HAVE_HIGH_TABLES == 1 +#if CONFIG_HAVE_HIGH_TABLES == 1 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE* 1024; printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); diff --git a/src/northbridge/via/vt8601/Config.lb b/src/northbridge/via/vt8601/Config.lb index 9cf0154983..1523f98cfd 100644 --- a/src/northbridge/via/vt8601/Config.lb +++ b/src/northbridge/via/vt8601/Config.lb @@ -1,7 +1,7 @@ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index b1e1c494cb..b58b8edf88 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -101,7 +101,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* maximum size of high tables in KB */ #define HIGH_TABLES_SIZE 64 extern uint64_t high_tables_base, high_tables_size; @@ -147,7 +147,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } -#if HAVE_HIGH_TABLES == 1 +#if CONFIG_HAVE_HIGH_TABLES == 1 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE* 1024; printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); diff --git a/src/northbridge/via/vt8623/Config.lb b/src/northbridge/via/vt8623/Config.lb index 9cf0154983..1523f98cfd 100644 --- a/src/northbridge/via/vt8623/Config.lb +++ b/src/northbridge/via/vt8623/Config.lb @@ -1,7 +1,7 @@ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 70ba59c1d2..41c472b568 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -253,7 +253,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* maximum size of high tables in KB */ #define HIGH_TABLES_SIZE 64 extern uint64_t high_tables_base, high_tables_size; @@ -299,7 +299,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } -#if HAVE_HIGH_TABLES == 1 +#if CONFIG_HAVE_HIGH_TABLES == 1 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE* 1024; printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); diff --git a/src/northbridge/via/vx800/examples/cache_as_ram_auto.c b/src/northbridge/via/vx800/examples/cache_as_ram_auto.c index 8f53975f89..1580d48acb 100644 --- a/src/northbridge/via/vx800/examples/cache_as_ram_auto.c +++ b/src/northbridge/via/vx800/examples/cache_as_ram_auto.c @@ -563,7 +563,7 @@ the following code is copied from src\mainboard\tyan\s2735\cache_as_ram_auto.c Only the code around CLEAR_FIRST_1M_RAM is changed. I remove all the code around CLEAR_FIRST_1M_RAM and #include "cpu/x86/car/cache_as_ram_post.c" the CLEAR_FIRST_1M_RAM seems to make cpu/x86/car/cache_as_ram_post.c stop at somewhere, -and cpu/x86/car/cache_as_ram_post.c do not cache my $XIP_ROM_BASE+SIZE area. +and cpu/x86/car/cache_as_ram_post.c do not cache my $CONFIG_XIP_ROM_BASE+SIZE area. So,I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c have some diff withx86-version */ @@ -621,11 +621,11 @@ So,I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c have #include "cpu/via/car/cache_as_ram_post.c" //#include "cpu/x86/car/cache_as_ram_post.c" __asm__ volatile ( - /* set new esp *//* before _RAMBASE */ + /* set new esp *//* before CONFIG_RAMBASE */ "subl %0, %%ebp\n\t" "subl %0, %%esp\n\t":: - "a" ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE) - - _RAMBASE) + "a" ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - + CONFIG_RAMBASE) ); { diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c index d4e7e40dec..644284eef7 100644 --- a/src/northbridge/via/vx800/examples/chipset_init.c +++ b/src/northbridge/via/vx800/examples/chipset_init.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME == 1 #include <arch/acpi.h> #endif #include <../northbridge/via/vx800/vx800.h> @@ -620,7 +620,7 @@ void init_VIA_chipset(void) void hardwaremain(int boot_complete) { struct lb_memory *lb_mem; -#if HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME == 1 void *wake_vec; #endif diff --git a/src/northbridge/via/vx800/romstrap.lds b/src/northbridge/via/vx800/romstrap.lds index 2e300c95a5..66159e3a1c 100644 --- a/src/northbridge/via/vx800/romstrap.lds +++ b/src/northbridge/via/vx800/romstrap.lds @@ -19,7 +19,7 @@ */ SECTIONS { - . = (_ROMBASE + ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start); + . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start); .romstrap (.): { *(.romstrap) } diff --git a/src/pc80/mc146818rtc.c b/src/pc80/mc146818rtc.c index 0baa389c1f..592a0a52f1 100644 --- a/src/pc80/mc146818rtc.c +++ b/src/pc80/mc146818rtc.c @@ -138,7 +138,7 @@ void rtc_init(int invalid) printk_debug("RTC Init\n"); -#if HAVE_OPTION_TABLE +#if CONFIG_HAVE_OPTION_TABLE /* See if there has been a CMOS power problem. */ x = cmos_read(RTC_VALID); cmos_invalid = !(x & RTC_VRT); @@ -179,10 +179,10 @@ void rtc_init(int invalid) /* Setup the frequency it operates at */ cmos_write(RTC_FREQ_SELECT_DEFAULT, RTC_FREQ_SELECT); -#if HAVE_OPTION_TABLE +#if CONFIG_HAVE_OPTION_TABLE /* See if there is a LB CMOS checksum error */ - checksum_invalid = !rtc_checksum_valid(LB_CKS_RANGE_START, - LB_CKS_RANGE_END,LB_CKS_LOC); + checksum_invalid = !rtc_checksum_valid(CONFIG_LB_CKS_RANGE_START, + CONFIG_LB_CKS_RANGE_END,CONFIG_LB_CKS_LOC); if(checksum_invalid) printk_debug("Invalid CMOS LB checksum\n"); @@ -196,7 +196,7 @@ void rtc_init(int invalid) } -#if USE_OPTION_TABLE == 1 +#if CONFIG_USE_OPTION_TABLE == 1 /* This routine returns the value of the requested bits input bit = bit count from the beginning of the cmos image length = number of bits to include in the value @@ -259,9 +259,9 @@ int get_option(void *dest, char *name) if(get_cmos_value(ce->bit, ce->length, dest)) return(-3); - if(!rtc_checksum_valid(LB_CKS_RANGE_START, - LB_CKS_RANGE_END,LB_CKS_LOC)) + if(!rtc_checksum_valid(CONFIG_LB_CKS_RANGE_START, + CONFIG_LB_CKS_RANGE_END,CONFIG_LB_CKS_LOC)) return(-4); return(0); } -#endif /* USE_OPTION_TABLE */ +#endif /* CONFIG_USE_OPTION_TABLE */ diff --git a/src/pc80/mc146818rtc_early.c b/src/pc80/mc146818rtc_early.c index 2e3d09c8c0..6db9ec8e1a 100644 --- a/src/pc80/mc146818rtc_early.c +++ b/src/pc80/mc146818rtc_early.c @@ -1,11 +1,11 @@ #include <pc80/mc146818rtc.h> #include <part/fallback_boot.h> -#ifndef MAX_REBOOT_CNT -#error "MAX_REBOOT_CNT not defined" +#ifndef CONFIG_MAX_REBOOT_CNT +#error "CONFIG_MAX_REBOOT_CNT not defined" #endif -#if MAX_REBOOT_CNT > 15 -#error "MAX_REBOOT_CNT too high" +#if CONFIG_MAX_REBOOT_CNT > 15 +#error "CONFIG_MAX_REBOOT_CNT too high" #endif static unsigned char cmos_read(unsigned char addr) @@ -44,14 +44,14 @@ static int cmos_chksum_valid(void) unsigned long sum, old_sum; sum = 0; /* Comput the cmos checksum */ - for(addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) { + for(addr = CONFIG_LB_CKS_RANGE_START; addr <= CONFIG_LB_CKS_RANGE_END; addr++) { sum += cmos_read(addr); } sum = (sum & 0xffff) ^ 0xffff; /* Read the stored checksum */ - old_sum = cmos_read(LB_CKS_LOC) << 8; - old_sum |= cmos_read(LB_CKS_LOC+1); + old_sum = cmos_read(CONFIG_LB_CKS_LOC) << 8; + old_sum |= cmos_read(CONFIG_LB_CKS_LOC+1); return sum == old_sum; } @@ -75,7 +75,7 @@ static int do_normal_boot(void) */ byte = cmos_read(RTC_BOOT_BYTE); byte &= 0x0c; - byte |= MAX_REBOOT_CNT << 4; + byte |= CONFIG_MAX_REBOOT_CNT << 4; cmos_write(byte, RTC_BOOT_BYTE); } @@ -89,12 +89,12 @@ static int do_normal_boot(void) /* Properly set the last boot flag */ byte &= 0xfc; - if ((byte >> 4) < MAX_REBOOT_CNT) { + if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { byte |= (1<<1); } /* Are we already at the max count? */ - if ((byte >> 4) < MAX_REBOOT_CNT) { + if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { byte += 1 << 4; /* No, add 1 to the count */ } else { @@ -109,7 +109,7 @@ static int do_normal_boot(void) static unsigned read_option(unsigned start, unsigned size, unsigned def) { -#if USE_OPTION_TABLE == 1 +#if CONFIG_USE_OPTION_TABLE == 1 unsigned byte; byte = cmos_read(start/8); return (byte >> (start & 7U)) & ((1U << size) - 1U); diff --git a/src/pc80/serial.c b/src/pc80/serial.c index d2079d32ab..5136497407 100644 --- a/src/pc80/serial.c +++ b/src/pc80/serial.c @@ -1,27 +1,27 @@ #include <part/fallback_boot.h> /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS #if CONFIG_USE_PRINTK_IN_CAR == 0 @@ -46,7 +46,7 @@ static int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } static void uart_wait_to_tx_byte(void) @@ -57,14 +57,14 @@ static void uart_wait_to_tx_byte(void) static void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } static void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -72,24 +72,24 @@ static void uart_tx_byte(unsigned char data) static void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); -#if USE_OPTION_TABLE == 1 + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); +#if CONFIG_USE_OPTION_TABLE == 1 static const unsigned char divisor[] = { 1,2,3,6,12,24,48,96 }; unsigned ttys0_div, ttys0_index; ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0); ttys0_index &= 7; ttys0_div = divisor[ttys0_index]; - outb(ttys0_div & 0xff, TTYS0_BASE + UART_DLL); - outb(0, TTYS0_BASE + UART_DLM); + outb(ttys0_div & 0xff, CONFIG_TTYS0_BASE + UART_DLL); + outb(0, CONFIG_TTYS0_BASE + UART_DLM); #else - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); #endif - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } #else @@ -98,15 +98,15 @@ static void uart_init(void) extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs); void uart_init(void) { -#if USE_OPTION_TABLE == 1 +#if CONFIG_USE_OPTION_TABLE == 1 static const unsigned char divisor[] = { 1,2,3,6,12,24,48,96 }; unsigned ttys0_div, ttys0_index; ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0); ttys0_index &= 7; ttys0_div = divisor[ttys0_index]; - uart8250_init(TTYS0_BASE, ttys0_div, UART_LCS); + uart8250_init(CONFIG_TTYS0_BASE, ttys0_div, UART_LCS); #else - uart8250_init(TTYS0_BASE, TTYS0_DIV, UART_LCS); + uart8250_init(CONFIG_TTYS0_BASE, CONFIG_TTYS0_DIV, UART_LCS); #endif } #endif diff --git a/src/pc80/usbdebug_direct_serial.c b/src/pc80/usbdebug_direct_serial.c index e795349a22..604294bf1c 100644 --- a/src/pc80/usbdebug_direct_serial.c +++ b/src/pc80/usbdebug_direct_serial.c @@ -3,14 +3,14 @@ static void early_usbdebug_direct_init(void) { struct ehci_debug_info *dbg_info = - (struct ehci_debug_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - sizeof (struct ehci_debug_info)); + (struct ehci_debug_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof (struct ehci_debug_info)); usbdebug_direct_init(EHCI_BAR, EHCI_DEBUG_OFFSET, dbg_info); } void usbdebug_direct_tx_byte(unsigned char data) { struct ehci_debug_info *dbg_info; - dbg_info = (struct ehci_debug_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - sizeof (struct ehci_debug_info)); // in Cache + dbg_info = (struct ehci_debug_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof (struct ehci_debug_info)); // in Cache if (dbg_info->ehci_debug) { dbgp_bulk_write_x(dbg_info, &data, 1); } diff --git a/src/ram/ramtest.c b/src/ram/ramtest.c index b65c11dd34..9f329ef51b 100644 --- a/src/ram/ramtest.c +++ b/src/ram/ramtest.c @@ -1,6 +1,6 @@ static void write_phys(unsigned long addr, unsigned long value) { -#if HAVE_MOVNTI +#if CONFIG_HAVE_MOVNTI asm volatile( "movnti %1, (%0)" : /* outputs */ diff --git a/src/southbridge/amd/amd8111/amd8111_acpi.c b/src/southbridge/amd/amd8111/amd8111_acpi.c index 57c26910f8..9511474062 100644 --- a/src/southbridge/amd/amd8111/amd8111_acpi.c +++ b/src/southbridge/amd/amd8111/amd8111_acpi.c @@ -16,8 +16,8 @@ #define SLOW_CPU_OFF 0 #define SLOW_CPU__ON 1 -#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif @@ -66,7 +66,7 @@ static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) return do_smbus_write_byte(res->base, device, address, val); } -#if HAVE_ACPI_TABLES == 1 +#if CONFIG_HAVE_ACPI_TABLES == 1 unsigned pm_base; #endif @@ -112,7 +112,7 @@ static void acpi_init(struct device *dev) pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5)); /* power on after power fail */ - on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; @@ -140,7 +140,7 @@ static void acpi_init(struct device *dev) (on*12)+(on>>1),(on&1)*5); } -#if HAVE_ACPI_TABLES == 1 +#if CONFIG_HAVE_ACPI_TABLES == 1 pm_base = pci_read_config16(dev, 0x58) & 0xff00; printk_debug("pm_base: 0x%04x\n",pm_base); #endif diff --git a/src/southbridge/amd/cs5530/cs5530_pirq.c b/src/southbridge/amd/cs5530/cs5530_pirq.c index edae7c9ab6..3fb9a74a1e 100644 --- a/src/southbridge/amd/cs5530/cs5530_pirq.c +++ b/src/southbridge/amd/cs5530/cs5530_pirq.c @@ -23,7 +23,7 @@ #include <device/pci.h> #include <device/pci_ids.h> -#if (PIRQ_ROUTE==1 && HAVE_PIRQ_TABLE==1) +#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_HAVE_PIRQ_TABLE==1) void pirq_assign_irqs(const unsigned char pIntAtoD[4]) { device_t pdev; diff --git a/src/southbridge/amd/cs5536/cs5536_pirq.c b/src/southbridge/amd/cs5536/cs5536_pirq.c index b8b4a10b1d..0723253898 100644 --- a/src/southbridge/amd/cs5536/cs5536_pirq.c +++ b/src/southbridge/amd/cs5536/cs5536_pirq.c @@ -23,7 +23,7 @@ #include <device/pci.h> #include <device/pci_ids.h> -#if (PIRQ_ROUTE==1 && HAVE_PIRQ_TABLE==1) +#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_HAVE_PIRQ_TABLE==1) void pirq_assign_irqs(const unsigned char pIntAtoD[4]) { device_t pdev; diff --git a/src/southbridge/amd/sb600/sb600_early_setup.c b/src/southbridge/amd/sb600/sb600_early_setup.c index e63e8e930e..b605b5e3bf 100644 --- a/src/southbridge/amd/sb600/sb600_early_setup.c +++ b/src/southbridge/amd/sb600/sb600_early_setup.c @@ -434,7 +434,7 @@ static void sb600_devices_por_init() /*CIM set this register; but I didn't find its description in RPR. On DBM690T platform, I didn't find different between set and skip this register. - But on Filbert platform, the DEBUG message from serial port on Peanut board can't be displayed + But on Filbert platform, the CONFIG_DEBUG message from serial port on Peanut board can't be displayed after the bit0 of this register is set. pci_write_config8(dev, 0x04, 0x21); */ diff --git a/src/southbridge/amd/sb600/sb600_sm.c b/src/southbridge/amd/sb600/sb600_sm.c index a107d2dfd1..b0f99533a2 100644 --- a/src/southbridge/amd/sb600/sb600_sm.c +++ b/src/southbridge/amd/sb600/sb600_sm.c @@ -36,8 +36,8 @@ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif struct ioapicreg { @@ -164,7 +164,7 @@ static void sm_init(device_t dev) pm_iowrite(0x53, byte); /* power after power fail */ - on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); byte = pm_ioread(0x74); byte &= ~0x03; diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c index dd11810483..2222102170 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c @@ -3,7 +3,7 @@ * by yinghai.lu@amd.com */ -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 static void bcm5785_enable_rom(void) { @@ -42,7 +42,7 @@ static void bcm5785_enable_lpc(void) byte |=(1<<1)|(1<<0); pci_write_config8(dev, 0x48, byte); } -#endif /* USE_FALLBACK_IMAGE == 1 */ +#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ static void bcm5785_enable_wdt_port_cf9(void) diff --git a/src/southbridge/intel/i82801ca/cmos_failover.c b/src/southbridge/intel/i82801ca/cmos_failover.c index 8eb11c3f64..bf35764c19 100644 --- a/src/southbridge/intel/i82801ca/cmos_failover.c +++ b/src/southbridge/intel/i82801ca/cmos_failover.c @@ -4,7 +4,7 @@ static void check_cmos_failed(void) { -#if HAVE_OPTION_TABLE +#if CONFIG_HAVE_OPTION_TABLE uint8_t byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3); if( byte & RTC_BATTERY_DEAD) { @@ -12,7 +12,7 @@ static void check_cmos_failed(void) // clear reboot_bits byte = cmos_read(RTC_BOOT_BYTE); byte &= 0x0c; - byte |= MAX_REBOOT_CNT << 4; + byte |= CONFIG_MAX_REBOOT_CNT << 4; cmos_write(byte, RTC_BOOT_BYTE); } #endif diff --git a/src/southbridge/intel/i82801ca/i82801ca_lpc.c b/src/southbridge/intel/i82801ca/i82801ca_lpc.c index b249438a1f..69535bc016 100644 --- a/src/southbridge/intel/i82801ca/i82801ca_lpc.c +++ b/src/southbridge/intel/i82801ca/i82801ca_lpc.c @@ -15,8 +15,8 @@ #define NMI_OFF 0 -#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif #define MAINBOARD_POWER_OFF 0 @@ -88,7 +88,7 @@ void i82801ca_rtc_init(struct device *dev) { uint32_t dword; int rtc_failed; - int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3); rtc_failed = pmcon3 & RTC_BATTERY_DEAD; diff --git a/src/southbridge/intel/i82801dbm/cmos_failover.c b/src/southbridge/intel/i82801dbm/cmos_failover.c index 9702313f9c..4821fad3d2 100644 --- a/src/southbridge/intel/i82801dbm/cmos_failover.c +++ b/src/southbridge/intel/i82801dbm/cmos_failover.c @@ -10,7 +10,7 @@ static void check_cmos_failed(void) //clear bit 1 and bit 2 byte = cmos_read(RTC_BOOT_BYTE); byte &= 0x0c; - byte |= MAX_REBOOT_CNT << 4; + byte |= CONFIG_MAX_REBOOT_CNT << 4; cmos_write(byte, RTC_BOOT_BYTE); } } diff --git a/src/southbridge/intel/i82801er/cmos_failover.c b/src/southbridge/intel/i82801er/cmos_failover.c index 9702313f9c..4821fad3d2 100644 --- a/src/southbridge/intel/i82801er/cmos_failover.c +++ b/src/southbridge/intel/i82801er/cmos_failover.c @@ -10,7 +10,7 @@ static void check_cmos_failed(void) //clear bit 1 and bit 2 byte = cmos_read(RTC_BOOT_BYTE); byte &= 0x0c; - byte |= MAX_REBOOT_CNT << 4; + byte |= CONFIG_MAX_REBOOT_CNT << 4; cmos_write(byte, RTC_BOOT_BYTE); } } diff --git a/src/southbridge/intel/i82801er/i82801er_lpc.c b/src/southbridge/intel/i82801er/i82801er_lpc.c index 02d474e8d5..fa89469693 100644 --- a/src/southbridge/intel/i82801er/i82801er_lpc.c +++ b/src/southbridge/intel/i82801er/i82801er_lpc.c @@ -18,8 +18,8 @@ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif #define ALL (0xff << 24) @@ -283,7 +283,7 @@ static void lpc_init(struct device *dev) { uint8_t byte; uint32_t value; - int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; /* IO APIC initialization */ value = pci_read_config32(dev, 0xd0); diff --git a/src/southbridge/intel/i82801gx/Config.lb b/src/southbridge/intel/i82801gx/Config.lb index 53186ed293..9ef5f435e8 100644 --- a/src/southbridge/intel/i82801gx/Config.lb +++ b/src/southbridge/intel/i82801gx/Config.lb @@ -17,7 +17,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_SMI_HANDLER +uses CONFIG_HAVE_SMI_HANDLER config chip.h driver i82801gx.o @@ -36,7 +36,7 @@ driver i82801gx_usb_ehci.o object i82801gx_reset.o object i82801gx_watchdog.o -if HAVE_SMI_HANDLER +if CONFIG_HAVE_SMI_HANDLER object i82801gx_smi.o smmobject i82801gx_smihandler.o end diff --git a/src/southbridge/intel/i82801gx/cmos_failover.c b/src/southbridge/intel/i82801gx/cmos_failover.c index 0765404ceb..9eae0cbae7 100644 --- a/src/southbridge/intel/i82801gx/cmos_failover.c +++ b/src/southbridge/intel/i82801gx/cmos_failover.c @@ -31,7 +31,7 @@ static void check_cmos_failed(void) // clear bit 1 and bit 2 byte = cmos_read(RTC_BOOT_BYTE); byte &= 0x0c; - byte |= MAX_REBOOT_CNT << 4; + byte |= CONFIG_MAX_REBOOT_CNT << 4; cmos_write(byte, RTC_BOOT_BYTE); } } diff --git a/src/southbridge/intel/i82801gx/i82801gx_azalia.c b/src/southbridge/intel/i82801gx/i82801gx_azalia.c index fba46bae7c..d0f351413c 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_azalia.c +++ b/src/southbridge/intel/i82801gx/i82801gx_azalia.c @@ -283,7 +283,7 @@ static void azalia_init(struct device *dev) u8 reg8; u32 reg32; -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT // ESD reg32 = pci_mmio_read_config32(dev, 0x134); reg32 &= 0xff00ffff; @@ -314,7 +314,7 @@ static void azalia_init(struct device *dev) reg32 |= (0x80 << 0); // VCi map pci_mmio_write_config32(dev, 0x120, reg32); #else -#error ICH7 Azalia required MMCONF_SUPPORT +#error ICH7 Azalia required CONFIG_MMCONF_SUPPORT #endif /* Set Bus Master */ diff --git a/src/southbridge/intel/i82801gx/i82801gx_lpc.c b/src/southbridge/intel/i82801gx/i82801gx_lpc.c index 241d610bdd..636b975669 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_lpc.c +++ b/src/southbridge/intel/i82801gx/i82801gx_lpc.c @@ -185,7 +185,7 @@ static void i82801gx_power_options(device_t dev) u8 reg8; u16 reg16; - int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; int nmi_option; /* Which state do we want to goto after g3 (power restored)? @@ -296,7 +296,7 @@ static void enable_clock_gating(void) RCBA32(0x341c) = reg32; } -#if HAVE_SMI_HANDLER +#if CONFIG_HAVE_SMI_HANDLER static void i82801gx_lock_smm(struct device *dev) { void smm_lock(void); @@ -401,7 +401,7 @@ static void lpc_init(struct device *dev) setup_i8259(); -#if HAVE_SMI_HANDLER +#if CONFIG_HAVE_SMI_HANDLER i82801gx_lock_smm(dev); #endif diff --git a/src/southbridge/intel/i82801gx/i82801gx_pci.c b/src/southbridge/intel/i82801gx/i82801gx_pci.c index 2bf228b135..bf252ec37e 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_pci.c +++ b/src/southbridge/intel/i82801gx/i82801gx_pci.c @@ -72,11 +72,11 @@ static void ich_pci_dev_enable_resources(struct device *dev) if (dev->on_mainboard && ops && ops->set_subsystem) { printk_debug("%s subsystem <- %02x/%02x\n", dev_path(dev), - MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, - MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); + CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, + CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); ops->set_subsystem(dev, - MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, - MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); + CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, + CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); } command = pci_read_config16(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/i82801gx/i82801gx_pcie.c b/src/southbridge/intel/i82801gx/i82801gx_pcie.c index 6965b30972..d7655c5ea5 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_pcie.c +++ b/src/southbridge/intel/i82801gx/i82801gx_pcie.c @@ -55,7 +55,7 @@ static void pci_init(struct device *dev) reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); pci_write_config32(dev, 0xe1, reg32); -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT /* Set VC0 transaction class */ reg32 = pci_mmio_read_config32(dev, 0x114); reg32 &= 0xffffff00; diff --git a/src/southbridge/intel/i82801xx/cmos_failover.c b/src/southbridge/intel/i82801xx/cmos_failover.c index 2ff632548b..9307f40305 100644 --- a/src/southbridge/intel/i82801xx/cmos_failover.c +++ b/src/southbridge/intel/i82801xx/cmos_failover.c @@ -26,7 +26,7 @@ static void check_cmos_failed(void) //clear bit 1 and bit 2 byte = cmos_read(RTC_BOOT_BYTE); byte &= 0x0c; - byte |= MAX_REBOOT_CNT << 4; + byte |= CONFIG_MAX_REBOOT_CNT << 4; cmos_write(byte, RTC_BOOT_BYTE); } } diff --git a/src/southbridge/nvidia/ck804/Config.lb b/src/southbridge/nvidia/ck804/Config.lb index 481ced004d..36682984e6 100644 --- a/src/southbridge/nvidia/ck804/Config.lb +++ b/src/southbridge/nvidia/ck804/Config.lb @@ -1,4 +1,4 @@ -uses HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_TABLES config chip.h driver ck804.o @@ -15,6 +15,6 @@ driver ck804_pcie.o driver ck804_ht.o object ck804_reset.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object ck804_fadt.o end diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup.c b/src/southbridge/nvidia/ck804/ck804_early_setup.c index 0632197c7c..0d8a630d7a 100644 --- a/src/southbridge/nvidia/ck804/ck804_early_setup.c +++ b/src/southbridge/nvidia/ck804/ck804_early_setup.c @@ -71,13 +71,13 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, #define CK804_CHIP_REV 3 -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE -#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else -#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 +#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 #define CK804B_DEVN_BASE 1 #else #define CK804B_DEVN_BASE CK804_DEVN_BASE diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c index cec869fae5..3e2a69a164 100644 --- a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c +++ b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c @@ -78,13 +78,13 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, #define CK804_CHIP_REV 3 -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE -#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else -#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 +#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 #define CK804B_DEVN_BASE 1 #else #define CK804B_DEVN_BASE CK804_DEVN_BASE diff --git a/src/southbridge/nvidia/ck804/ck804_enable_rom.c b/src/southbridge/nvidia/ck804/ck804_enable_rom.c index fac0da5a3a..8e2b29d61d 100644 --- a/src/southbridge/nvidia/ck804/ck804_enable_rom.c +++ b/src/southbridge/nvidia/ck804/ck804_enable_rom.c @@ -3,10 +3,10 @@ * by yhlu@tyan.com */ -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE -#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else -#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif static void ck804_enable_rom(void) diff --git a/src/southbridge/nvidia/ck804/ck804_lpc.c b/src/southbridge/nvidia/ck804/ck804_lpc.c index db7c29ba84..bb2cf99401 100644 --- a/src/southbridge/nvidia/ck804/ck804_lpc.c +++ b/src/southbridge/nvidia/ck804/ck804_lpc.c @@ -108,8 +108,8 @@ static void setup_ioapic(unsigned long ioapic_base) #define SLOW_CPU_OFF 0 #define SLOW_CPU__ON 1 -#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif static void lpc_common_init(device_t dev) @@ -198,7 +198,7 @@ static void lpc_init(device_t dev) #endif /* power after power fail */ - on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; diff --git a/src/southbridge/nvidia/ck804/id.inc b/src/southbridge/nvidia/ck804/id.inc index 5c0991871b..d8e26ebde4 100644 --- a/src/southbridge/nvidia/ck804/id.inc +++ b/src/southbridge/nvidia/ck804/id.inc @@ -3,12 +3,12 @@ .globl __id_start __id_start: vendor: - .asciz MAINBOARD_VENDOR + .asciz CONFIG_MAINBOARD_VENDOR part: - .asciz MAINBOARD_PART_NUMBER + .asciz CONFIG_MAINBOARD_PART_NUMBER .long __id_end + 0x80 - vendor /* Reverse offset to the vendor ID */ .long __id_end + 0x80 - part /* Reverse offset to the part number */ -.long PAYLOAD_SIZE + ROM_IMAGE_SIZE /* Size of this ROM image */ +.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE /* Size of this ROM image */ .globl __id_end __id_end: diff --git a/src/southbridge/nvidia/ck804/id.lds b/src/southbridge/nvidia/ck804/id.lds index 947a2f0c03..d95b9afcf4 100644 --- a/src/southbridge/nvidia/ck804/id.lds +++ b/src/southbridge/nvidia/ck804/id.lds @@ -1,5 +1,5 @@ SECTIONS { - . = (_ROMBASE + ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start); + . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start); .id (.): { *(.id) } diff --git a/src/southbridge/nvidia/ck804/romstrap.lds b/src/southbridge/nvidia/ck804/romstrap.lds index 5b69024629..f26299f69f 100644 --- a/src/southbridge/nvidia/ck804/romstrap.lds +++ b/src/southbridge/nvidia/ck804/romstrap.lds @@ -1,5 +1,5 @@ SECTIONS { - . = (_ROMBASE + ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start); + . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start); .romstrap (.): { *(.romstrap) } diff --git a/src/southbridge/nvidia/mcp55/Config.lb b/src/southbridge/nvidia/mcp55/Config.lb index f84fde780f..492cd3fdf9 100644 --- a/src/southbridge/nvidia/mcp55/Config.lb +++ b/src/southbridge/nvidia/mcp55/Config.lb @@ -19,7 +19,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_TABLES config chip.h driver mcp55.o @@ -35,6 +35,6 @@ driver mcp55_pci.o driver mcp55_pcie.o driver mcp55_ht.o object mcp55_reset.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object mcp55_fadt.o end diff --git a/src/southbridge/nvidia/mcp55/id.inc b/src/southbridge/nvidia/mcp55/id.inc index ad386e7eee..880ae4b766 100644 --- a/src/southbridge/nvidia/mcp55/id.inc +++ b/src/southbridge/nvidia/mcp55/id.inc @@ -24,12 +24,12 @@ .globl __id_start __id_start: vendor: - .asciz MAINBOARD_VENDOR + .asciz CONFIG_MAINBOARD_VENDOR part: - .asciz MAINBOARD_PART_NUMBER + .asciz CONFIG_MAINBOARD_PART_NUMBER .long __id_end + 0x80 - vendor /* Reverse offset to the vendor id */ .long __id_end + 0x80 - part /* Reverse offset to the part number */ -.long PAYLOAD_SIZE + ROM_IMAGE_SIZE /* Size of this romimage */ +.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE /* Size of this romimage */ .globl __id_end __id_end: diff --git a/src/southbridge/nvidia/mcp55/id.lds b/src/southbridge/nvidia/mcp55/id.lds index 668600a377..53215beb63 100644 --- a/src/southbridge/nvidia/mcp55/id.lds +++ b/src/southbridge/nvidia/mcp55/id.lds @@ -20,7 +20,7 @@ */ SECTIONS { - . = (_ROMBASE + ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start); + . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start); .id (.): { *(.id) } diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c b/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c index 4bf0756f66..78e587e063 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c +++ b/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c @@ -21,10 +21,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if HT_CHAIN_END_UNITID_BASE != 0x20 - #define MCP55_DEVN_BASE HT_CHAIN_END_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else - #define MCP55_DEVN_BASE HT_CHAIN_UNITID_BASE + #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif static void mcp55_enable_rom(void) diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c index 4775d9f516..1c7a26bffc 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c +++ b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c @@ -21,10 +21,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if HT_CHAIN_END_UNITID_BASE != 0x20 - #define MCP55_DEVN_BASE HT_CHAIN_END_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else - #define MCP55_DEVN_BASE HT_CHAIN_UNITID_BASE + #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif #define EHCI_BAR_INDEX 0x10 diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c index 4aff452958..4faaf08fe9 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c +++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c @@ -132,8 +132,8 @@ static void setup_ioapic(unsigned long ioapic_base, int master) #define SLOW_CPU_OFF 0 #define SLOW_CPU__ON 1 -#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif static void lpc_common_init(device_t dev, int master) @@ -181,7 +181,7 @@ static void lpc_init(device_t dev) /* power after power fail */ #if 1 - on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; diff --git a/src/southbridge/nvidia/mcp55/mcp55_smbus.c b/src/southbridge/nvidia/mcp55/mcp55_smbus.c index cff22a3af7..484702ae64 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_smbus.c +++ b/src/southbridge/nvidia/mcp55/mcp55_smbus.c @@ -94,7 +94,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -#if HAVE_ACPI_TABLES == 1 +#if CONFIG_HAVE_ACPI_TABLES == 1 unsigned pm_base; #endif @@ -115,7 +115,7 @@ static void mcp55_sm_read_resources(device_t dev) static void mcp55_sm_init(device_t dev) { -#if HAVE_ACPI_TABLES == 1 +#if CONFIG_HAVE_ACPI_TABLES == 1 struct resource *res; res = find_resource(dev, 0x60); diff --git a/src/southbridge/nvidia/mcp55/romstrap.lds b/src/southbridge/nvidia/mcp55/romstrap.lds index 8a4efd49f1..c45f864152 100644 --- a/src/southbridge/nvidia/mcp55/romstrap.lds +++ b/src/southbridge/nvidia/mcp55/romstrap.lds @@ -20,7 +20,7 @@ */ SECTIONS { - . = (_ROMBASE + ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start); + . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start); .romstrap (.): { *(.romstrap) } diff --git a/src/southbridge/sis/sis966/id.inc b/src/southbridge/sis/sis966/id.inc index ad386e7eee..880ae4b766 100644 --- a/src/southbridge/sis/sis966/id.inc +++ b/src/southbridge/sis/sis966/id.inc @@ -24,12 +24,12 @@ .globl __id_start __id_start: vendor: - .asciz MAINBOARD_VENDOR + .asciz CONFIG_MAINBOARD_VENDOR part: - .asciz MAINBOARD_PART_NUMBER + .asciz CONFIG_MAINBOARD_PART_NUMBER .long __id_end + 0x80 - vendor /* Reverse offset to the vendor id */ .long __id_end + 0x80 - part /* Reverse offset to the part number */ -.long PAYLOAD_SIZE + ROM_IMAGE_SIZE /* Size of this romimage */ +.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE /* Size of this romimage */ .globl __id_end __id_end: diff --git a/src/southbridge/sis/sis966/id.lds b/src/southbridge/sis/sis966/id.lds index 668600a377..53215beb63 100644 --- a/src/southbridge/sis/sis966/id.lds +++ b/src/southbridge/sis/sis966/id.lds @@ -20,7 +20,7 @@ */ SECTIONS { - . = (_ROMBASE + ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start); + . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start); .id (.): { *(.id) } diff --git a/src/southbridge/sis/sis966/romstrap.lds b/src/southbridge/sis/sis966/romstrap.lds index 8a4efd49f1..c45f864152 100644 --- a/src/southbridge/sis/sis966/romstrap.lds +++ b/src/southbridge/sis/sis966/romstrap.lds @@ -20,7 +20,7 @@ */ SECTIONS { - . = (_ROMBASE + ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start); + . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start); .romstrap (.): { *(.romstrap) } diff --git a/src/southbridge/sis/sis966/sis966_enable_rom.c b/src/southbridge/sis/sis966/sis966_enable_rom.c index 0e54694a95..63ef616563 100644 --- a/src/southbridge/sis/sis966/sis966_enable_rom.c +++ b/src/southbridge/sis/sis966/sis966_enable_rom.c @@ -23,10 +23,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE - #define SIS966_DEVN_BASE HT_CHAIN_END_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE + #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else - #define SIS966_DEVN_BASE HT_CHAIN_UNITID_BASE + #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif static void sis966_enable_rom(void) diff --git a/src/southbridge/sis/sis966/sis966_enable_usbdebug_direct.c b/src/southbridge/sis/sis966/sis966_enable_usbdebug_direct.c index 22f82f3ef2..f17a79e6c4 100644 --- a/src/southbridge/sis/sis966/sis966_enable_usbdebug_direct.c +++ b/src/southbridge/sis/sis966/sis966_enable_usbdebug_direct.c @@ -21,10 +21,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE - #define SIS966_DEVN_BASE HT_CHAIN_END_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE + #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else - #define SIS966_DEVN_BASE HT_CHAIN_UNITID_BASE + #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif #define EHCI_BAR_INDEX 0x10 diff --git a/src/southbridge/sis/sis966/sis966_lpc.c b/src/southbridge/sis/sis966/sis966_lpc.c index 4e1b3cd5bc..6d3dd8e798 100644 --- a/src/southbridge/sis/sis966/sis966_lpc.c +++ b/src/southbridge/sis/sis966/sis966_lpc.c @@ -128,8 +128,8 @@ static void setup_ioapic(unsigned long ioapic_base) #define SLOW_CPU_OFF 0 #define SLOW_CPU__ON 1 -#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif static void lpc_common_init(device_t dev) @@ -179,7 +179,7 @@ static void lpc_init(device_t dev) /* power after power fail */ - on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; diff --git a/src/southbridge/via/k8t890/k8t890_dram.c b/src/southbridge/via/k8t890/k8t890_dram.c index 5339257743..b32e5f870e 100644 --- a/src/southbridge/via/k8t890/k8t890_dram.c +++ b/src/southbridge/via/k8t890/k8t890_dram.c @@ -91,7 +91,7 @@ static void get_memres(void *gp, struct device *dev, struct resource *res) (proposed_base < ((uint64_t) 0xffffffff) )) { resmax = res; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* in arch/i386/boot/tables.c */ extern uint64_t high_tables_base, high_tables_size; diff --git a/src/southbridge/via/k8t890/romstrap.lds b/src/southbridge/via/k8t890/romstrap.lds index ee162c37c8..6ce04f19ba 100644 --- a/src/southbridge/via/k8t890/romstrap.lds +++ b/src/southbridge/via/k8t890/romstrap.lds @@ -22,7 +22,7 @@ /* Modified for K8T890 ROM strap by Rudolf Marek <r.marek@assembler.cz>. */ SECTIONS { - . = (_ROMBASE + ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start); + . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start); .romstrap (.): { *(.romstrap) } diff --git a/src/southbridge/via/vt8237r/Config.lb b/src/southbridge/via/vt8237r/Config.lb index cca4a307ce..c127c5ab5f 100644 --- a/src/southbridge/via/vt8237r/Config.lb +++ b/src/southbridge/via/vt8237r/Config.lb @@ -17,7 +17,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_TABLES config chip.h @@ -26,6 +26,6 @@ driver vt8237_ctrl.o driver vt8237r_ide.o driver vt8237r_lpc.o driver vt8237r_sata.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object vt8237_fadt.o end diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c index fbcb5f3abe..1719fe09d8 100644 --- a/src/southbridge/via/vt8237r/vt8237r.c +++ b/src/southbridge/via/vt8237r/vt8237r.c @@ -33,7 +33,7 @@ void hard_reset(void) printk_err("NO HARD RESET ON VT8237R! FIX ME!\n"); } -#if DEFAULT_CONSOLE_LOGLEVEL > 7 +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 7 void writeback(struct device *dev, u16 where, u8 what) { u8 regval; diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c index 66cb3de77b..0711da8eb2 100644 --- a/src/southbridge/via/vt8237r/vt8237r_lpc.c +++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c @@ -225,7 +225,7 @@ static void setup_pm(device_t dev) /* SCI is generated for RTC/pwrBtn/slpBtn. */ tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); -#if HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME == 1 acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; printk_debug("SLP_TYP type was %x %x\n", tmp, acpi_slp_type); #endif diff --git a/src/stream/ide_stream.c b/src/stream/ide_stream.c index 832f503a95..8cf51920ab 100644 --- a/src/stream/ide_stream.c +++ b/src/stream/ide_stream.c @@ -6,8 +6,8 @@ #include <string.h> #include <pc80/ide.h> -#ifndef IDE_BOOT_DRIVE -#define IDE_BOOT_DRIVE 0 +#ifndef CONFIG_IDE_BOOT_DRIVE +#define CONFIG_IDE_BOOT_DRIVE 0 #endif static unsigned long offset; @@ -27,12 +27,12 @@ int stream_init(void) #ifdef ONE_TRACK offset = (ONE_TRACK*512); -#elif defined(IDE_OFFSET) - offset = IDE_OFFSET; +#elif defined(CONFIG_IDE_OFFSET) + offset = CONFIG_IDE_OFFSET; #else offset = 0x7e00; #endif - res = ide_probe(IDE_BOOT_DRIVE); + res = ide_probe(CONFIG_IDE_BOOT_DRIVE); delay(1); return res; } @@ -59,7 +59,7 @@ static byte_offset_t stream_ide_read(void *vdest, byte_offset_t offs, byte_offse if (block_num != offs / 512 || first_fill) { block_num = offs / 512; printk_notice ("."); - ide_read(IDE_BOOT_DRIVE, block_num, buffer); + ide_read(CONFIG_IDE_BOOT_DRIVE, block_num, buffer); first_fill = 0; } diff --git a/src/stream/rom_stream.c b/src/stream/rom_stream.c index c05af2d677..2c8699d2c5 100644 --- a/src/stream/rom_stream.c +++ b/src/stream/rom_stream.c @@ -42,7 +42,7 @@ unsigned long ulzma(unsigned char *src, unsigned char *dst); /*XXXXXXXXXXXXXX */ unsigned char *rom_start = (unsigned char *)CONFIG_ROM_PAYLOAD_START; -unsigned char *rom_end = (unsigned char *)(CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE - 1); +unsigned char *rom_end = (unsigned char *)(CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE - 1); /*XXXXXXXXXXXXXX */ static const unsigned char *rom; @@ -76,7 +76,7 @@ int stream_init(void) dest = &_eheap; /* need a good address on RAM */ -#if _RAMBASE<0x00100000 +#if CONFIG_RAMBASE<0x00100000 olen = *(unsigned int *)dest; #if (CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1) if((dest < (unsigned char *)0xa0000) && ((dest+olen)>(unsigned char *)0xa0000)) { diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index c537ded431..e761cd4fae 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -51,7 +51,7 @@ static void pnp_exit_ext_func_mode(device_t dev) pnp_write_config(dev, 0x02, 0x02); } -#ifdef HAVE_FANCTL +#ifdef CONFIG_HAVE_FANCTL extern void init_ec(uint16_t base); #else static void pnp_write_index(uint16_t port_base, uint8_t reg, uint8_t value) diff --git a/targets/a-trend/atc-6220/Config.lb b/targets/a-trend/atc-6220/Config.lb index 609110ffd9..4d8ebc0e3e 100644 --- a/targets/a-trend/atc-6220/Config.lb +++ b/targets/a-trend/atc-6220/Config.lb @@ -21,29 +21,29 @@ target atc-6220 mainboard a-trend/atc-6220 -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 -option MAINBOARD_VENDOR = "A-Trend" -option MAINBOARD_PART_NUMBER = "ATC-6220" +option CONFIG_MAINBOARD_VENDOR = "A-Trend" +option CONFIG_MAINBOARD_PART_NUMBER = "ATC-6220" -option IRQ_SLOT_COUNT = 7 +option CONFIG_IRQ_SLOT_COUNT = 7 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/a-trend/atc-6240/Config.lb b/targets/a-trend/atc-6240/Config.lb index bbd57e09a8..16a0c263b2 100644 --- a/targets/a-trend/atc-6240/Config.lb +++ b/targets/a-trend/atc-6240/Config.lb @@ -21,29 +21,29 @@ target atc-6240 mainboard a-trend/atc-6240 -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 -option MAINBOARD_VENDOR = "A-Trend" -option MAINBOARD_PART_NUMBER = "ATC-6240" +option CONFIG_MAINBOARD_VENDOR = "A-Trend" +option CONFIG_MAINBOARD_PART_NUMBER = "ATC-6240" -option IRQ_SLOT_COUNT = 7 +option CONFIG_IRQ_SLOT_COUNT = 7 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload ../payload.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/abit/be6-ii_v2_0/Config.lb b/targets/abit/be6-ii_v2_0/Config.lb index 2a4bc79c17..cfeeca0610 100644 --- a/targets/abit/be6-ii_v2_0/Config.lb +++ b/targets/abit/be6-ii_v2_0/Config.lb @@ -21,29 +21,29 @@ target be6-ii_v2_0 mainboard abit/be6-ii_v2_0 -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 -option MAINBOARD_VENDOR = "Abit" -option MAINBOARD_PART_NUMBER = "BE6-II V2.0" +option CONFIG_MAINBOARD_VENDOR = "Abit" +option CONFIG_MAINBOARD_PART_NUMBER = "BE6-II V2.0" -option IRQ_SLOT_COUNT = 9 +option CONFIG_IRQ_SLOT_COUNT = 9 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/advantech/pcm-5820/Config.lb b/targets/advantech/pcm-5820/Config.lb index fe26b2b645..8be840d6f1 100644 --- a/targets/advantech/pcm-5820/Config.lb +++ b/targets/advantech/pcm-5820/Config.lb @@ -21,12 +21,12 @@ target pcm-5820 mainboard advantech/pcm-5820 -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 -option MAINBOARD_VENDOR = "Advantech" -option MAINBOARD_PART_NUMBER = "PCM-5820" +option CONFIG_MAINBOARD_VENDOR = "Advantech" +option CONFIG_MAINBOARD_PART_NUMBER = "PCM-5820" -option IRQ_SLOT_COUNT = 2 +option CONFIG_IRQ_SLOT_COUNT = 2 ## Enable VGA with a splash screen (only 640x480 to run on most monitors). ## We want to support up to 1024x768@16 so we need 2MiB video memory. @@ -36,19 +36,19 @@ option CONFIG_GX1_VIDEOMODE = 0 option CONFIG_SPLASH_GRAPHIC = 1 option CONFIG_VIDEO_MB = 2 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/amd/db800/Config.lb b/targets/amd/db800/Config.lb index f1455a0fad..a9230f01bd 100644 --- a/targets/amd/db800/Config.lb +++ b/targets/amd/db800/Config.lb @@ -30,20 +30,20 @@ option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 option CONFIG_COMPRESSED_PAYLOAD_LZMA=0 # Leave 36k for VSA. -option ROM_SIZE=512*1024-36*1024 -# option ROM_SIZE=256*1024-36*1024 -option FALLBACK_SIZE=ROM_SIZE +option CONFIG_ROM_SIZE=512*1024-36*1024 +# option CONFIG_ROM_SIZE=256*1024-36*1024 +option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 -# option DEFAULT_CONSOLE_LOGLEVEL = 4 -# option MAXIMUM_CONSOLE_LOGLEVEL = 4 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 +# option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 4 +# option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 4 romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=64*1024 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=64*1024 option COREBOOT_EXTRA_VERSION=".0Fallback" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/amd/dbm690t/Config-abuild.lb b/targets/amd/dbm690t/Config-abuild.lb index ec05545ff7..e299413a2d 100644 --- a/targets/amd/dbm690t/Config-abuild.lb +++ b/targets/amd/dbm690t/Config-abuild.lb @@ -4,27 +4,27 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ -option ROM_SIZE=1024*1024 +option CONFIG_ROM_SIZE=1024*1024 romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "failover" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-failover" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "failover" diff --git a/targets/amd/dbm690t/Config.lb b/targets/amd/dbm690t/Config.lb index c0c3f22595..80c9db639d 100644 --- a/targets/amd/dbm690t/Config.lb +++ b/targets/amd/dbm690t/Config.lb @@ -4,18 +4,18 @@ target dbm690t mainboard amd/dbm690t romimage "normal" - option ROM_SIZE = 1024*1024 - 55808 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_ROM_SIZE = 1024*1024 - 55808 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 payload ../payload.elf end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/amd/norwich/Config.lb b/targets/amd/norwich/Config.lb index 4f4100af3f..5f927c567a 100644 --- a/targets/amd/norwich/Config.lb +++ b/targets/amd/norwich/Config.lb @@ -30,20 +30,20 @@ option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 option CONFIG_COMPRESSED_PAYLOAD_LZMA=0 -option ROM_SIZE=512*1024-36*1024 -#option ROM_SIZE=256*1024-36*1024 -option FALLBACK_SIZE=ROM_SIZE +option CONFIG_ROM_SIZE=512*1024-36*1024 +#option CONFIG_ROM_SIZE=256*1024-36*1024 +option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 -#option DEFAULT_CONSOLE_LOGLEVEL = 4 -#option MAXIMUM_CONSOLE_LOGLEVEL = 4 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 +#option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 4 +#option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 4 romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=64*1024 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=64*1024 option COREBOOT_EXTRA_VERSION=".0Fallback" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/amd/pistachio/Config-abuild.lb b/targets/amd/pistachio/Config-abuild.lb index ec05545ff7..e299413a2d 100644 --- a/targets/amd/pistachio/Config-abuild.lb +++ b/targets/amd/pistachio/Config-abuild.lb @@ -4,27 +4,27 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ -option ROM_SIZE=1024*1024 +option CONFIG_ROM_SIZE=1024*1024 romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "failover" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-failover" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "failover" diff --git a/targets/amd/pistachio/Config.lb b/targets/amd/pistachio/Config.lb index af8e1afa40..e2e7939ac7 100644 --- a/targets/amd/pistachio/Config.lb +++ b/targets/amd/pistachio/Config.lb @@ -4,18 +4,18 @@ target pistachio mainboard amd/pistachio romimage "normal" - option ROM_SIZE = 1024*1024 - 55808 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_ROM_SIZE = 1024*1024 - 55808 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 payload ../payload.elf end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/amd/rumba/Config.lb b/targets/amd/rumba/Config.lb index ee30902b8b..ac42dd41e9 100644 --- a/targets/amd/rumba/Config.lb +++ b/targets/amd/rumba/Config.lb @@ -4,11 +4,11 @@ target rumba mainboard amd/rumba -option ROM_SIZE=256*1024 +option CONFIG_ROM_SIZE=256*1024 romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -19,8 +19,8 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -30,4 +30,4 @@ romimage "fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/amd/rumba/Config.nofallback.lb b/targets/amd/rumba/Config.nofallback.lb index 448df55652..d3c5464882 100644 --- a/targets/amd/rumba/Config.nofallback.lb +++ b/targets/amd/rumba/Config.nofallback.lb @@ -4,13 +4,13 @@ target rumba mainboard amd/rumba -option ROM_SIZE=128*1024 -option FALLBACK_SIZE=ROM_SIZE -#option FALLBACK_SIZE=65535 +option CONFIG_ROM_SIZE=128*1024 +option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE +#option CONFIG_FALLBACK_SIZE=65535 #romimage "normal" -# option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x10000 +# option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x10000 # option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -21,8 +21,8 @@ option FALLBACK_SIZE=ROM_SIZE #end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -33,6 +33,6 @@ romimage "fallback" # payload /home/ollie/work/filo-0.4.1/filo.elf end -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" -buildrom ./coreboot.rom ROM_SIZE "fallback" +#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/amd/serengeti_cheetah/Config-abuild.lb b/targets/amd/serengeti_cheetah/Config-abuild.lb index 88dd1684e3..b1c927705b 100644 --- a/targets/amd/serengeti_cheetah/Config-abuild.lb +++ b/targets/amd/serengeti_cheetah/Config-abuild.lb @@ -4,33 +4,33 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "normal" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/amd/serengeti_cheetah/Config-lab.lb b/targets/amd/serengeti_cheetah/Config-lab.lb index 42cefc190e..bcb443bcac 100644 --- a/targets/amd/serengeti_cheetah/Config-lab.lb +++ b/targets/amd/serengeti_cheetah/Config-lab.lb @@ -5,20 +5,20 @@ target serengeti_cheetah mainboard amd/serengeti_cheetah -option ROM_SIZE = 0x100000 -option USE_FAILOVER_IMAGE=0 -option HAVE_FAILOVER_BOOT=0 -option FAILOVER_SIZE=0 +option CONFIG_ROM_SIZE = 0x100000 +option CONFIG_USE_FAILOVER_IMAGE=0 +option CONFIG_HAVE_FAILOVER_BOOT=0 +option CONFIG_FAILOVER_SIZE=0 romimage "fallback" option CONFIG_PRECOMPRESSED_PAYLOAD=1 option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 - option FALLBACK_SIZE=ROM_SIZE - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x1a000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x1a000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" payload ../payload.elf.lzma end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/amd/serengeti_cheetah/Config.lb b/targets/amd/serengeti_cheetah/Config.lb index a23505f6d3..ce180ea3d9 100644 --- a/targets/amd/serengeti_cheetah/Config.lb +++ b/targets/amd/serengeti_cheetah/Config.lb @@ -8,18 +8,18 @@ mainboard amd/serengeti_cheetah # serengeti_leopard romimage "normal" # 48K for SCSI FW -# option ROM_SIZE = 475136 +# option CONFIG_ROM_SIZE = 475136 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 425984 +# option CONFIG_ROM_SIZE = 425984 # 64K for Etherboot -# option ROM_SIZE = 458752 - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x18800 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x40000 +# option CONFIG_ROM_SIZE = 458752 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x18800 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -42,13 +42,13 @@ romimage "normal" end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x19800 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x40000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x19800 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -75,13 +75,13 @@ romimage "fallback" end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb b/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb index 996a1b50c3..6892a0eaa2 100644 --- a/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb +++ b/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb @@ -4,27 +4,27 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ -option ROM_SIZE=1024*1024 +option CONFIG_ROM_SIZE=1024*1024 romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x3f000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x3f000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION=".0-failover" end -buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover" diff --git a/targets/amd/serengeti_cheetah_fam10/Config-lab.lb b/targets/amd/serengeti_cheetah_fam10/Config-lab.lb index 61e1b3c762..7cc594cd7d 100644 --- a/targets/amd/serengeti_cheetah_fam10/Config-lab.lb +++ b/targets/amd/serengeti_cheetah_fam10/Config-lab.lb @@ -25,30 +25,30 @@ target serengeti_cheetah_fam10 mainboard amd/serengeti_cheetah_fam10 # Request this level of debugging output - option DEFAULT_CONSOLE_LOGLEVEL=9 + option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 # At a maximum only compile in this level of debugging - option MAXIMUM_CONSOLE_LOGLEVEL=9 + option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 # 1024KB ROM -option ROM_SIZE=1024*1024 -option FALLBACK_SIZE=ROM_SIZE-FAILOVER_SIZE +option CONFIG_ROM_SIZE=1024*1024 +option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE-CONFIG_FAILOVER_SIZE romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x30000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x30000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ../payload.elf.lzma end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover" diff --git a/targets/amd/serengeti_cheetah_fam10/Config.lb b/targets/amd/serengeti_cheetah_fam10/Config.lb index cad35150b6..189d536277 100644 --- a/targets/amd/serengeti_cheetah_fam10/Config.lb +++ b/targets/amd/serengeti_cheetah_fam10/Config.lb @@ -25,46 +25,46 @@ target serengeti_cheetah_fam10 mainboard amd/serengeti_cheetah_fam10 # Request this level of debugging output - option DEFAULT_CONSOLE_LOGLEVEL=9 + option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 # At a maximum only compile in this level of debugging - option MAXIMUM_CONSOLE_LOGLEVEL=9 + option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 # 512KB ROM -option ROM_SIZE=1024*1024 +option CONFIG_ROM_SIZE=1024*1024 # Cheetah Family 10 #romimage "normal" # 1MB ROM -# option ROM_SIZE = 0x100000 -# option USE_FAILOVER_IMAGE=0 -# option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x30000 -# option XIP_ROM_SIZE=0x40000 +# option CONFIG_ROM_SIZE = 0x100000 +# option CONFIG_USE_FAILOVER_IMAGE=0 +# option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x30000 +# option CONFIG_XIP_ROM_SIZE=0x40000 # option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../payload.elf #end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x19800 - option ROM_IMAGE_SIZE=0x7f000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x80000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x19800 + option CONFIG_ROM_IMAGE_SIZE=0x7f000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_XIP_ROM_SIZE=0x80000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ../payload.elf end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" -buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" +#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover" diff --git a/targets/arima/hdama/Config-abuild.lb b/targets/arima/hdama/Config-abuild.lb index 44cec1431d..03331da64c 100644 --- a/targets/arima/hdama/Config-abuild.lb +++ b/targets/arima/hdama/Config-abuild.lb @@ -4,25 +4,25 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ -option ROM_SIZE=512*1024 +option CONFIG_ROM_SIZE=512*1024 romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/arima/hdama/Config.kernelimage.lb b/targets/arima/hdama/Config.kernelimage.lb index 7bfaa5c477..bf5c59850c 100644 --- a/targets/arima/hdama/Config.kernelimage.lb +++ b/targets/arima/hdama/Config.kernelimage.lb @@ -6,79 +6,79 @@ loadoptions target hdama -uses ARCH +uses CONFIG_ARCH uses CONFIG_COMPRESS uses CONFIG_IOAPIC uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_UDELAY_TSC uses CPU_FIXUP -uses FALLBACK_SIZE -uses HAVE_FALLBACK_BOOT -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses HAVE_HARD_RESET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_HARD_RESET uses i586 uses i686 -uses INTEL_PPRO_MTRR -uses HEAP_SIZE -uses IRQ_SLOT_COUNT +uses CONFIG_INTEL_PPRO_MTRR +uses CONFIG_HEAP_SIZE +uses CONFIG_IRQ_SLOT_COUNT uses k7 uses k8 -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR uses CONFIG_SMP uses CONFIG_MAX_CPUS -uses MEMORY_HOLE -uses PAYLOAD_SIZE -uses _RAMBASE -uses _ROMBASE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_OFFSET -uses ROM_SECTION_SIZE -uses ROM_SIZE -uses STACK_SIZE -uses USE_FALLBACK_IMAGE -uses USE_OPTION_TABLE -uses HAVE_OPTION_TABLE -uses MAXIMUM_CONSOLE_LOGLEVEL -uses DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MEMORY_HOLE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_RAMBASE +uses CONFIG_ROMBASE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_OFFSET +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 -uses MAINBOARD +uses CONFIG_MAINBOARD uses CONFIG_CHIP_CONFIGURE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE uses COREBOOT_EXTRA_VERSION option CONFIG_CHIP_CONFIGURE=1 -option MAXIMUM_CONSOLE_LOGLEVEL=8 -option DEFAULT_CONSOLE_LOGLEVEL=8 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 option CONFIG_CONSOLE_SERIAL8250=1 option CPU_FIXUP=1 option CONFIG_UDELAY_TSC=0 option i686=1 option i586=1 -option INTEL_PPRO_MTRR=1 +option CONFIG_INTEL_PPRO_MTRR=1 option k7=1 option k8=1 -option ROM_SIZE=1024*1024 +option CONFIG_ROM_SIZE=1024*1024 -option HAVE_OPTION_TABLE=1 +option CONFIG_HAVE_OPTION_TABLE=1 option CONFIG_ROM_PAYLOAD=1 -option HAVE_FALLBACK_BOOT=1 +option CONFIG_HAVE_FALLBACK_BOOT=1 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -option FALLBACK_SIZE=ROM_SIZE +option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE ## Coreboot C code runs at this location in RAM -option _RAMBASE=0x00004000 +option CONFIG_RAMBASE=0x00004000 # ### @@ -89,9 +89,9 @@ option _RAMBASE=0x00004000 # # Arima hdama romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x10000 -# option ROM_SECTION_SIZE=0x100000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x10000 +# option CONFIG_ROM_SECTION_SIZE=0x100000 option COREBOOT_EXTRA_VERSION=".0Fallback" mainboard arima/hdama # payload ../../../../tg3--ide_disk.zelf @@ -100,4 +100,4 @@ romimage "fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/arima/hdama/Config.lb b/targets/arima/hdama/Config.lb index 038e38d63c..38d6df0704 100644 --- a/targets/arima/hdama/Config.lb +++ b/targets/arima/hdama/Config.lb @@ -6,23 +6,23 @@ target hdama mainboard arima/hdama -option ROM_SIZE=512*1024-36*1024 +option CONFIG_ROM_SIZE=512*1024-36*1024 # Arima hdama romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0Normal" payload ../../../payloads/filo.elf # payload /etc/hosts end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0Fallback" payload ../../../payloads/filo.elf # payload /etc/hosts end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/artecgroup/dbe61/Config.lb b/targets/artecgroup/dbe61/Config.lb index 9a5ec8acb9..0cd1ee5710 100644 --- a/targets/artecgroup/dbe61/Config.lb +++ b/targets/artecgroup/dbe61/Config.lb @@ -9,26 +9,26 @@ option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 option CONFIG_COMPRESSED_PAYLOAD_LZMA=0 -## ROM_SIZE is the total number of bytes allocated for coreboot use +## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use ## (normal AND fallback images and payloads). ## leave 36k for vsa and 32K for video ROM -#option ROM_SIZE = 1024*256 - 36*1024 - 32 * 1024 +#option CONFIG_ROM_SIZE = 1024*256 - 36*1024 - 32 * 1024 #No VGA for now -option ROM_SIZE = 1024*512 - 36*1024 +option CONFIG_ROM_SIZE = 1024*512 - 36*1024 -# ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, +# CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, ## not including any payload. -option ROM_IMAGE_SIZE=64*1024 +option CONFIG_ROM_IMAGE_SIZE=64*1024 -option FALLBACK_SIZE = ROM_SIZE +option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 romimage "fallback" - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=1 option COREBOOT_EXTRA_VERSION=".0Fallback" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/asi/mb_5blgp/Config.lb b/targets/asi/mb_5blgp/Config.lb index 12371c9a42..db75ec55de 100644 --- a/targets/asi/mb_5blgp/Config.lb +++ b/targets/asi/mb_5blgp/Config.lb @@ -21,12 +21,12 @@ target mb_5blgp mainboard asi/mb_5blgp -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 -option MAINBOARD_VENDOR = "ASI" -option MAINBOARD_PART_NUMBER = "MB-5BLGP" +option CONFIG_MAINBOARD_VENDOR = "ASI" +option CONFIG_MAINBOARD_PART_NUMBER = "MB-5BLGP" -option IRQ_SLOT_COUNT = 3 +option CONFIG_IRQ_SLOT_COUNT = 3 ## Enable VGA with a splash screen (only 640x480 to run on most monitors). ## We want to support up to 1024x768@16 so we need 2MiB video memory. @@ -36,19 +36,19 @@ option CONFIG_GX1_VIDEOMODE = 0 option CONFIG_SPLASH_GRAPHIC = 1 option CONFIG_VIDEO_MB = 2 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload ../payload.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/asi/mb_5blmp/Config.lb b/targets/asi/mb_5blmp/Config.lb index 94462503a8..3dfe28a6f7 100644 --- a/targets/asi/mb_5blmp/Config.lb +++ b/targets/asi/mb_5blmp/Config.lb @@ -21,23 +21,23 @@ target mb_5blmp mainboard asi/mb_5blmp -option ROM_SIZE = (256 * 1024) -# option ROM_SIZE = (256 * 1024) - (32 * 1024) -# option FALLBACK_SIZE = (256 * 1024) - (32 * 1024) +option CONFIG_ROM_SIZE = (256 * 1024) +# option CONFIG_ROM_SIZE = (256 * 1024) - (32 * 1024) +# option CONFIG_FALLBACK_SIZE = (256 * 1024) - (32 * 1024) romimage "normal" - option USE_FALLBACK_IMAGE = 0 - option ROM_IMAGE_SIZE = 64 * 1024 + option CONFIG_USE_FALLBACK_IMAGE = 0 + option CONFIG_ROM_IMAGE_SIZE = 64 * 1024 option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 - option ROM_IMAGE_SIZE = 64 * 1024 + option CONFIG_USE_FALLBACK_IMAGE = 1 + option CONFIG_ROM_IMAGE_SIZE = 64 * 1024 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" -# buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" +# buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/asus/a8n_e/Config-abuild.lb b/targets/asus/a8n_e/Config-abuild.lb index 88dd1684e3..b1c927705b 100644 --- a/targets/asus/a8n_e/Config-abuild.lb +++ b/targets/asus/a8n_e/Config-abuild.lb @@ -4,33 +4,33 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "normal" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/asus/a8n_e/Config.lb b/targets/asus/a8n_e/Config.lb index fc7330b96f..d805784ca4 100644 --- a/targets/asus/a8n_e/Config.lb +++ b/targets/asus/a8n_e/Config.lb @@ -23,30 +23,30 @@ target asus_a8n_e mainboard asus/a8n_e romimage "normal" - option USE_FAILOVER_IMAGE = 0 - option USE_FALLBACK_IMAGE = 0 - option ROM_IMAGE_SIZE = 128 * 1024 - option XIP_ROM_SIZE = 128 * 1024 + option CONFIG_USE_FAILOVER_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 + option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 + option CONFIG_XIP_ROM_SIZE = 128 * 1024 option COREBOOT_EXTRA_VERSION = "_Normal" payload ../payload.elf end romimage "fallback" - option USE_FAILOVER_IMAGE = 0 - option USE_FALLBACK_IMAGE = 1 - option ROM_IMAGE_SIZE = 128 * 1024 - option XIP_ROM_SIZE = 128 * 1024 + option CONFIG_USE_FAILOVER_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 1 + option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 + option CONFIG_XIP_ROM_SIZE = 128 * 1024 option COREBOOT_EXTRA_VERSION = "_Fallback" payload ../payload.elf end romimage "failover" - option USE_FAILOVER_IMAGE = 1 - option USE_FALLBACK_IMAGE = 0 - option ROM_IMAGE_SIZE = FAILOVER_SIZE - option XIP_ROM_SIZE = FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 0 + option CONFIG_ROM_IMAGE_SIZE = CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE = CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION = "_Failover" end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" -# buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +# buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/asus/a8v-e_se/Config.lb b/targets/asus/a8v-e_se/Config.lb index 7ae42e817a..a0af2964e5 100644 --- a/targets/asus/a8v-e_se/Config.lb +++ b/targets/asus/a8v-e_se/Config.lb @@ -21,18 +21,18 @@ target asus_a8v-e_se mainboard asus/a8v-e_se romimage "normal" - option ROM_SIZE = 512 * 1024 - option USE_FALLBACK_IMAGE = 0 - option ROM_IMAGE_SIZE = 128 * 1024 + option CONFIG_ROM_SIZE = 512 * 1024 + option CONFIG_USE_FALLBACK_IMAGE = 0 + option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 option COREBOOT_EXTRA_VERSION=".0Normal" payload ../payload.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 - option ROM_IMAGE_SIZE = 128 * 1024 + option CONFIG_USE_FALLBACK_IMAGE = 1 + option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 option COREBOOT_EXTRA_VERSION=".0Fallback" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/asus/m2v-mx_se/Config-abuild.lb b/targets/asus/m2v-mx_se/Config-abuild.lb index eaa917d109..d7357a7467 100644 --- a/targets/asus/m2v-mx_se/Config-abuild.lb +++ b/targets/asus/m2v-mx_se/Config-abuild.lb @@ -21,32 +21,32 @@ target asus_m2v-mx_se mainboard asus/m2v-mx_se option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" -## ROM_SIZE is the total number of bytes allocated for coreboot use +## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use ## (normal AND fallback images and payloads). # The board comes with 512KB SPI flash (DIP8), 128KB is for coreboot binary # 384KB of flash is for payload/roms. -option ROM_SIZE = 512 * 1024 +option CONFIG_ROM_SIZE = 512 * 1024 -## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, +## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, ## not including any payload. # Please note that 128KB is cached for (XIP) too -option ROM_IMAGE_SIZE = 128 * 1024 +option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 -## FALLBACK_SIZE is the amount of the ROM the complete fallback image +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image ## (including payload) will use. -option FALLBACK_SIZE = ROM_SIZE +option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE romimage "fallback" - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=1 payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/asus/m2v-mx_se/Config.lb b/targets/asus/m2v-mx_se/Config.lb index f963f651da..b091732bdb 100644 --- a/targets/asus/m2v-mx_se/Config.lb +++ b/targets/asus/m2v-mx_se/Config.lb @@ -20,35 +20,35 @@ target asus_m2v-mx_se mainboard asus/m2v-mx_se -## ROM_SIZE is the total number of bytes allocated for coreboot use +## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use ## (normal AND fallback images and payloads). # The board comes with 512KB SPI flash (DIP8), 128KB is for coreboot binary # 384KB of flash is for payload/roms. -option ROM_SIZE = 512 * 1024 +option CONFIG_ROM_SIZE = 512 * 1024 # Use following line instead if you want to use onboard VGA - # padd the rom size to 64KB or XIP won't work, complaining about # not good base. -#option ROM_SIZE = (512 * 1024) - (64 * 1024) +#option CONFIG_ROM_SIZE = (512 * 1024) - (64 * 1024) -## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, +## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, ## not including any payload. # Please note that 128KB is cached for (XIP) too -option ROM_IMAGE_SIZE = 128 * 1024 +option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 -## FALLBACK_SIZE is the amount of the ROM the complete fallback image +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image ## (including payload) will use. -option FALLBACK_SIZE = ROM_SIZE +option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE romimage "fallback" - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=1 payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/asus/mew-am/Config.lb b/targets/asus/mew-am/Config.lb index 3aef3c0ea6..ce65169529 100644 --- a/targets/asus/mew-am/Config.lb +++ b/targets/asus/mew-am/Config.lb @@ -21,29 +21,29 @@ target mew-am mainboard asus/mew-am -option ROM_SIZE = 512 * 1024 +option CONFIG_ROM_SIZE = 512 * 1024 -option MAINBOARD_VENDOR = "ASUS" -option MAINBOARD_PART_NUMBER = "MEW-AM" +option CONFIG_MAINBOARD_VENDOR = "ASUS" +option CONFIG_MAINBOARD_PART_NUMBER = "MEW-AM" -option IRQ_SLOT_COUNT = 8 +option CONFIG_IRQ_SLOT_COUNT = 8 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/asus/mew-vm/Config.lb b/targets/asus/mew-vm/Config.lb index b54ecaef3f..be75e03304 100644 --- a/targets/asus/mew-vm/Config.lb +++ b/targets/asus/mew-vm/Config.lb @@ -2,24 +2,24 @@ target mew-vm mainboard asus/mew-vm ## Without VGA BIOS -option ROM_SIZE = 512 * 1024 +option CONFIG_ROM_SIZE = 512 * 1024 ## With VGA BIOS (32k) -#option ROM_SIZE = (512 * 1024) - (32 * 1024) +#option CONFIG_ROM_SIZE = (512 * 1024) - (32 * 1024) romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Normal" # payload /etc/hosts payload /home/amp/filo-0.5/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /etc/hosts payload /home/amp/filo-0.5/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/asus/p2b-d/Config.lb b/targets/asus/p2b-d/Config.lb index 39f23551a6..739bb77512 100644 --- a/targets/asus/p2b-d/Config.lb +++ b/targets/asus/p2b-d/Config.lb @@ -21,29 +21,29 @@ target p2b-d mainboard asus/p2b-d -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 -option MAINBOARD_VENDOR = "ASUS" -option MAINBOARD_PART_NUMBER = "P2B-D" +option CONFIG_MAINBOARD_VENDOR = "ASUS" +option CONFIG_MAINBOARD_PART_NUMBER = "P2B-D" -option IRQ_SLOT_COUNT = 6 +option CONFIG_IRQ_SLOT_COUNT = 6 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload ../payload.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/asus/p2b-ds/Config.lb b/targets/asus/p2b-ds/Config.lb index 99e3739100..ca039ed372 100644 --- a/targets/asus/p2b-ds/Config.lb +++ b/targets/asus/p2b-ds/Config.lb @@ -21,29 +21,29 @@ target p2b-ds mainboard asus/p2b-ds -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 -option MAINBOARD_VENDOR = "ASUS" -option MAINBOARD_PART_NUMBER = "P2B-DS" +option CONFIG_MAINBOARD_VENDOR = "ASUS" +option CONFIG_MAINBOARD_PART_NUMBER = "P2B-DS" -option IRQ_SLOT_COUNT = 7 +option CONFIG_IRQ_SLOT_COUNT = 7 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload ../payload.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/asus/p2b-f/Config.lb b/targets/asus/p2b-f/Config.lb index 48d29942d8..0c19593cef 100644 --- a/targets/asus/p2b-f/Config.lb +++ b/targets/asus/p2b-f/Config.lb @@ -21,29 +21,29 @@ target p2b-f mainboard asus/p2b-f -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 -option MAINBOARD_VENDOR = "ASUS" -option MAINBOARD_PART_NUMBER = "P2B-F" +option CONFIG_MAINBOARD_VENDOR = "ASUS" +option CONFIG_MAINBOARD_PART_NUMBER = "P2B-F" -option IRQ_SLOT_COUNT = 7 +option CONFIG_IRQ_SLOT_COUNT = 7 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/asus/p2b/Config.lb b/targets/asus/p2b/Config.lb index 933d42bb06..8f5f33c3d8 100644 --- a/targets/asus/p2b/Config.lb +++ b/targets/asus/p2b/Config.lb @@ -21,29 +21,29 @@ target p2b mainboard asus/p2b -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 -option MAINBOARD_VENDOR = "ASUS" -option MAINBOARD_PART_NUMBER = "P2B" +option CONFIG_MAINBOARD_VENDOR = "ASUS" +option CONFIG_MAINBOARD_PART_NUMBER = "P2B" -option IRQ_SLOT_COUNT = 6 +option CONFIG_IRQ_SLOT_COUNT = 6 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/asus/p3b-f/Config.lb b/targets/asus/p3b-f/Config.lb index b363187329..9c2eb6131b 100644 --- a/targets/asus/p3b-f/Config.lb +++ b/targets/asus/p3b-f/Config.lb @@ -21,29 +21,29 @@ target p3b-f mainboard asus/p3b-f -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 -option MAINBOARD_VENDOR = "ASUS" -option MAINBOARD_PART_NUMBER = "P3B-F" +option CONFIG_MAINBOARD_VENDOR = "ASUS" +option CONFIG_MAINBOARD_PART_NUMBER = "P3B-F" -option IRQ_SLOT_COUNT = 8 +option CONFIG_IRQ_SLOT_COUNT = 8 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/axus/tc320/Config.lb b/targets/axus/tc320/Config.lb index 871fe9659a..749cd24992 100644 --- a/targets/axus/tc320/Config.lb +++ b/targets/axus/tc320/Config.lb @@ -23,7 +23,7 @@ target tc320 mainboard axus/tc320 -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 ## Enable VGA with a splash screen (only 640x480 to run on most monitors). ## We want to support up to 1024x768@16 so we need 2MiB video memory. @@ -33,19 +33,19 @@ option CONFIG_GX1_VIDEOMODE = 0 option CONFIG_SPLASH_GRAPHIC = 1 option CONFIG_VIDEO_MB = 2 -option DEFAULT_CONSOLE_LOGLEVEL = 6 -option MAXIMUM_CONSOLE_LOGLEVEL = 6 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload ../../../../../../../images/etherboot.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload ../../../../../../../images/etherboot.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/azza/pt-6ibd/Config.lb b/targets/azza/pt-6ibd/Config.lb index 8daca27159..19bceceed2 100644 --- a/targets/azza/pt-6ibd/Config.lb +++ b/targets/azza/pt-6ibd/Config.lb @@ -21,29 +21,29 @@ target pt-6ibd mainboard azza/pt-6ibd -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 -option MAINBOARD_VENDOR = "AZZA" -option MAINBOARD_PART_NUMBER = "PT-6IBD" +option CONFIG_MAINBOARD_VENDOR = "AZZA" +option CONFIG_MAINBOARD_PART_NUMBER = "PT-6IBD" -option IRQ_SLOT_COUNT = 7 +option CONFIG_IRQ_SLOT_COUNT = 7 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/bcom/winnet100/Config.lb b/targets/bcom/winnet100/Config.lb index ec5210fe68..de81d0f75d 100644 --- a/targets/bcom/winnet100/Config.lb +++ b/targets/bcom/winnet100/Config.lb @@ -23,7 +23,7 @@ target winnet100 mainboard bcom/winnet100 -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 ## Enable VGA with a splash screen (only 640x480 to run on most monitors). ## We want to support up to 1024x768@16 so we need 2MiB video memory. @@ -33,21 +33,21 @@ option CONFIG_GX1_VIDEOMODE = 0 option CONFIG_SPLASH_GRAPHIC = 1 option CONFIG_VIDEO_MB = 2 -option DEFAULT_CONSOLE_LOGLEVEL = 6 -option MAXIMUM_CONSOLE_LOGLEVEL = 6 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6 romimage "normal" - option USE_FALLBACK_IMAGE = 0 - option ROM_IMAGE_SIZE = 64 * 1024 + option CONFIG_USE_FALLBACK_IMAGE = 0 + option CONFIG_ROM_IMAGE_SIZE = 64 * 1024 option COREBOOT_EXTRA_VERSION = ".0Normal" payload ../../../../../../../images/etherboot.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 - option ROM_IMAGE_SIZE = 64 * 1024 + option CONFIG_USE_FALLBACK_IMAGE = 1 + option CONFIG_ROM_IMAGE_SIZE = 64 * 1024 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload ../../../../../../../images/etherboot.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/bcom/winnetp680/Config-abuild.lb b/targets/bcom/winnetp680/Config-abuild.lb index d364cb7cbd..2a65acae0d 100644 --- a/targets/bcom/winnetp680/Config-abuild.lb +++ b/targets/bcom/winnetp680/Config-abuild.lb @@ -4,18 +4,18 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ -option ROM_SIZE=512*1024 +option CONFIG_ROM_SIZE=512*1024 romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/bcom/winnetp680/Config.lb b/targets/bcom/winnetp680/Config.lb index 079e2ec8b3..ced4de9ba8 100644 --- a/targets/bcom/winnetp680/Config.lb +++ b/targets/bcom/winnetp680/Config.lb @@ -22,24 +22,24 @@ target bcom-winnet-p680 mainboard bcom/winnetp680 -option MAXIMUM_CONSOLE_LOGLEVEL=8 -option DEFAULT_CONSOLE_LOGLEVEL=8 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 option CONFIG_CONSOLE_SERIAL8250=1 # coreboot C code runs at this location in RAM -option _RAMBASE=0x00004000 +option CONFIG_RAMBASE=0x00004000 # # If space is allotted for a VGA BIOS, # generate the final ROM like this: # cat vgabios bochsbios coreboot.rom > coreboot.rom.final # -#option ROM_SIZE = (512 * 1024) - (63 * 1024) - (64 * 1024) -option ROM_SIZE = (512 * 1024) +#option CONFIG_ROM_SIZE = (512 * 1024) - (63 * 1024) - (64 * 1024) +option CONFIG_ROM_SIZE = (512 * 1024) romimage "image" option COREBOOT_EXTRA_VERSION = "-winnetp680" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "image" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "image" diff --git a/targets/biostar/m6tba/Config.lb b/targets/biostar/m6tba/Config.lb index 6439c4e926..f3ab12fb00 100644 --- a/targets/biostar/m6tba/Config.lb +++ b/targets/biostar/m6tba/Config.lb @@ -22,29 +22,29 @@ target m6tba mainboard biostar/m6tba # Note: The original flash ROM chip is 128 KB. -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 -option MAINBOARD_VENDOR = "Biostar" -option MAINBOARD_PART_NUMBER = "M6TBA" +option CONFIG_MAINBOARD_VENDOR = "Biostar" +option CONFIG_MAINBOARD_PART_NUMBER = "M6TBA" -option IRQ_SLOT_COUNT = 7 +option CONFIG_IRQ_SLOT_COUNT = 7 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/broadcom/blast/Config.lb b/targets/broadcom/blast/Config.lb index e65ed1ec97..9cef8d621f 100644 --- a/targets/broadcom/blast/Config.lb +++ b/targets/broadcom/blast/Config.lb @@ -7,17 +7,17 @@ mainboard broadcom/blast romimage "normal" # 48K for ATI rom - option ROM_SIZE = 512*1024-48*1024 + option CONFIG_ROM_SIZE = 512*1024-48*1024 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024 # 64K for Etherboot -# option ROM_SIZE = 512*1024-64*1024 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x17800 -# option ROM_IMAGE_SIZE=0x15000 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 +# option CONFIG_ROM_SIZE = 512*1024-64*1024 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x17800 +# option CONFIG_ROM_IMAGE_SIZE=0x15000 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -37,12 +37,12 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x17800 -# option ROM_IMAGE_SIZE=0x15000 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x17800 +# option CONFIG_ROM_IMAGE_SIZE=0x15000 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -62,4 +62,4 @@ romimage "fallback" # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/compaq/deskpro_en_sff_p600/Config.lb b/targets/compaq/deskpro_en_sff_p600/Config.lb index c14ae1d067..8df90b72d3 100644 --- a/targets/compaq/deskpro_en_sff_p600/Config.lb +++ b/targets/compaq/deskpro_en_sff_p600/Config.lb @@ -21,29 +21,29 @@ target deskpro_en_sff_p600 mainboard compaq/deskpro_en_sff_p600 -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 -option MAINBOARD_VENDOR = "Compaq" -option MAINBOARD_PART_NUMBER = "Deskpro EN SFF P600" +option CONFIG_MAINBOARD_VENDOR = "Compaq" +option CONFIG_MAINBOARD_PART_NUMBER = "Deskpro EN SFF P600" -option IRQ_SLOT_COUNT = 5 +option CONFIG_IRQ_SLOT_COUNT = 5 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/dell/s1850/Config.lb b/targets/dell/s1850/Config.lb index 05a26bff66..75eb19d655 100644 --- a/targets/dell/s1850/Config.lb +++ b/targets/dell/s1850/Config.lb @@ -1,24 +1,24 @@ target s1850 mainboard dell/s1850 -option ROM_SIZE=1024*1024 -option MAXIMUM_CONSOLE_LOGLEVEL=9 -option DEFAULT_CONSOLE_LOGLEVEL=9 +option CONFIG_ROM_SIZE=1024*1024 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x16000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x16000 option COREBOOT_EXTRA_VERSION=".0Normal" # payload ../../../payloads/filo.elf payload /tmp/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x16000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x16000 option COREBOOT_EXTRA_VERSION=".0Fallback" # payload ../../../payloads/filo.elf payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/digitallogic/adl855pc/Config.lb b/targets/digitallogic/adl855pc/Config.lb index 18372414a2..91021374ca 100644 --- a/targets/digitallogic/adl855pc/Config.lb +++ b/targets/digitallogic/adl855pc/Config.lb @@ -4,20 +4,20 @@ target adl855pc mainboard digitallogic/adl855pc -option DEFAULT_CONSOLE_LOGLEVEL=9 -option MAXIMUM_CONSOLE_LOGLEVEL=9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Normal" payload /etc/hosts end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Fallback" payload /etc/hosts end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/digitallogic/msm586seg/Config-abuild.lb b/targets/digitallogic/msm586seg/Config-abuild.lb index 7efa9040ec..9b5b027c16 100644 --- a/targets/digitallogic/msm586seg/Config-abuild.lb +++ b/targets/digitallogic/msm586seg/Config-abuild.lb @@ -2,18 +2,18 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "fallback" - option FALLBACK_SIZE = 256 * 1024 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE= 128 * 1024 + option CONFIG_FALLBACK_SIZE = 256 * 1024 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE= 128 * 1024 option COREBOOT_EXTRA_VERSION=".0Fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/digitallogic/msm586seg/Config.lb b/targets/digitallogic/msm586seg/Config.lb index 565434c238..a2ad579644 100644 --- a/targets/digitallogic/msm586seg/Config.lb +++ b/targets/digitallogic/msm586seg/Config.lb @@ -3,30 +3,30 @@ mainboard digitallogic/msm586seg -option DEFAULT_CONSOLE_LOGLEVEL=3 -option MAXIMUM_CONSOLE_LOGLEVEL=3 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=3 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=3 option CONFIG_COMPRESS=0 option CONFIG_CONSOLE_VGA=0 #romimage "normal" -# option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x10000 +# option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x10000 # option COREBOOT_EXTRA_VERSION=".0Normal" # payload /etc/hosts #end romimage "fallback" - option FALLBACK_SIZE = 256 * 1024 -# option ROM_SIZE=512*1024 -# option ROM_SECTION_SIZE=512*1024 - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=32 * 1024 # 0x8000 - option ROM_IMAGE_SIZE=128 * 1024 # 0x10000 -# option ROM_IMAGE_SIZE=512 * 1024 # 0x10000 + option CONFIG_FALLBACK_SIZE = 256 * 1024 +# option CONFIG_ROM_SIZE=512*1024 +# option CONFIG_ROM_SECTION_SIZE=512*1024 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=32 * 1024 # 0x8000 + option CONFIG_ROM_IMAGE_SIZE=128 * 1024 # 0x10000 +# option CONFIG_ROM_IMAGE_SIZE=512 * 1024 # 0x10000 option COREBOOT_EXTRA_VERSION=".0Fallback" payload ../../filo.elf # payload ../../eepro100--ide_disk.zelf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/digitallogic/msm800sev/Config.lb b/targets/digitallogic/msm800sev/Config.lb index 83ca2f60b9..473556bea7 100644 --- a/targets/digitallogic/msm800sev/Config.lb +++ b/targets/digitallogic/msm800sev/Config.lb @@ -5,24 +5,24 @@ mainboard digitallogic/msm800sev option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 -## ROM_SIZE is the total number of bytes allocated for coreboot use +## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use ## (normal AND fallback images and payloads). ## leave 36k for vsa ## -option ROM_SIZE = 1024*1024 - 36 * 1024 +option CONFIG_ROM_SIZE = 1024*1024 - 36 * 1024 -## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, +## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, ## not including any payload. -option ROM_IMAGE_SIZE=64*1024 +option CONFIG_ROM_IMAGE_SIZE=64*1024 -option FALLBACK_SIZE = ROM_SIZE +option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 romimage "fallback" - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=1 option COREBOOT_EXTRA_VERSION=".0Fallback" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/eaglelion/5bcm/Config.lb b/targets/eaglelion/5bcm/Config.lb index b237190ad9..323ab7a623 100644 --- a/targets/eaglelion/5bcm/Config.lb +++ b/targets/eaglelion/5bcm/Config.lb @@ -4,11 +4,11 @@ target 5bcm mainboard eaglelion/5bcm -option ROM_SIZE=256*1024 +option CONFIG_ROM_SIZE=256*1024 romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -18,8 +18,8 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -28,4 +28,4 @@ romimage "fallback" payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/embeddedplanet/ep405pc/Config.lb b/targets/embeddedplanet/ep405pc/Config.lb index ba794badf6..0f7d13040f 100644 --- a/targets/embeddedplanet/ep405pc/Config.lb +++ b/targets/embeddedplanet/ep405pc/Config.lb @@ -6,10 +6,10 @@ mainboard embeddedplanet/ep405pc romimage "normal" ## Enable PPC405 instructions - option CPU_OPT="-mcpu=405" + option CONFIG_CPU_OPT="-mcpu=405" ## use a cross compiler - #option CROSS_COMPILE="powerpc-ibm-eabi-" + #option CONFIG_CROSS_COMPILE="powerpc-ibm-eabi-" ## Use stage 1 initialization code option CONFIG_USE_INIT=1 @@ -21,14 +21,14 @@ romimage "normal" option CONFIG_COMPRESS=0 ## Turn off POST codes - option NO_POST=1 + option CONFIG_NO_POST=1 ## Enable serial console - option DEFAULT_CONSOLE_LOGLEVEL=8 + option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 option CONFIG_CONSOLE_SERIAL8250=1 # Divisor of 69 == 9600 baud due to weird clocking - option TTYS0_DIV=69 - option TTYS0_BAUD=9600 + option CONFIG_TTYS0_DIV=69 + option CONFIG_TTYS0_BAUD=9600 ## Boot linux from IDE option CONFIG_IDE=1 @@ -36,25 +36,25 @@ romimage "normal" option CONFIG_FS_EXT2=1 option CONFIG_FS_ISO9660=1 option CONFIG_FS_FAT=1 - option AUTOBOOT_CMDLINE="hda1:/vmlinuz" + option CONFIG_AUTOBOOT_CMDLINE="hda1:/vmlinuz" - option ROM_SIZE=1024*1024 + option CONFIG_ROM_SIZE=1024*1024 ## Board has fixed size RAM - option EMBEDDED_RAM_SIZE=64*1024*1024 + option CONFIG_EMBEDDED_RAM_SIZE=64*1024*1024 ## Coreboot C code runs at this location in RAM - option _RAMBASE=0x00100000 + option CONFIG_RAMBASE=0x00100000 ## ## Use a 64K stack ## - option STACK_SIZE=0x10000 + option CONFIG_STACK_SIZE=0x10000 ## ## Use a 64K heap ## - option HEAP_SIZE=0x10000 + option CONFIG_HEAP_SIZE=0x10000 ## ## System clock @@ -62,20 +62,20 @@ romimage "normal" option CONFIG_SYS_CLK_FREQ=33 ## - option _ROMBASE=0xfff00000 + option CONFIG_ROMBASE=0xfff00000 ## Reset vector address - option _RESET=0xfffffffc + option CONFIG_RESET=0xfffffffc ## Exception vectors - option _EXCEPTION_VECTORS=_ROMBASE+0x100 + option CONFIG_EXCEPTION_VECTORS=CONFIG_ROMBASE+0x100 ## coreboot ROM start address - option _ROMSTART=0xfff03000 + option CONFIG_ROMSTART=0xfff03000 ## coreboot C code runs at this location in RAM - option _RAMBASE=0x00100000 + option CONFIG_RAMBASE=0x00100000 end -buildrom ./coreboot.rom ROM_SIZE "normal" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" diff --git a/targets/emulation/qemu-x86/Config-abuild.lb b/targets/emulation/qemu-x86/Config-abuild.lb index bcfc9c5aad..0d537cad91 100644 --- a/targets/emulation/qemu-x86/Config-abuild.lb +++ b/targets/emulation/qemu-x86/Config-abuild.lb @@ -2,17 +2,17 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "fallback" - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=1 option COREBOOT_EXTRA_VERSION=".0" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/emulation/qemu-x86/Config-car.lb b/targets/emulation/qemu-x86/Config-car.lb index bdb27bc9cd..00b2200b2e 100644 --- a/targets/emulation/qemu-x86/Config-car.lb +++ b/targets/emulation/qemu-x86/Config-car.lb @@ -3,24 +3,24 @@ target qemu-x86-car mainboard emulation/qemu-x86 -option USE_DCACHE_RAM=1 +option CONFIG_USE_DCACHE_RAM=1 option CONFIG_USE_INIT=1 -option ROM_SIZE=512*1024 +option CONFIG_ROM_SIZE=512*1024 option CONFIG_USE_INIT=1 option CONFIG_USE_PRINTK_IN_CAR=1 option CC="gcc -m32" -option HAVE_PIRQ_TABLE=1 -option IRQ_SLOT_COUNT=6 +option CONFIG_HAVE_PIRQ_TABLE=1 +option CONFIG_IRQ_SLOT_COUNT=6 romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION="-GRUB2" # payload /home/stepan/core.img payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/emulation/qemu-x86/Config-lab.lb b/targets/emulation/qemu-x86/Config-lab.lb index 970b95295d..2e38aa1fd1 100644 --- a/targets/emulation/qemu-x86/Config-lab.lb +++ b/targets/emulation/qemu-x86/Config-lab.lb @@ -3,19 +3,19 @@ target qemu-x86 mainboard emulation/qemu-x86 -option ROM_SIZE=2048*1024 +option CONFIG_ROM_SIZE=2048*1024 option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 option CONFIG_PRECOMPRESSED_PAYLOAD=1 option CC="gcc -m32" -option HAVE_PIRQ_TABLE=1 -option IRQ_SLOT_COUNT=6 +option CONFIG_HAVE_PIRQ_TABLE=1 +option CONFIG_IRQ_SLOT_COUNT=6 romimage "image" option COREBOOT_EXTRA_VERSION="-LAB" payload ../payload.elf.lzma end -buildrom ./coreboot.rom ROM_SIZE "image" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "image" diff --git a/targets/emulation/qemu-x86/Config.OLPC.lb b/targets/emulation/qemu-x86/Config.OLPC.lb index 93c4fb3557..6f5b2abe4c 100644 --- a/targets/emulation/qemu-x86/Config.OLPC.lb +++ b/targets/emulation/qemu-x86/Config.OLPC.lb @@ -3,19 +3,19 @@ target qemu-x86-OLPC mainboard emulation/qemu-x86 -option ROM_SIZE=1024*1024 - (128 * 1024) +option CONFIG_ROM_SIZE=1024*1024 - (128 * 1024) option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 option CONFIG_PRECOMPRESSED_PAYLOAD=0 option CC="gcc -m32" -option HAVE_PIRQ_TABLE=1 -option IRQ_SLOT_COUNT=6 +option CONFIG_HAVE_PIRQ_TABLE=1 +option CONFIG_IRQ_SLOT_COUNT=6 romimage "image" option COREBOOT_EXTRA_VERSION="-OpenBIOS" payload /tmp/olpcpayload.elf end -buildrom ./coreboot.rom ROM_SIZE "image" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "image" diff --git a/targets/emulation/qemu-x86/Config.lb b/targets/emulation/qemu-x86/Config.lb index 91d4413725..659da67358 100644 --- a/targets/emulation/qemu-x86/Config.lb +++ b/targets/emulation/qemu-x86/Config.lb @@ -3,14 +3,14 @@ target qemu-x86 mainboard emulation/qemu-x86 -option ROM_SIZE=512*1024 +option CONFIG_ROM_SIZE=512*1024 option CC="gcc -m32" -option HAVE_PIRQ_TABLE=1 -option IRQ_SLOT_COUNT=6 -option DEFAULT_CONSOLE_LOGLEVEL=9 -option MAXIMUM_CONSOLE_LOGLEVEL=9 +option CONFIG_HAVE_PIRQ_TABLE=1 +option CONFIG_IRQ_SLOT_COUNT=6 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 romimage "normal" option COREBOOT_EXTRA_VERSION="-GRUB2" @@ -18,5 +18,5 @@ romimage "normal" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" diff --git a/targets/gigabyte/ga-6bxc/Config.lb b/targets/gigabyte/ga-6bxc/Config.lb index 12f259087c..4efbcb6398 100644 --- a/targets/gigabyte/ga-6bxc/Config.lb +++ b/targets/gigabyte/ga-6bxc/Config.lb @@ -21,29 +21,29 @@ target ga-6bxc mainboard gigabyte/ga-6bxc -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 -option MAINBOARD_VENDOR = "GIGABYTE" -option MAINBOARD_PART_NUMBER = "GA-6BXC" +option CONFIG_MAINBOARD_VENDOR = "GIGABYTE" +option CONFIG_MAINBOARD_PART_NUMBER = "GA-6BXC" -option IRQ_SLOT_COUNT = 6 +option CONFIG_IRQ_SLOT_COUNT = 6 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/gigabyte/ga_2761gxdk/Config-abuild.lb b/targets/gigabyte/ga_2761gxdk/Config-abuild.lb index bba261153c..14e83807e8 100644 --- a/targets/gigabyte/ga_2761gxdk/Config-abuild.lb +++ b/targets/gigabyte/ga_2761gxdk/Config-abuild.lb @@ -23,39 +23,39 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ -option ROM_SIZE = 512*1024 +option CONFIG_ROM_SIZE = 512*1024 romimage "normal" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x28000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x28000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION=".0-Normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION=".0-Failover" end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/gigabyte/ga_2761gxdk/Config.lb b/targets/gigabyte/ga_2761gxdk/Config.lb index fc802f24a2..1266366e80 100644 --- a/targets/gigabyte/ga_2761gxdk/Config.lb +++ b/targets/gigabyte/ga_2761gxdk/Config.lb @@ -26,33 +26,33 @@ mainboard gigabyte/ga_2761gxdk romimage "normal" # 32K for VGA BIOS - option ROM_SIZE = (512*1024 - 32*1024) + option CONFIG_ROM_SIZE = (512*1024 - 32*1024) - option USE_FAILOVER_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../../payloads/filo_uda1.elf payload ../payload.elf end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../../payloads/filo_uda1.elf payload ../payload.elf end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -# buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" - buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +# buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" + buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/gigabyte/m57sli/Config-abuild.lb b/targets/gigabyte/m57sli/Config-abuild.lb index 88dd1684e3..b1c927705b 100644 --- a/targets/gigabyte/m57sli/Config-abuild.lb +++ b/targets/gigabyte/m57sli/Config-abuild.lb @@ -4,33 +4,33 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "normal" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/gigabyte/m57sli/Config-lab.lb b/targets/gigabyte/m57sli/Config-lab.lb index 06435429d9..6ed4f11656 100644 --- a/targets/gigabyte/m57sli/Config-lab.lb +++ b/targets/gigabyte/m57sli/Config-lab.lb @@ -24,26 +24,26 @@ target m57sli mainboard gigabyte/m57sli -option ROM_SIZE=0x100000 -option FALLBACK_SIZE=(ROM_SIZE-0x1000) +option CONFIG_ROM_SIZE=0x100000 +option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x1000) romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 option CONFIG_PRECOMPRESSED_PAYLOAD=1 - option ROM_IMAGE_SIZE=0x17000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_ROM_IMAGE_SIZE=0x17000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ../payload.elf.lzma end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover" diff --git a/targets/gigabyte/m57sli/Config.lb b/targets/gigabyte/m57sli/Config.lb index 5a61bede5b..06d26eba5c 100644 --- a/targets/gigabyte/m57sli/Config.lb +++ b/targets/gigabyte/m57sli/Config.lb @@ -25,20 +25,20 @@ mainboard gigabyte/m57sli # serengeti_leopard romimage "normal" # 48K for SCSI FW -# option ROM_SIZE = 475136 +# option CONFIG_ROM_SIZE = 475136 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 425984 +# option CONFIG_ROM_SIZE = 425984 # 64K for Etherboot -# option ROM_SIZE = 458752 +# option CONFIG_ROM_SIZE = 458752 # 44k for atixx.rom -# option ROM_SIZE = 479232 - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x18800 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x40000 +# option CONFIG_ROM_SIZE = 479232 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x18800 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -61,13 +61,13 @@ romimage "normal" end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x19800 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x40000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x19800 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -95,12 +95,12 @@ romimage "fallback" end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/gigabyte/m57sli/Config.lb.kernel b/targets/gigabyte/m57sli/Config.lb.kernel index 6485e6c461..e5952e3785 100644 --- a/targets/gigabyte/m57sli/Config.lb.kernel +++ b/targets/gigabyte/m57sli/Config.lb.kernel @@ -24,19 +24,19 @@ target m57sli mainboard gigabyte/m57sli -option ROM_SIZE=0x200000 -option FALLBACK_SIZE=(ROM_SIZE-0x1000) +option CONFIG_ROM_SIZE=0x200000 +option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x1000) romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 option CONFIG_PRECOMPRESSED_PAYLOAD=1 -# option ROM_IMAGE_SIZE=0x19800 - option ROM_IMAGE_SIZE=0x17000 -# option ROM_IMAGE_SIZE=0x15800 -# option ROM_IMAGE_SIZE=0x13800 - option XIP_ROM_SIZE=0x40000 +# option CONFIG_ROM_IMAGE_SIZE=0x19800 + option CONFIG_ROM_IMAGE_SIZE=0x17000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -65,13 +65,13 @@ romimage "fallback" end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover" +#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/hp/dl145_g3/Config.lb b/targets/hp/dl145_g3/Config.lb index 47aae1b225..c66a94fc83 100644 --- a/targets/hp/dl145_g3/Config.lb +++ b/targets/hp/dl145_g3/Config.lb @@ -24,16 +24,16 @@ target dl145_g3 mainboard hp/dl145_g3 -option ROM_SIZE= 1024*1024 +option CONFIG_ROM_SIZE= 1024*1024 romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ./bios.bin.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" pci_rom ./matrox.rom vendor_id=0x102b device_id=0x0522 diff --git a/targets/ibm/e325/Config.lb b/targets/ibm/e325/Config.lb index 8e492d5a53..cd1a055815 100644 --- a/targets/ibm/e325/Config.lb +++ b/targets/ibm/e325/Config.lb @@ -14,16 +14,16 @@ mainboard ibm/e325 # # Arima hdama romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0Normal" # payload ../../filo.elf payload ../../../payloads/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0Fallback" # payload ../../filo.elf payload ../../../payloads/filo.elf @@ -31,4 +31,4 @@ romimage "fallback" # payload /etc/hosts end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/ibm/e326/Config-abuild.lb b/targets/ibm/e326/Config-abuild.lb index 44cec1431d..03331da64c 100644 --- a/targets/ibm/e326/Config-abuild.lb +++ b/targets/ibm/e326/Config-abuild.lb @@ -4,25 +4,25 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ -option ROM_SIZE=512*1024 +option CONFIG_ROM_SIZE=512*1024 romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/ibm/e326/Config.lb b/targets/ibm/e326/Config.lb index 8129dd6ab5..34ba0d9eeb 100644 --- a/targets/ibm/e326/Config.lb +++ b/targets/ibm/e326/Config.lb @@ -10,16 +10,16 @@ mainboard ibm/e326 ### romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0Normal" # payload ../../filo.elf payload ../../../payloads/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0Fallback" # payload ../../filo.elf payload ../../../payloads/filo.elf @@ -27,4 +27,4 @@ romimage "fallback" # payload /etc/hosts end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/iei/juki-511p/Config-abuild.lb b/targets/iei/juki-511p/Config-abuild.lb index 3c203bdd9b..f26e780cf3 100644 --- a/targets/iei/juki-511p/Config-abuild.lb +++ b/targets/iei/juki-511p/Config-abuild.lb @@ -2,31 +2,31 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ -option ROM_SIZE=256*1024 +option CONFIG_ROM_SIZE=256*1024 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -option FALLBACK_SIZE=128*1024 +option CONFIG_FALLBACK_SIZE=128*1024 romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=64*1024 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=64*1024 option COREBOOT_EXTRA_VERSION=".0-Normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=64*1024 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=64*1024 option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/iei/juki-511p/Config.lb b/targets/iei/juki-511p/Config.lb index 5015562285..83fa1ffa67 100644 --- a/targets/iei/juki-511p/Config.lb +++ b/targets/iei/juki-511p/Config.lb @@ -21,17 +21,17 @@ target juki-511p mainboard iei/juki-511p -option ROM_SIZE=256*1024 +option CONFIG_ROM_SIZE=256*1024 -option HAVE_PIRQ_TABLE=1 +option CONFIG_HAVE_PIRQ_TABLE=1 option CONFIG_COMPRESS=0 option CONFIG_PRECOMPRESSED_PAYLOAD=0 romimage "image" - option ROM_IMAGE_SIZE=64*1024 + option CONFIG_ROM_IMAGE_SIZE=64*1024 option COREBOOT_EXTRA_VERSION="-filo" payload ../../filo.elf end -buildrom ./coreboot.rom ROM_SIZE "image" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "image" diff --git a/targets/iei/nova4899r/Config.lb b/targets/iei/nova4899r/Config.lb index ec2e76f588..7a7e108fb2 100644 --- a/targets/iei/nova4899r/Config.lb +++ b/targets/iei/nova4899r/Config.lb @@ -24,24 +24,24 @@ target nova4899r mainboard iei/nova4899r -#option ROM_SIZE=256*1024 +#option CONFIG_ROM_SIZE=256*1024 #from OLPC definitions option CONFIG_COMPRESSED_PAYLOAD_NRV2B=1 #option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 #option CONFIG_PRECOMPRESSED_PAYLOAD=0 # leave 128k for vsa and 32k for VGA code -option ROM_SIZE=(256*1024)-(128*1024)-(32*1024) -option FALLBACK_SIZE=ROM_SIZE +option CONFIG_ROM_SIZE=(256*1024)-(128*1024)-(32*1024) +option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE -option DEFAULT_CONSOLE_LOGLEVEL = 8 -option MAXIMUM_CONSOLE_LOGLEVEL = 8 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=64*1024 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=64*1024 option COREBOOT_EXTRA_VERSION=".0Fallback" payload /opt/coreboot-SVN/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" #"normal" diff --git a/targets/iei/pcisa-lx-800-r10/Config.lb b/targets/iei/pcisa-lx-800-r10/Config.lb index 7993fa6aaa..8b848065b3 100644 --- a/targets/iei/pcisa-lx-800-r10/Config.lb +++ b/targets/iei/pcisa-lx-800-r10/Config.lb @@ -27,20 +27,20 @@ option CONFIG_COMPRESSED_PAYLOAD_NRV2B = 0 option CONFIG_COMPRESSED_PAYLOAD_LZMA = 0 # Leave 36k for VSA. -option ROM_SIZE = (512 * 1024) - (36 * 1024) -# option ROM_SIZE = (2048 * 1024) - (36 * 1024) +option CONFIG_ROM_SIZE = (512 * 1024) - (36 * 1024) +# option CONFIG_ROM_SIZE = (2048 * 1024) - (36 * 1024) # Leave 36k for VSA, 1152k for bzImage and 750k for initrd. -# option ROM_SIZE = (2048 * 1024) - (36 * 1024) - (1152 * 1024) - (750 * 1024) -option FALLBACK_SIZE = ROM_SIZE +# option CONFIG_ROM_SIZE = (2048 * 1024) - (36 * 1024) - (1152 * 1024) - (750 * 1024) +option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE -option DEFAULT_CONSOLE_LOGLEVEL = 0 -option MAXIMUM_CONSOLE_LOGLEVEL = 0 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0 romimage "fallback" - option USE_FALLBACK_IMAGE = 1 - option ROM_IMAGE_SIZE = 80 * 1024 + option CONFIG_USE_FALLBACK_IMAGE = 1 + option CONFIG_ROM_IMAGE_SIZE = 80 * 1024 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/intel/mtarvon/Config.lb b/targets/intel/mtarvon/Config.lb index 432bf6a1c2..87dc4f9d45 100644 --- a/targets/intel/mtarvon/Config.lb +++ b/targets/intel/mtarvon/Config.lb @@ -20,21 +20,21 @@ target mtarvon mainboard intel/mtarvon -## ROM_SIZE is the total number of bytes allocated for coreboot use +## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use ## (normal AND fallback images and payloads). -option ROM_SIZE = 2 * 1024 * 1024 +option CONFIG_ROM_SIZE = 2 * 1024 * 1024 -## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, +## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, ## not including any payload. -option ROM_IMAGE_SIZE = 128 * 1024 +option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 -## FALLBACK_SIZE is the amount of the ROM the complete fallback image +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image ## (including payload) will use -option FALLBACK_SIZE = ROM_SIZE +option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE romimage "fallback" - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=1 payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/intel/truxton/Config.lb b/targets/intel/truxton/Config.lb index 3b1a580fd9..669c1c00cc 100644 --- a/targets/intel/truxton/Config.lb +++ b/targets/intel/truxton/Config.lb @@ -20,21 +20,21 @@ target truxton mainboard intel/truxton -## ROM_SIZE is the total number of bytes allocated for coreboot use +## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use ## (normal AND fallback images and payloads). -option ROM_SIZE = 2 * 1024 * 1024 +option CONFIG_ROM_SIZE = 2 * 1024 * 1024 -## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, +## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, ## not including any payload. -option ROM_IMAGE_SIZE = 128 * 1024 +option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 -## FALLBACK_SIZE is the amount of the ROM the complete fallback image +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image ## (including payload) will use -option FALLBACK_SIZE = ROM_SIZE +option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE romimage "fallback" - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=1 payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/intel/xe7501devkit/Config.lb b/targets/intel/xe7501devkit/Config.lb index b421f1b005..00f9451984 100644 --- a/targets/intel/xe7501devkit/Config.lb +++ b/targets/intel/xe7501devkit/Config.lb @@ -1,22 +1,22 @@ target xe7501devkit mainboard intel/xe7501devkit -## ROM_SIZE is the total number of bytes allocated for coreboot use +## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use ## (normal AND fallback images and payloads). -option ROM_SIZE = 192*1024 +option CONFIG_ROM_SIZE = 192*1024 -## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, +## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, ## not including any payload. -option ROM_IMAGE_SIZE = 0x1B000 +option CONFIG_ROM_IMAGE_SIZE = 0x1B000 -## FALLBACK_SIZE is the amount of the ROM the complete fallback image +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image ## (including payload) will use -option FALLBACK_SIZE = 0 +option CONFIG_FALLBACK_SIZE = 0 romimage "normal" - option USE_FALLBACK_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 # option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../../../../../memtest86/memtest # payload ../../../../../../../etherboot/src/bin/e1000.zelf @@ -27,11 +27,11 @@ end #NOTE: CMOS currently not supported due to conflicts with factory BIOS # Thus no support for fallback boot. #romimage "fallback" -# option USE_FALLBACK_IMAGE=1 +# option CONFIG_USE_FALLBACK_IMAGE=1 # option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../../../../../memtest86/memtest # payload ../../../../../../../etherboot/src/bin/e1000.zelf # payload ../../../../../../../etherboot/src/bin/e1000--filo.zelf #end -buildrom ./coreboot.rom ROM_SIZE "normal" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" diff --git a/targets/iwill/dk8_htx/Config-abuild.lb b/targets/iwill/dk8_htx/Config-abuild.lb index 88dd1684e3..b1c927705b 100644 --- a/targets/iwill/dk8_htx/Config-abuild.lb +++ b/targets/iwill/dk8_htx/Config-abuild.lb @@ -4,33 +4,33 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "normal" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/iwill/dk8_htx/Config.lb b/targets/iwill/dk8_htx/Config.lb index 842bd3d021..460dcc417d 100644 --- a/targets/iwill/dk8_htx/Config.lb +++ b/targets/iwill/dk8_htx/Config.lb @@ -5,18 +5,18 @@ mainboard iwill/dk8_htx # serengeti_leopard romimage "normal" # 48K for SCSI FW -# option ROM_SIZE = 475136 +# option CONFIG_ROM_SIZE = 475136 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 425984 +# option CONFIG_ROM_SIZE = 425984 # 64K for Etherboot -# option ROM_SIZE = 458752 - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x17800 -# option ROM_IMAGE_SIZE=0x15800 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 +# option CONFIG_ROM_SIZE = 458752 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x17800 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -36,13 +36,13 @@ romimage "normal" end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x17800 -# option ROM_IMAGE_SIZE=0x15800 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x17800 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -63,12 +63,12 @@ romimage "fallback" end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/iwill/dk8s2/Config.lb b/targets/iwill/dk8s2/Config.lb index c239a163ad..e4b426fc6f 100644 --- a/targets/iwill/dk8s2/Config.lb +++ b/targets/iwill/dk8s2/Config.lb @@ -6,13 +6,13 @@ target dk8s2 mainboard iwill/dk8s2 -option HAVE_HARD_RESET=1 +option CONFIG_HAVE_HARD_RESET=1 -option HAVE_OPTION_TABLE=1 -option HAVE_MP_TABLE=1 -option ROM_SIZE=1024*1024 +option CONFIG_HAVE_OPTION_TABLE=1 +option CONFIG_HAVE_MP_TABLE=1 +option CONFIG_ROM_SIZE=1024*1024 -option HAVE_FALLBACK_BOOT=1 +option CONFIG_HAVE_FALLBACK_BOOT=1 #option CONFIG_LSI_SCSI_FW_FIXUP=1 @@ -21,8 +21,8 @@ option HAVE_FALLBACK_BOOT=1 ### ### Build code to export a programmable irq routing table ### -option HAVE_PIRQ_TABLE=1 -option IRQ_SLOT_COUNT=12 +option CONFIG_HAVE_PIRQ_TABLE=1 +option CONFIG_IRQ_SLOT_COUNT=12 # ### ### Build code for SMP support @@ -39,7 +39,7 @@ option CONFIG_MAX_PHYSICAL_CPUS=2 option CONFIG_IOAPIC=1 # ### -### MEMORY_HOLE instructs earlymtrr.inc to +### CONFIG_MEMORY_HOLE instructs earlymtrr.inc to ### enable caching from 0-640KB and to disable ### caching from 640KB-1MB using fixed MTRRs ### @@ -47,24 +47,24 @@ option CONFIG_IOAPIC=1 ### CPU identification depends on only variable MTRRs ### being enabled. ### -#option MEMORY_HOLE=0 +#option CONFIG_MEMORY_HOLE=0 # ### ### Clean up the motherboard id strings ### -option MAINBOARD_PART_NUMBER="DK8S2" -option MAINBOARD_VENDOR="IWILL" +option CONFIG_MAINBOARD_PART_NUMBER="DK8S2" +option CONFIG_MAINBOARD_VENDOR="IWILL" # ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -#option FALLBACK_SIZE=524288 -#option FALLBACK_SIZE=98304 -option FALLBACK_SIZE=131072 +#option CONFIG_FALLBACK_SIZE=524288 +#option CONFIG_FALLBACK_SIZE=98304 +option CONFIG_FALLBACK_SIZE=131072 -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -option ROM_IMAGE_SIZE=65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +option CONFIG_ROM_IMAGE_SIZE=65536 ### @@ -77,7 +77,7 @@ option ROM_IMAGE_SIZE=65536 #option CONFIG_COMPRESS=1 option CONFIG_CONSOLE_SERIAL8250=1 -option TTYS0_BAUD=115200 +option CONFIG_TTYS0_BAUD=115200 ## ### Select the coreboot loglevel @@ -89,30 +89,30 @@ option TTYS0_BAUD=115200 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -option DEFAULT_CONSOLE_LOGLEVEL=7 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 ## At a maximum only compile in this level of debugging -option MAXIMUM_CONSOLE_LOGLEVEL=7 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=7 -#option DEBUG=1 +#option CONFIG_DEBUG=1 # ## Coreboot C code runs at this location in RAM -option _RAMBASE=0x004000 +option CONFIG_RAMBASE=0x004000 ## ## Use a 32K stack ## -option STACK_SIZE=0x8000 +option CONFIG_STACK_SIZE=0x8000 ## ## Use a 56K heap ## -option HEAP_SIZE=0xe000 +option CONFIG_HEAP_SIZE=0xe000 # ### @@ -125,22 +125,22 @@ option CONFIG_ROM_PAYLOAD = 1 # romimage "normal" # 48K for SCSI FW -# option ROM_SIZE = 512*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" - option USE_FALLBACK_IMAGE=0 - option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - option ROM_SECTION_OFFSET= 0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_SECTION_SIZE = (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE) + option CONFIG_ROM_SECTION_OFFSET= 0 - option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) - option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - option _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) + option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE) + option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) + option CONFIG_ROMBASE = (CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE) -# option XIP_ROM_SIZE = FALLBACK_SIZE - option XIP_ROM_SIZE = 65536 +# option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE + option CONFIG_XIP_ROM_SIZE = 65536 - option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) + option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE) payload /usr/src/filo-0.4.1_btext/filo.elf # payload /usr/src/filo-0.4.2/filo.elf @@ -148,20 +148,20 @@ end romimage "fallback" option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_SECTION_SIZE = FALLBACK_SIZE - option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE) + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE + option CONFIG_ROM_SECTION_OFFSET= (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE) - option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) - option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - option _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) + option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE) + option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) + option CONFIG_ROMBASE = (CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE) -# option XIP_ROM_SIZE = FALLBACK_SIZE - option XIP_ROM_SIZE = 65536 - option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +# option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE + option CONFIG_XIP_ROM_SIZE = 65536 + option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE) payload ../../../payloads/filo.elf # payload /usr/src/filo-0.4.2/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/iwill/dk8x/Config.lb b/targets/iwill/dk8x/Config.lb index bcb18b8998..ab4ff09c60 100644 --- a/targets/iwill/dk8x/Config.lb +++ b/targets/iwill/dk8x/Config.lb @@ -6,13 +6,13 @@ target dk8x mainboard iwill/dk8x -option HAVE_HARD_RESET=1 +option CONFIG_HAVE_HARD_RESET=1 -option HAVE_OPTION_TABLE=1 -option HAVE_MP_TABLE=1 -option ROM_SIZE=1024*1024 +option CONFIG_HAVE_OPTION_TABLE=1 +option CONFIG_HAVE_MP_TABLE=1 +option CONFIG_ROM_SIZE=1024*1024 -option HAVE_FALLBACK_BOOT=1 +option CONFIG_HAVE_FALLBACK_BOOT=1 #option CONFIG_LSI_SCSI_FW_FIXUP=1 @@ -21,8 +21,8 @@ option HAVE_FALLBACK_BOOT=1 ### ### Build code to export a programmable irq routing table ### -option HAVE_PIRQ_TABLE=1 -option IRQ_SLOT_COUNT=12 +option CONFIG_HAVE_PIRQ_TABLE=1 +option CONFIG_IRQ_SLOT_COUNT=12 # ### ### Build code for SMP support @@ -39,7 +39,7 @@ option CONFIG_MAX_PHYSICAL_CPUS=2 option CONFIG_IOAPIC=1 # ### -### MEMORY_HOLE instructs earlymtrr.inc to +### CONFIG_MEMORY_HOLE instructs earlymtrr.inc to ### enable caching from 0-640KB and to disable ### caching from 640KB-1MB using fixed MTRRs ### @@ -47,24 +47,24 @@ option CONFIG_IOAPIC=1 ### CPU identification depends on only variable MTRRs ### being enabled. ### -#option MEMORY_HOLE=0 +#option CONFIG_MEMORY_HOLE=0 # ### ### Clean up the motherboard id strings ### -option MAINBOARD_PART_NUMBER="DK8X" -option MAINBOARD_VENDOR="IWILL" +option CONFIG_MAINBOARD_PART_NUMBER="DK8X" +option CONFIG_MAINBOARD_VENDOR="IWILL" # ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -#option FALLBACK_SIZE=524288 -#option FALLBACK_SIZE=98304 -option FALLBACK_SIZE=131072 +#option CONFIG_FALLBACK_SIZE=524288 +#option CONFIG_FALLBACK_SIZE=98304 +option CONFIG_FALLBACK_SIZE=131072 -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -option ROM_IMAGE_SIZE=65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +option CONFIG_ROM_IMAGE_SIZE=65536 ### @@ -77,7 +77,7 @@ option ROM_IMAGE_SIZE=65536 #option CONFIG_COMPRESS=1 option CONFIG_CONSOLE_SERIAL8250=1 -option TTYS0_BAUD=115200 +option CONFIG_TTYS0_BAUD=115200 ## ### Select the coreboot loglevel @@ -89,30 +89,30 @@ option TTYS0_BAUD=115200 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -option DEFAULT_CONSOLE_LOGLEVEL=7 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 ## At a maximum only compile in this level of debugging -option MAXIMUM_CONSOLE_LOGLEVEL=7 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=7 -#option DEBUG=1 +#option CONFIG_DEBUG=1 # ## Coreboot C code runs at this location in RAM -option _RAMBASE=0x004000 +option CONFIG_RAMBASE=0x004000 ## ## Use a 32K stack ## -option STACK_SIZE=0x8000 +option CONFIG_STACK_SIZE=0x8000 ## ## Use a 56K heap ## -option HEAP_SIZE=0xe000 +option CONFIG_HEAP_SIZE=0xe000 # ### @@ -125,22 +125,22 @@ option CONFIG_ROM_PAYLOAD = 1 # romimage "normal" # 48K for SCSI FW -# option ROM_SIZE = 512*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" - option USE_FALLBACK_IMAGE=0 - option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - option ROM_SECTION_OFFSET= 0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_SECTION_SIZE = (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE) + option CONFIG_ROM_SECTION_OFFSET= 0 - option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) - option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - option _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) + option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE) + option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) + option CONFIG_ROMBASE = (CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE) -# option XIP_ROM_SIZE = FALLBACK_SIZE - option XIP_ROM_SIZE = 65536 +# option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE + option CONFIG_XIP_ROM_SIZE = 65536 - option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) + option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE) payload /usr/src/filo-0.4.1_btext/filo.elf # payload /usr/src/filo-0.4.2/filo.elf @@ -148,20 +148,20 @@ end romimage "fallback" option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_SECTION_SIZE = FALLBACK_SIZE - option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE) + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE + option CONFIG_ROM_SECTION_OFFSET= (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE) - option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) - option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - option _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) + option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE) + option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) + option CONFIG_ROMBASE = (CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE) -# option XIP_ROM_SIZE = FALLBACK_SIZE - option XIP_ROM_SIZE = 65536 - option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +# option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE + option CONFIG_XIP_ROM_SIZE = 65536 + option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE) payload ../../../payloads/filo.elf # payload /usr/src/filo-0.4.2/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/jetway/j7f24/Config-abuild.lb b/targets/jetway/j7f24/Config-abuild.lb index d364cb7cbd..2a65acae0d 100644 --- a/targets/jetway/j7f24/Config-abuild.lb +++ b/targets/jetway/j7f24/Config-abuild.lb @@ -4,18 +4,18 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ -option ROM_SIZE=512*1024 +option CONFIG_ROM_SIZE=512*1024 romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/jetway/j7f24/Config.lb b/targets/jetway/j7f24/Config.lb index 268873d07a..52a1108ee3 100644 --- a/targets/jetway/j7f24/Config.lb +++ b/targets/jetway/j7f24/Config.lb @@ -22,24 +22,24 @@ target jetway-j7f24 mainboard jetway/j7f24 -option MAXIMUM_CONSOLE_LOGLEVEL=8 -option DEFAULT_CONSOLE_LOGLEVEL=8 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 option CONFIG_CONSOLE_SERIAL8250=1 # coreboot C code runs at this location in RAM -option _RAMBASE=0x00004000 +option CONFIG_RAMBASE=0x00004000 # # If space is allotted for a VGA BIOS, # generate the final ROM like this: # cat vgabios bochsbios coreboot.rom > coreboot.rom.final # -#option ROM_SIZE = (512 * 1024) - (63 * 1024) - (64 * 1024) -option ROM_SIZE = (512 * 1024) +#option CONFIG_ROM_SIZE = (512 * 1024) - (63 * 1024) - (64 * 1024) +option CONFIG_ROM_SIZE = (512 * 1024) romimage "image" option COREBOOT_EXTRA_VERSION = "-j7f24" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "image" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "image" diff --git a/targets/kontron/986lcd-m/Config-abuild.lb b/targets/kontron/986lcd-m/Config-abuild.lb index c5bb2c0d28..ac903d16e9 100644 --- a/targets/kontron/986lcd-m/Config-abuild.lb +++ b/targets/kontron/986lcd-m/Config-abuild.lb @@ -4,26 +4,26 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ -option ROM_SIZE=1024*1024 +option CONFIG_ROM_SIZE=1024*1024 romimage "normal" - option USE_FALLBACK_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=1 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" #pci_rom ../../../misc/kontron-pci8086,27a2.rom vendor_id=0x8086 device_id=0x27a2 diff --git a/targets/kontron/986lcd-m/Config.lb b/targets/kontron/986lcd-m/Config.lb index 8d1a1fd5a8..08f2836bf9 100644 --- a/targets/kontron/986lcd-m/Config.lb +++ b/targets/kontron/986lcd-m/Config.lb @@ -1,16 +1,16 @@ target kontron_986lcd_m mainboard kontron/986lcd-m -## ROM_SIZE is the total number of bytes allocated for coreboot use +## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use ## (normal AND fallback images and payloads). -option ROM_SIZE = 1024 * 1024 +option CONFIG_ROM_SIZE = 1024 * 1024 romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" # Uncomment this and fix the path to your VGA BIOS blob (~/amipci_01.20 here) for on-board VGA support. # See http://www.coreboot.org/Kontron_986LCD-M_mITX for details. diff --git a/targets/lippert/frontrunner/Config.lb b/targets/lippert/frontrunner/Config.lb index e2162685cf..cee55cdd55 100644 --- a/targets/lippert/frontrunner/Config.lb +++ b/targets/lippert/frontrunner/Config.lb @@ -4,11 +4,11 @@ target frontrunner mainboard lippert/frontrunner -option ROM_SIZE=256*1024 +option CONFIG_ROM_SIZE=256*1024 romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x16000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x16000 option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -19,8 +19,8 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x16000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x16000 option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -30,4 +30,4 @@ romimage "fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/lippert/roadrunner-lx/Config.lb b/targets/lippert/roadrunner-lx/Config.lb index 0d01da8652..130849c746 100644 --- a/targets/lippert/roadrunner-lx/Config.lb +++ b/targets/lippert/roadrunner-lx/Config.lb @@ -35,28 +35,28 @@ option CONFIG_COMPRESSED_PAYLOAD_LZMA = 0 #option CONFIG_IDE = 1 #option CONFIG_FS_PAYLOAD = 1 #option CONFIG_FS_EXT2 = 1 -#option AUTOBOOT_DELAY = 0 -#option AUTOBOOT_CMDLINE = "hda1:/payload.elf" +#option CONFIG_AUTOBOOT_DELAY = 0 +#option CONFIG_AUTOBOOT_CMDLINE = "hda1:/payload.elf" # Leave 36k for VSA. Usually board is equipped with a 512 KB FWH (LPC) flash, # however it can be replaced with a 1 MB chip. -option ROM_SIZE = (512 * 1024) - (36 * 1024) -#option ROM_SIZE = (1024 * 1024) - (36 * 1024) -option FALLBACK_SIZE = ROM_SIZE +option CONFIG_ROM_SIZE = (512 * 1024) - (36 * 1024) +#option CONFIG_ROM_SIZE = (1024 * 1024) - (36 * 1024) +option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE -#option DEFAULT_CONSOLE_LOGLEVEL = 4 -#option MAXIMUM_CONSOLE_LOGLEVEL = 4 +#option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 4 +#option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 4 -# Saves space on ROM_IMAGE_SIZE, but decompression costs a second on boot. +# Saves space on CONFIG_ROM_IMAGE_SIZE, but decompression costs a second on boot. option CONFIG_COMPRESS = 1 romimage "image" - option USE_FALLBACK_IMAGE = 1 - option ROM_IMAGE_SIZE = 64 * 1024 + option CONFIG_USE_FALLBACK_IMAGE = 1 + option CONFIG_ROM_IMAGE_SIZE = 64 * 1024 option COREBOOT_EXTRA_VERSION = ".0" payload ../payload.elf # If getting payload from IDE # payload /dev/null end -buildrom ./coreboot.rom ROM_SIZE "image" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "image" diff --git a/targets/lippert/spacerunner-lx/Config.lb b/targets/lippert/spacerunner-lx/Config.lb index a29202d8fa..d7b1d7916f 100644 --- a/targets/lippert/spacerunner-lx/Config.lb +++ b/targets/lippert/spacerunner-lx/Config.lb @@ -36,27 +36,27 @@ option CONFIG_COMPRESSED_PAYLOAD_LZMA = 0 #option CONFIG_IDE = 1 #option CONFIG_FS_PAYLOAD = 1 #option CONFIG_FS_EXT2 = 1 -#option AUTOBOOT_DELAY = 0 -#option AUTOBOOT_CMDLINE = "hda1:/payload.elf" +#option CONFIG_AUTOBOOT_DELAY = 0 +#option CONFIG_AUTOBOOT_CMDLINE = "hda1:/payload.elf" # Leave 36k for VSA. Board is equipped with a 1 MB SPI flash, however, due to # limitations of the IT8712F Super I/O, only the top 512 KB are directly mapped. -option ROM_SIZE = (512 * 1024) - (36 * 1024) -option FALLBACK_SIZE = ROM_SIZE +option CONFIG_ROM_SIZE = (512 * 1024) - (36 * 1024) +option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE -#option DEFAULT_CONSOLE_LOGLEVEL = 4 -#option MAXIMUM_CONSOLE_LOGLEVEL = 4 +#option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 4 +#option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 4 -# Saves space on ROM_IMAGE_SIZE, but decompression costs a second on boot. +# Saves space on CONFIG_ROM_IMAGE_SIZE, but decompression costs a second on boot. option CONFIG_COMPRESS = 1 romimage "image" - option USE_FALLBACK_IMAGE = 1 - option ROM_IMAGE_SIZE = 64 * 1024 + option CONFIG_USE_FALLBACK_IMAGE = 1 + option CONFIG_ROM_IMAGE_SIZE = 64 * 1024 option COREBOOT_EXTRA_VERSION = ".0" payload ../payload.elf # If getting payload from IDE # payload /dev/null end -buildrom ./coreboot.rom ROM_SIZE "image" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "image" diff --git a/targets/momentum/apache/Config.lb b/targets/momentum/apache/Config.lb index f3d3d6da3d..5d0fd32484 100644 --- a/targets/momentum/apache/Config.lb +++ b/targets/momentum/apache/Config.lb @@ -8,21 +8,21 @@ mainboard momentum/apache # Apache Demo Board romimage "normal" ## Base of ROM - option _ROMBASE=0xfff00000 + option CONFIG_ROMBASE=0xfff00000 ## Apache reset vector - option _RESET=_ROMBASE+0x100 + option CONFIG_RESET=CONFIG_ROMBASE+0x100 ## Exception vectors (other than reset vector) - option _EXCEPTION_VECTORS=_RESET+0x100 + option CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100 ## Start of coreboot in the boot rom - ## = _RESET + exeception vector table size - option _ROMSTART=_RESET+0x3100 + ## = CONFIG_RESET + exeception vector table size + option CONFIG_ROMSTART=CONFIG_RESET+0x3100 ## Coreboot C code runs at this location in RAM - option _RAMBASE=0x00100000 - option _RAMSTART=0x00100000 + option CONFIG_RAMBASE=0x00100000 + option CONFIG_RAMSTART=0x00100000 end -buildrom ./coreboot.rom ROM_SIZE "normal" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" diff --git a/targets/motorola/sandpoint/Config.lb b/targets/motorola/sandpoint/Config.lb index d70562328f..7ef1668969 100644 --- a/targets/motorola/sandpoint/Config.lb +++ b/targets/motorola/sandpoint/Config.lb @@ -9,23 +9,23 @@ mainboard motorola/sandpointx3_altimus_mpc7410 # Sandpoint Demo Board romimage "normal" ## Base of ROM - option _ROMBASE=0xfff00000 + option CONFIG_ROMBASE=0xfff00000 ## Sandpoint reset vector - option _RESET=_ROMBASE+0x100 + option CONFIG_RESET=CONFIG_ROMBASE+0x100 ## Exception vectors (other than reset vector) - option _EXCEPTION_VECTORS=_RESET+0x100 + option CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100 ## Start of coreboot in the boot rom - ## = _RESET + exeception vector table size - option _ROMSTART=_RESET+0x3100 + ## = CONFIG_RESET + exeception vector table size + option CONFIG_ROMSTART=CONFIG_RESET+0x3100 ## Coreboot C code runs at this location in RAM - option _RAMBASE=0x00100000 - option _RAMSTART=0x00100000 + option CONFIG_RAMBASE=0x00100000 + option CONFIG_RAMSTART=0x00100000 option CONFIG_SANDPOINT_ALTIMUS=1 end -buildrom ./coreboot.rom ROM_SIZE "normal" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" diff --git a/targets/motorola/sandpoint/Config.lb.ide_stream b/targets/motorola/sandpoint/Config.lb.ide_stream index 04b2591584..6649c092ae 100644 --- a/targets/motorola/sandpoint/Config.lb.ide_stream +++ b/targets/motorola/sandpoint/Config.lb.ide_stream @@ -6,32 +6,32 @@ loadoptions target sandpoint -uses CROSS_COMPILE -uses HAVE_OPTION_TABLE +uses CONFIG_CROSS_COMPILE +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_SANDPOINT_ALTIMUS uses CONFIG_COMPRESS -uses DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_USE_INIT uses CONFIG_CHIP_CONFIGURE -uses NO_POST +uses CONFIG_NO_POST uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BASE +uses CONFIG_TTYS0_BASE uses CONFIG_IDE_PAYLOAD -uses IDE_BOOT_DRIVE -uses IDE_SWAB IDE_OFFSET -uses ROM_SIZE -uses _RESET -uses _EXCEPTION_VECTORS -uses _ROMBASE -uses _ROMSTART -uses _RAMBASE -uses _RAMSTART -uses STACK_SIZE -uses HEAP_SIZE +uses CONFIG_IDE_BOOT_DRIVE +uses CONFIG_IDE_SWAB CONFIG_IDE_OFFSET +uses CONFIG_ROM_SIZE +uses CONFIG_RESET +uses CONFIG_EXCEPTION_VECTORS +uses CONFIG_ROMBASE +uses CONFIG_ROMSTART +uses CONFIG_RAMBASE +uses CONFIG_RAMSTART +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE ## use a cross compiler -#option CROSS_COMPILE="powerpc-eabi-" -#option CROSS_COMPILE="ppc_74xx-" +#option CONFIG_CROSS_COMPILE="powerpc-eabi-" +#option CONFIG_CROSS_COMPILE="ppc_74xx-" ## Use stage 1 initialization code option CONFIG_USE_INIT=1 @@ -43,48 +43,48 @@ option CONFIG_CHIP_CONFIGURE=1 option CONFIG_COMPRESS=0 ## Turn off POST codes -option NO_POST=1 +option CONFIG_NO_POST=1 ## Enable serial console -option DEFAULT_CONSOLE_LOGLEVEL=8 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 option CONFIG_CONSOLE_SERIAL8250=1 -option TTYS0_BASE=0x3f8 +option CONFIG_TTYS0_BASE=0x3f8 ## Boot linux from IDE option CONFIG_IDE_PAYLOAD=1 -option IDE_BOOT_DRIVE=0 -option IDE_SWAB=1 -option IDE_OFFSET=0 +option CONFIG_IDE_BOOT_DRIVE=0 +option CONFIG_IDE_SWAB=1 +option CONFIG_IDE_OFFSET=0 # ROM is 1Mb -option ROM_SIZE=1024*1024 +option CONFIG_ROM_SIZE=1024*1024 # Set stack and heap sizes (stage 2) -option STACK_SIZE=0x10000 -option HEAP_SIZE=0x10000 +option CONFIG_STACK_SIZE=0x10000 +option CONFIG_HEAP_SIZE=0x10000 # Sandpoint Demo Board romimage "normal" ## Base of ROM - option _ROMBASE=0xfff00000 + option CONFIG_ROMBASE=0xfff00000 ## Sandpoint reset vector - option _RESET=_ROMBASE+0x100 + option CONFIG_RESET=CONFIG_ROMBASE+0x100 ## Exception vectors (other than reset vector) - option _EXCEPTION_VECTORS=_RESET+0x100 + option CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100 ## Start of coreboot in the boot rom - ## = _RESET + exeception vector table size - option _ROMSTART=_RESET+0x3100 + ## = CONFIG_RESET + exeception vector table size + option CONFIG_ROMSTART=CONFIG_RESET+0x3100 ## Coreboot C code runs at this location in RAM - option _RAMBASE=0x00100000 - option _RAMSTART=0x00100000 + option CONFIG_RAMBASE=0x00100000 + option CONFIG_RAMSTART=0x00100000 option CONFIG_SANDPOINT_ALTIMUS=1 mainboard motorola/sandpoint end -buildrom ./coreboot.rom ROM_SIZE "normal" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" diff --git a/targets/msi/ms6119/Config.lb b/targets/msi/ms6119/Config.lb index 5f05bca879..271b7f0483 100644 --- a/targets/msi/ms6119/Config.lb +++ b/targets/msi/ms6119/Config.lb @@ -21,29 +21,29 @@ target ms6119 mainboard msi/ms6119 -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 -option MAINBOARD_VENDOR = "MSI" -option MAINBOARD_PART_NUMBER = "MS-6119" +option CONFIG_MAINBOARD_VENDOR = "MSI" +option CONFIG_MAINBOARD_PART_NUMBER = "MS-6119" -option IRQ_SLOT_COUNT = 7 +option CONFIG_IRQ_SLOT_COUNT = 7 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/msi/ms6147/Config.lb b/targets/msi/ms6147/Config.lb index b639587ee6..02a603557f 100644 --- a/targets/msi/ms6147/Config.lb +++ b/targets/msi/ms6147/Config.lb @@ -21,29 +21,29 @@ target ms6147 mainboard msi/ms6147 -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 -option MAINBOARD_VENDOR = "MSI" -option MAINBOARD_PART_NUMBER = "MS-6147" +option CONFIG_MAINBOARD_VENDOR = "MSI" +option CONFIG_MAINBOARD_PART_NUMBER = "MS-6147" -option IRQ_SLOT_COUNT = 8 +option CONFIG_IRQ_SLOT_COUNT = 8 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".Normal" payload ../payload.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".Fallback" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/msi/ms6178/Config.lb b/targets/msi/ms6178/Config.lb index 1276c88a77..d302f85998 100644 --- a/targets/msi/ms6178/Config.lb +++ b/targets/msi/ms6178/Config.lb @@ -21,32 +21,32 @@ target ms6178 mainboard msi/ms6178 -option ROM_SIZE = 512 * 1024 +option CONFIG_ROM_SIZE = 512 * 1024 -option MAINBOARD_VENDOR = "MSI" -option MAINBOARD_PART_NUMBER = "MS-6178" +option CONFIG_MAINBOARD_VENDOR = "MSI" +option CONFIG_MAINBOARD_PART_NUMBER = "MS-6178" -option IRQ_SLOT_COUNT = 4 +option CONFIG_IRQ_SLOT_COUNT = 4 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" # pci_rom i810.vga vendor_id=0x8086 device_id=0x7120 diff --git a/targets/msi/ms7135/Config-abuild.lb b/targets/msi/ms7135/Config-abuild.lb index 88dd1684e3..b1c927705b 100644 --- a/targets/msi/ms7135/Config-abuild.lb +++ b/targets/msi/ms7135/Config-abuild.lb @@ -4,33 +4,33 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "normal" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/msi/ms7135/Config.lb b/targets/msi/ms7135/Config.lb index e56fbff2e0..2d8ea4928a 100644 --- a/targets/msi/ms7135/Config.lb +++ b/targets/msi/ms7135/Config.lb @@ -23,39 +23,39 @@ target ms7135 mainboard msi/ms7135 -option DEFAULT_CONSOLE_LOGLEVEL=8 -option MAXIMUM_CONSOLE_LOGLEVEL=8 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 -option HAVE_PIRQ_TABLE=1 +option CONFIG_HAVE_PIRQ_TABLE=1 option CONFIG_CONSOLE_VGA=1 option CONFIG_PCI_ROM_RUN=1 romimage "normal" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="_Normal" payload /tmp/payload.elf end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="_Fallback" payload /tmp/payload.elf end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="_Failover" end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/msi/ms7260/Config-abuild.lb b/targets/msi/ms7260/Config-abuild.lb index a03aba0f40..f30a9b367e 100644 --- a/targets/msi/ms7260/Config-abuild.lb +++ b/targets/msi/ms7260/Config-abuild.lb @@ -22,37 +22,37 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "normal" - option USE_FAILOVER_IMAGE = 0 - option USE_FALLBACK_IMAGE = 0 - option ROM_IMAGE_SIZE = 128 * 1024 - option XIP_ROM_SIZE = 256 * 1024 + option CONFIG_USE_FAILOVER_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 + option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 + option CONFIG_XIP_ROM_SIZE = 256 * 1024 option COREBOOT_EXTRA_VERSION = ".0Normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FAILOVER_IMAGE = 0 - option USE_FALLBACK_IMAGE = 1 - option ROM_IMAGE_SIZE = 128 * 1024 - option XIP_ROM_SIZE = 256 * 1024 + option CONFIG_USE_FAILOVER_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 1 + option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 + option CONFIG_XIP_ROM_SIZE = 256 * 1024 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload __PAYLOAD__ end romimage "failover" - option USE_FAILOVER_IMAGE = 1 - option USE_FALLBACK_IMAGE = 0 - option ROM_IMAGE_SIZE = FAILOVER_SIZE - option XIP_ROM_SIZE = FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 0 + option CONFIG_ROM_IMAGE_SIZE = CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE = CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION = ".0Failover" end -# buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +# buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/msi/ms7260/Config.lb b/targets/msi/ms7260/Config.lb index 1ef5be266b..04a33ff68b 100644 --- a/targets/msi/ms7260/Config.lb +++ b/targets/msi/ms7260/Config.lb @@ -21,38 +21,38 @@ target ms7260 mainboard msi/ms7260 -option ROM_SIZE = 512 * 1024 +option CONFIG_ROM_SIZE = 512 * 1024 option CONFIG_COMPRESSED_PAYLOAD_NRV2B = 1 # NRV2B compression # option CONFIG_COMPRESSED_PAYLOAD_LZMA = 1 # LZMA compression romimage "normal" - option USE_FAILOVER_IMAGE = 0 - option USE_FALLBACK_IMAGE = 0 - option ROM_IMAGE_SIZE = 128 * 1024 - option XIP_ROM_SIZE = 256 * 1024 + option CONFIG_USE_FAILOVER_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 + option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 + option CONFIG_XIP_ROM_SIZE = 256 * 1024 option COREBOOT_EXTRA_VERSION = ".0Normal" # payload /tmp/filo.elf payload ../payload.elf end romimage "fallback" - option USE_FAILOVER_IMAGE = 0 - option USE_FALLBACK_IMAGE = 1 - option ROM_IMAGE_SIZE = 128 * 1024 - option XIP_ROM_SIZE = 256 * 1024 + option CONFIG_USE_FAILOVER_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 1 + option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 + option CONFIG_XIP_ROM_SIZE = 256 * 1024 option COREBOOT_EXTRA_VERSION = ".0Fallback" # payload /tmp/filo.elf payload ../payload.elf end romimage "failover" - option USE_FAILOVER_IMAGE = 1 - option USE_FALLBACK_IMAGE = 0 - option ROM_IMAGE_SIZE = FAILOVER_SIZE - option XIP_ROM_SIZE = FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 0 + option CONFIG_ROM_IMAGE_SIZE = CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE = CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION = ".0Failover" end -# buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +# buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/msi/ms9185/Config-abuild.lb b/targets/msi/ms9185/Config-abuild.lb index b136df4768..3baa41a42a 100644 --- a/targets/msi/ms9185/Config-abuild.lb +++ b/targets/msi/ms9185/Config-abuild.lb @@ -4,23 +4,23 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE = 128 * 1024 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE = 128 * 1024 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/msi/ms9185/Config.lb b/targets/msi/ms9185/Config.lb index e77a42c6bd..a7cf3f135f 100644 --- a/targets/msi/ms9185/Config.lb +++ b/targets/msi/ms9185/Config.lb @@ -29,17 +29,17 @@ mainboard msi/ms9185 # ms9185 romimage "normal" # 36k for ATI option rom - option ROM_SIZE = 512*1024-36*1024 -# option ROM_SIZE = 524288 -# option ROM_SIZE = 425984 + option CONFIG_ROM_SIZE = 512*1024-36*1024 +# option CONFIG_ROM_SIZE = 524288 +# option CONFIG_ROM_SIZE = 425984 # 64K for Etherboot -# option ROM_SIZE = 458752 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x18800 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x40000 +# option CONFIG_ROM_SIZE = 458752 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x18800 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -62,12 +62,12 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x19800 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x40000 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x19800 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -91,4 +91,4 @@ romimage "fallback" # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/msi/ms9282/Config-abuild.lb b/targets/msi/ms9282/Config-abuild.lb index b136df4768..3baa41a42a 100644 --- a/targets/msi/ms9282/Config-abuild.lb +++ b/targets/msi/ms9282/Config-abuild.lb @@ -4,23 +4,23 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE = 128 * 1024 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE = 128 * 1024 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/msi/ms9282/Config.lb b/targets/msi/ms9282/Config.lb index 0e78424a48..0f3c87ed32 100644 --- a/targets/msi/ms9282/Config.lb +++ b/targets/msi/ms9282/Config.lb @@ -24,19 +24,19 @@ mainboard msi/ms9282 romimage "normal" # 48K for SCSI FW -# option ROM_SIZE = 475136 - option ROM_SIZE = 512*1024-36*1024 -# option ROM_SIZE = 524288 +# option CONFIG_ROM_SIZE = 475136 + option CONFIG_ROM_SIZE = 512*1024-36*1024 +# option CONFIG_ROM_SIZE = 524288 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 425984 +# option CONFIG_ROM_SIZE = 425984 # 64K for Etherboot -# option ROM_SIZE = 458752 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x18800 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x40000 +# option CONFIG_ROM_SIZE = 458752 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x18800 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -59,12 +59,12 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x19800 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x40000 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x19800 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -88,4 +88,4 @@ romimage "fallback" # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/nec/powermate2000/Config.lb b/targets/nec/powermate2000/Config.lb index dbb40ebc0d..72e29cc9a1 100644 --- a/targets/nec/powermate2000/Config.lb +++ b/targets/nec/powermate2000/Config.lb @@ -21,29 +21,29 @@ target powermate2000 mainboard nec/powermate2000 -option ROM_SIZE = 512 * 1024 +option CONFIG_ROM_SIZE = 512 * 1024 -option MAINBOARD_VENDOR = "NEC" -option MAINBOARD_PART_NUMBER = "PowerMate 2000" +option CONFIG_MAINBOARD_VENDOR = "NEC" +option CONFIG_MAINBOARD_PART_NUMBER = "PowerMate 2000" -option IRQ_SLOT_COUNT = 5 +option CONFIG_IRQ_SLOT_COUNT = 5 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload ../payload.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/newisys/khepri/Config.lb b/targets/newisys/khepri/Config.lb index 04bea9b890..d624b9c46b 100644 --- a/targets/newisys/khepri/Config.lb +++ b/targets/newisys/khepri/Config.lb @@ -12,34 +12,34 @@ option CC="gcc -m32" # Configuration options. -option MAXIMUM_CONSOLE_LOGLEVEL=8 -option DEFAULT_CONSOLE_LOGLEVEL=8 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 option CONFIG_CONSOLE_SERIAL8250=1 # Size of the image. Khepri comes with 512k per default. -option ROM_SIZE=512*1024 +option CONFIG_ROM_SIZE=512*1024 -option HAVE_OPTION_TABLE=1 +option CONFIG_HAVE_OPTION_TABLE=1 option CONFIG_ROM_PAYLOAD=1 -option HAVE_FALLBACK_BOOT=1 +option CONFIG_HAVE_FALLBACK_BOOT=1 -option FALLBACK_SIZE=131072 +option CONFIG_FALLBACK_SIZE=131072 ## Coreboot C code runs at this location in RAM -option _RAMBASE=0x00004000 +option CONFIG_RAMBASE=0x00004000 romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="-Khepri-Normal" payload ../../../payloads/tg3--ide_disk.zelf end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="-Khepri-Fallback" payload ../../../payloads/tg3--ide_disk.zelf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/nvidia/l1_2pvv/Config-abuild.lb b/targets/nvidia/l1_2pvv/Config-abuild.lb index 88dd1684e3..b1c927705b 100644 --- a/targets/nvidia/l1_2pvv/Config-abuild.lb +++ b/targets/nvidia/l1_2pvv/Config-abuild.lb @@ -4,33 +4,33 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "normal" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/nvidia/l1_2pvv/Config.lb b/targets/nvidia/l1_2pvv/Config.lb index c6d546ed83..87171a7449 100644 --- a/targets/nvidia/l1_2pvv/Config.lb +++ b/targets/nvidia/l1_2pvv/Config.lb @@ -29,20 +29,20 @@ mainboard nvidia/l1_2pvv # serengeti_leopard romimage "normal" # 48K for SCSI FW -# option ROM_SIZE = 475136 +# option CONFIG_ROM_SIZE = 475136 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 425984 +# option CONFIG_ROM_SIZE = 425984 # 64K for Etherboot -# option ROM_SIZE = 458752 +# option CONFIG_ROM_SIZE = 458752 # 44k for atixx.rom -# option ROM_SIZE = 479232 - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x18800 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x40000 +# option CONFIG_ROM_SIZE = 479232 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x18800 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -64,13 +64,13 @@ romimage "normal" end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x19800 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x40000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x19800 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -97,12 +97,12 @@ romimage "fallback" end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/nvidia/l1_2pvv/Config.lb.kernel b/targets/nvidia/l1_2pvv/Config.lb.kernel index a0a16cf53e..70e95e4230 100644 --- a/targets/nvidia/l1_2pvv/Config.lb.kernel +++ b/targets/nvidia/l1_2pvv/Config.lb.kernel @@ -26,19 +26,19 @@ target l1_2pvv mainboard nvidia/l1_2pvv -option ROM_SIZE=0x200000 -option FALLBACK_SIZE=(ROM_SIZE-0x1000) +option CONFIG_ROM_SIZE=0x200000 +option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x1000) romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 option CONFIG_PRECOMPRESSED_PAYLOAD=1 -# option ROM_IMAGE_SIZE=0x19800 - option ROM_IMAGE_SIZE=0x17000 -# option ROM_IMAGE_SIZE=0x15800 -# option ROM_IMAGE_SIZE=0x13800 - option XIP_ROM_SIZE=0x40000 +# option CONFIG_ROM_IMAGE_SIZE=0x19800 + option CONFIG_ROM_IMAGE_SIZE=0x17000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -67,13 +67,13 @@ romimage "fallback" end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover" +#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/olpc/btest/Config.lb b/targets/olpc/btest/Config.lb index 3789519f91..df9d0fec91 100644 --- a/targets/olpc/btest/Config.lb +++ b/targets/olpc/btest/Config.lb @@ -9,16 +9,16 @@ mainboard olpc/btest #option CONFIG_PRECOMPRESSED_PAYLOAD=0 # leave 64k for vsa and 64k for EC code -option ROM_SIZE=(1024*1024)-(64*1024)-(64*1024) -option FALLBACK_SIZE=ROM_SIZE +option CONFIG_ROM_SIZE=(1024*1024)-(64*1024)-(64*1024) +option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE -option DEFAULT_CONSOLE_LOGLEVEL = 3 -option MAXIMUM_CONSOLE_LOGLEVEL = 3 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 3 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 3 romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=32*1024 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=32*1024 option COREBOOT_EXTRA_VERSION=".0Fallback" payload /tmp/olpcpayload.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/olpc/rev_a/Config.1M.lb b/targets/olpc/rev_a/Config.1M.lb index cacc9a030f..bd7d4bb1ef 100644 --- a/targets/olpc/rev_a/Config.1M.lb +++ b/targets/olpc/rev_a/Config.1M.lb @@ -8,16 +8,16 @@ mainboard olpc/rev_a #option CONFIG_PRECOMPRESSED_PAYLOAD=1 # leave 64k for vsa -option ROM_SIZE=(1024*1024)-(64*1024) -option FALLBACK_SIZE=ROM_SIZE +option CONFIG_ROM_SIZE=(1024*1024)-(64*1024) +option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=32*1024 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=32*1024 option COREBOOT_EXTRA_VERSION=".0Fallback" payload /tmp/olpcpayload.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/olpc/rev_a/Config.SPI.lb b/targets/olpc/rev_a/Config.SPI.lb index fa3593a8e6..70e45223cd 100644 --- a/targets/olpc/rev_a/Config.SPI.lb +++ b/targets/olpc/rev_a/Config.SPI.lb @@ -9,16 +9,16 @@ mainboard olpc/rev_a #option CONFIG_PRECOMPRESSED_PAYLOAD=0 # leave 64k for vsa and 64k for EC code -option ROM_SIZE=(1024*1024)-(64*1024)-(64*1024) -option FALLBACK_SIZE=ROM_SIZE +option CONFIG_ROM_SIZE=(1024*1024)-(64*1024)-(64*1024) +option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=32*1024 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=32*1024 option COREBOOT_EXTRA_VERSION=".0Fallback" payload /tmp/olpcpayload.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/olpc/rev_a/Config.kernel.lb b/targets/olpc/rev_a/Config.kernel.lb index ed612f7e90..15b5a6f32c 100644 --- a/targets/olpc/rev_a/Config.kernel.lb +++ b/targets/olpc/rev_a/Config.kernel.lb @@ -3,12 +3,12 @@ target rev_a mainboard olpc/rev_a -option ROM_SIZE=7*128*1024 -option FALLBACK_SIZE=ROM_SIZE +option CONFIG_ROM_SIZE=7*128*1024 +option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE #romimage "normal" -# option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x10000 +# option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x10000 # option COREBOOT_EXTRA_VERSION=".0Normal" ## payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf ## payload ../../../../tg3--ide_disk.zelf @@ -19,8 +19,8 @@ option FALLBACK_SIZE=ROM_SIZE #end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -31,5 +31,5 @@ romimage "fallback" payload /tmp/olpc end -buildrom ./coreboot.rom ROM_SIZE "fallback" -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" +#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/olpc/rev_a/Config.lb b/targets/olpc/rev_a/Config.lb index b570c66bcc..28258770a1 100644 --- a/targets/olpc/rev_a/Config.lb +++ b/targets/olpc/rev_a/Config.lb @@ -5,16 +5,16 @@ mainboard olpc/rev_a # leave 64k for vsa option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 -option ROM_SIZE=512*1024-64*1024 -option FALLBACK_SIZE=ROM_SIZE +option CONFIG_ROM_SIZE=512*1024-64*1024 +option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=32*1024 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=32*1024 option COREBOOT_EXTRA_VERSION=".0Fallback" payload /tmp/olpcpayload.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/pcengines/alix1c/Config.lb b/targets/pcengines/alix1c/Config.lb index 82415e0269..2c7a376f3a 100644 --- a/targets/pcengines/alix1c/Config.lb +++ b/targets/pcengines/alix1c/Config.lb @@ -3,23 +3,23 @@ mainboard pcengines/alix1c option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 -## ROM_SIZE is the total number of bytes allocated for coreboot use +## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use ## (normal AND fallback images and payloads). Leave 36k for VSA. -option ROM_SIZE = (512 * 1024) - (36 * 1024) +option CONFIG_ROM_SIZE = (512 * 1024) - (36 * 1024) -## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, +## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, ## not including any payload. -option ROM_IMAGE_SIZE = (64 * 1024) +option CONFIG_ROM_IMAGE_SIZE = (64 * 1024) -option FALLBACK_SIZE = ROM_SIZE +option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE -option DEFAULT_CONSOLE_LOGLEVEL = 3 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 3 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/rca/rm4100/Config-abuild.lb b/targets/rca/rm4100/Config-abuild.lb index 8162eca6be..d7c1ec2c18 100644 --- a/targets/rca/rm4100/Config-abuild.lb +++ b/targets/rca/rm4100/Config-abuild.lb @@ -22,16 +22,16 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/rca/rm4100/Config.lb b/targets/rca/rm4100/Config.lb index 7df9899f3c..7d17739a00 100644 --- a/targets/rca/rm4100/Config.lb +++ b/targets/rca/rm4100/Config.lb @@ -25,9 +25,9 @@ mainboard rca/rm4100 ## Total number of bytes allocated for coreboot use ## (fallback images and payloads). ## -# option ROM_SIZE = 1024 * 1024 +# option CONFIG_ROM_SIZE = 1024 * 1024 ## For VGA BIOS (-64k) -option ROM_SIZE = (1024 * 1024) - (64 * 1024) +option CONFIG_ROM_SIZE = (1024 * 1024) - (64 * 1024) ## ## VGA Console @@ -51,14 +51,14 @@ option CONFIG_VIDEO_MB = 8 ## ## Request this level of debugging output ## -option DEFAULT_CONSOLE_LOGLEVEL = 7 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 7 romimage "fallback" - option USE_FALLBACK_IMAGE = 1 - option FALLBACK_SIZE = ROM_SIZE + option CONFIG_USE_FALLBACK_IMAGE = 1 + option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE option COREBOOT_EXTRA_VERSION = "_RM4100" payload /tmp/filo.elf # payload /tmp/eb-5.4.3-eepro100.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/soyo/sy-6ba-plus-iii/Config.lb b/targets/soyo/sy-6ba-plus-iii/Config.lb index 05e9be4698..98bd66666e 100644 --- a/targets/soyo/sy-6ba-plus-iii/Config.lb +++ b/targets/soyo/sy-6ba-plus-iii/Config.lb @@ -21,31 +21,31 @@ target sy-6ba-plus-iii mainboard soyo/sy-6ba-plus-iii -option ROM_SIZE = 256 * 1024 -# option FALLBACK_SIZE = ROM_SIZE +option CONFIG_ROM_SIZE = 256 * 1024 +# option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE -option MAINBOARD_VENDOR = "Soyo" -option MAINBOARD_PART_NUMBER = "SY-6BA+ III" +option CONFIG_MAINBOARD_VENDOR = "Soyo" +option CONFIG_MAINBOARD_PART_NUMBER = "SY-6BA+ III" -option IRQ_SLOT_COUNT = 7 +option CONFIG_IRQ_SLOT_COUNT = 7 -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload ../payload.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload ../payload.elf end -# buildrom ./coreboot.rom ROM_SIZE "fallback" -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +# buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/sunw/ultra40/Config.lb b/targets/sunw/ultra40/Config.lb index 4761b3e037..cbd7f9698e 100644 --- a/targets/sunw/ultra40/Config.lb +++ b/targets/sunw/ultra40/Config.lb @@ -5,24 +5,24 @@ target ultra40 mainboard sunw/ultra40 -option ROM_SIZE=512*1024 +option CONFIG_ROM_SIZE=512*1024 # sunw ultra40 romimage "normal" # 48K for SCSI FW -# option ROM_SIZE = 512*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024 # 64K for Etherboot -# option ROM_SIZE = 512*1024-64*1024 +# option CONFIG_ROM_SIZE = 512*1024-64*1024 # 64K for NIC option 48K for Raid option rom -# option ROM_SIZE = 512*1024-64*1024-48*1024 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x15000 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x17800 - option XIP_ROM_SIZE=0x20000 +# option CONFIG_ROM_SIZE = 512*1024-64*1024-48*1024 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x15000 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x17800 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -45,13 +45,13 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x15000 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x17800 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x15000 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x17800 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -70,4 +70,4 @@ romimage "fallback" # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/supermicro/h8dme/Config-abuild.lb b/targets/supermicro/h8dme/Config-abuild.lb index 9720675b80..7e93e76234 100644 --- a/targets/supermicro/h8dme/Config-abuild.lb +++ b/targets/supermicro/h8dme/Config-abuild.lb @@ -4,34 +4,34 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "normal" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION=".0-failover" end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/supermicro/h8dme/Config-lab.lb b/targets/supermicro/h8dme/Config-lab.lb index cb00452669..4f81981b3d 100644 --- a/targets/supermicro/h8dme/Config-lab.lb +++ b/targets/supermicro/h8dme/Config-lab.lb @@ -19,27 +19,27 @@ target h8dmre mainboard supermicro/h8dme -option ROM_SIZE=0x100000 +option CONFIG_ROM_SIZE=0x100000 # 44K for ATI ROM in 1M; 4K for failover -option FALLBACK_SIZE=(ROM_SIZE-0xC000) +option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0xC000) romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 option CONFIG_PRECOMPRESSED_PAYLOAD=1 - option ROM_IMAGE_SIZE=0x18000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_ROM_IMAGE_SIZE=0x18000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ../payload.elf.lzma end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover" diff --git a/targets/supermicro/h8dme/Config.lb b/targets/supermicro/h8dme/Config.lb index de68f38fb7..559371e078 100644 --- a/targets/supermicro/h8dme/Config.lb +++ b/targets/supermicro/h8dme/Config.lb @@ -20,29 +20,29 @@ target h8dme mainboard supermicro/h8dme romimage "normal" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" payload ../payload.elf end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ../payload.elf end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/supermicro/h8dme/Config.lb.kernel b/targets/supermicro/h8dme/Config.lb.kernel index d50f9ed2b0..bf09ee5c68 100644 --- a/targets/supermicro/h8dme/Config.lb.kernel +++ b/targets/supermicro/h8dme/Config.lb.kernel @@ -19,27 +19,27 @@ target h8dme mainboard supermicro/h8dme -option ROM_SIZE=0x200000 -option FALLBACK_SIZE=(ROM_SIZE-0x1000) +option CONFIG_ROM_SIZE=0x200000 +option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x1000) romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 option CONFIG_PRECOMPRESSED_PAYLOAD=1 - option ROM_IMAGE_SIZE=0x18000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_ROM_IMAGE_SIZE=0x18000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover" diff --git a/targets/supermicro/h8dmr/Config-abuild.lb b/targets/supermicro/h8dmr/Config-abuild.lb index 8ee91ab323..683f9704f1 100644 --- a/targets/supermicro/h8dmr/Config-abuild.lb +++ b/targets/supermicro/h8dmr/Config-abuild.lb @@ -4,34 +4,34 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "normal" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION=".0-failover" end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/supermicro/h8dmr/Config-lab.lb b/targets/supermicro/h8dmr/Config-lab.lb index 47cdc6454e..6fcde1fd91 100644 --- a/targets/supermicro/h8dmr/Config-lab.lb +++ b/targets/supermicro/h8dmr/Config-lab.lb @@ -22,27 +22,27 @@ target h8dmr mainboard supermicro/h8dmr -option ROM_SIZE=0x100000 +option CONFIG_ROM_SIZE=0x100000 # 44K for ATI ROM in 1M; 4K for failover -option FALLBACK_SIZE=(ROM_SIZE-0xC000) +option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0xC000) romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 option CONFIG_PRECOMPRESSED_PAYLOAD=1 - option ROM_IMAGE_SIZE=0x18000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_ROM_IMAGE_SIZE=0x18000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ../payload.elf.lzma end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover" diff --git a/targets/supermicro/h8dmr/Config.lb b/targets/supermicro/h8dmr/Config.lb index 7ee6d29c55..37f54c252a 100644 --- a/targets/supermicro/h8dmr/Config.lb +++ b/targets/supermicro/h8dmr/Config.lb @@ -24,43 +24,43 @@ mainboard supermicro/h8dmr romimage "normal" # 48K for SCSI FW -# option ROM_SIZE = 475136 +# option CONFIG_ROM_SIZE = 475136 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 425984 +# option CONFIG_ROM_SIZE = 425984 # 64K for Etherboot -# option ROM_SIZE = 458752 +# option CONFIG_ROM_SIZE = 458752 # 44k for atixx.rom -# option ROM_SIZE = 479232 - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x18800 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x40000 +# option CONFIG_ROM_SIZE = 479232 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x18800 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" payload ../payload.elf end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x19800 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x40000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x19800 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ../payload.elf end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/supermicro/h8dmr/Config.lb.kernel b/targets/supermicro/h8dmr/Config.lb.kernel index 8e8c5a4f9a..4b8cf7c4ed 100644 --- a/targets/supermicro/h8dmr/Config.lb.kernel +++ b/targets/supermicro/h8dmr/Config.lb.kernel @@ -22,19 +22,19 @@ target h8dmr mainboard supermicro/h8dmr -option ROM_SIZE=0x200000 -option FALLBACK_SIZE=(ROM_SIZE-0x1000) +option CONFIG_ROM_SIZE=0x200000 +option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x1000) romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 option CONFIG_PRECOMPRESSED_PAYLOAD=1 -# option ROM_IMAGE_SIZE=0x19800 - option ROM_IMAGE_SIZE=0x18000 -# option ROM_IMAGE_SIZE=0x15800 -# option ROM_IMAGE_SIZE=0x13800 - option XIP_ROM_SIZE=0x40000 +# option CONFIG_ROM_IMAGE_SIZE=0x19800 + option CONFIG_ROM_IMAGE_SIZE=0x18000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -63,13 +63,13 @@ romimage "fallback" end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover" +#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/technexion/tim8690/Config-abuild.lb b/targets/technexion/tim8690/Config-abuild.lb index d425fd5666..4e65fac881 100644 --- a/targets/technexion/tim8690/Config-abuild.lb +++ b/targets/technexion/tim8690/Config-abuild.lb @@ -4,23 +4,23 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/technexion/tim8690/Config.lb b/targets/technexion/tim8690/Config.lb index 80330e48dc..8a25959260 100644 --- a/targets/technexion/tim8690/Config.lb +++ b/targets/technexion/tim8690/Config.lb @@ -5,23 +5,23 @@ mainboard technexion/tim8690 romimage "normal" - option ROM_SIZE = 1024*512 - 55808 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_ROM_SIZE = 1024*512 - 55808 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 payload /home/daniel/mypayloads/link end romimage "fallback" - option FALLBACK_SIZE= 1024*512 - 55808 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_FALLBACK_SIZE= 1024*512 - 55808 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 payload /home/daniel/mypayloads/link end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/technologic/ts5300/Config-abuild.lb b/targets/technologic/ts5300/Config-abuild.lb index 6bd9cd56b7..2b619bf21a 100644 --- a/targets/technologic/ts5300/Config-abuild.lb +++ b/targets/technologic/ts5300/Config-abuild.lb @@ -2,18 +2,18 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "fallback" - option FALLBACK_SIZE = 256 * 1024 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=128 * 1024 # 0x10000 + option CONFIG_FALLBACK_SIZE = 256 * 1024 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=128 * 1024 # 0x10000 option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/technologic/ts5300/Config.lb b/targets/technologic/ts5300/Config.lb index 329d8a81bb..720ff07301 100644 --- a/targets/technologic/ts5300/Config.lb +++ b/targets/technologic/ts5300/Config.lb @@ -4,29 +4,29 @@ target technologic_ts5300 mainboard technologic/ts5300 -option DEFAULT_CONSOLE_LOGLEVEL=3 -option MAXIMUM_CONSOLE_LOGLEVEL=3 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=3 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=3 option CONFIG_COMPRESS=1 #romimage "normal" -# option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x10000 +# option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x10000 # option COREBOOT_EXTRA_VERSION=".0-Normal" # payload /etc/hosts #end romimage "fallback" - option FALLBACK_SIZE = 128 * 1024 -# option ROM_SIZE=512*1024 -# option ROM_SECTION_SIZE=512*1024 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=32 * 1024 # 0x8000 -# option ROM_IMAGE_SIZE=48 * 1024 # 0x8000 -# option ROM_IMAGE_SIZE=64 * 1024 # 0x10000 -# option ROM_IMAGE_SIZE=512 * 1024 # 0x10000 + option CONFIG_FALLBACK_SIZE = 128 * 1024 +# option CONFIG_ROM_SIZE=512*1024 +# option CONFIG_ROM_SECTION_SIZE=512*1024 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=32 * 1024 # 0x8000 +# option CONFIG_ROM_IMAGE_SIZE=48 * 1024 # 0x8000 +# option CONFIG_ROM_IMAGE_SIZE=64 * 1024 # 0x10000 +# option CONFIG_ROM_IMAGE_SIZE=512 * 1024 # 0x10000 # option COREBOOT_EXTRA_VERSION=".0-Fallback" option COREBOOT_EXTRA_VERSION=".0" payload /home/stepan/filo-ts5300.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/televideo/tc7020/Config.lb b/targets/televideo/tc7020/Config.lb index 339d33e0ab..c078209fb0 100644 --- a/targets/televideo/tc7020/Config.lb +++ b/targets/televideo/tc7020/Config.lb @@ -21,7 +21,7 @@ target tc7020 mainboard televideo/tc7020 -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 ## Enable VGA with a splash screen (only 640x480 to run on most monitors). ## We want to support up to 1024x768@16 so we need 2MiB video memory. @@ -31,21 +31,21 @@ option CONFIG_GX1_VIDEOMODE = 0 option CONFIG_SPLASH_GRAPHIC = 1 option CONFIG_VIDEO_MB = 2 -option DEFAULT_CONSOLE_LOGLEVEL = 6 -option MAXIMUM_CONSOLE_LOGLEVEL = 6 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6 romimage "normal" - option USE_FALLBACK_IMAGE = 0 - option ROM_IMAGE_SIZE = 64 * 1024 + option CONFIG_USE_FALLBACK_IMAGE = 0 + option CONFIG_ROM_IMAGE_SIZE = 64 * 1024 option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 - option ROM_IMAGE_SIZE = 64 * 1024 + option CONFIG_USE_FALLBACK_IMAGE = 1 + option CONFIG_ROM_IMAGE_SIZE = 64 * 1024 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/thomson/ip1000/Config-abuild.lb b/targets/thomson/ip1000/Config-abuild.lb index 02175bc26b..bdacc46478 100644 --- a/targets/thomson/ip1000/Config-abuild.lb +++ b/targets/thomson/ip1000/Config-abuild.lb @@ -22,16 +22,16 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/thomson/ip1000/Config.lb b/targets/thomson/ip1000/Config.lb index 44aa77a475..b3d2c3baf8 100644 --- a/targets/thomson/ip1000/Config.lb +++ b/targets/thomson/ip1000/Config.lb @@ -25,9 +25,9 @@ mainboard thomson/ip1000 ## Total number of bytes allocated for coreboot use ## (fallback images and payloads). ## -# option ROM_SIZE = 1024 * 1024 +# option CONFIG_ROM_SIZE = 1024 * 1024 ## For VGA BIOS (-64k) -option ROM_SIZE = (1024 * 1024) - (64 * 1024) +option CONFIG_ROM_SIZE = (1024 * 1024) - (64 * 1024) ## ## VGA Console @@ -51,14 +51,14 @@ option CONFIG_VIDEO_MB = 8 ## ## Request this level of debugging output ## -option DEFAULT_CONSOLE_LOGLEVEL = 7 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 7 romimage "fallback" - option USE_FALLBACK_IMAGE = 1 - option FALLBACK_SIZE = ROM_SIZE + option CONFIG_USE_FALLBACK_IMAGE = 1 + option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE option COREBOOT_EXTRA_VERSION = "_IP1000" payload /tmp/filo.elf # payload /tmp/eb-5.4.3-eepro100.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/totalimpact/briq/Config.lb b/targets/totalimpact/briq/Config.lb index 92288234fe..c352936ba4 100644 --- a/targets/totalimpact/briq/Config.lb +++ b/targets/totalimpact/briq/Config.lb @@ -12,47 +12,47 @@ option CONFIG_USE_INIT=1 option CONFIG_COMPRESS=0 ## Turn off POST codes -option NO_POST=1 +option CONFIG_NO_POST=1 ## Enable serial console -option DEFAULT_CONSOLE_LOGLEVEL=8 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 option CONFIG_CONSOLE_SERIAL8250=1 ## Boot linux from IDE option CONFIG_IDE_PAYLOAD=1 -option IDE_BOOT_DRIVE=0 -option IDE_SWAB=1 -option IDE_OFFSET=0 +option CONFIG_IDE_BOOT_DRIVE=0 +option CONFIG_IDE_SWAB=1 +option CONFIG_IDE_OFFSET=0 # ROM is 1Mb -option ROM_SIZE=1024*1024 +option CONFIG_ROM_SIZE=1024*1024 # Set stack and heap sizes (stage 2) -option STACK_SIZE=0x10000 -option HEAP_SIZE=0x10000 +option CONFIG_STACK_SIZE=0x10000 +option CONFIG_HEAP_SIZE=0x10000 # Sandpoint Demo Board romimage "normal" ## Base of ROM - option _ROMBASE=0xfff00000 + option CONFIG_ROMBASE=0xfff00000 ## Sandpoint reset vector - option _RESET=_ROMBASE+0x100 + option CONFIG_RESET=CONFIG_ROMBASE+0x100 ## Exception vectors (other than reset vector) - option _EXCEPTION_VECTORS=_RESET+0x100 + option CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100 ## Start of coreboot in the boot rom - ## = _RESET + exeception vector table size - option _ROMSTART=_RESET+0x3100 + ## = CONFIG_RESET + exeception vector table size + option CONFIG_ROMSTART=CONFIG_RESET+0x3100 ## Coreboot C code runs at this location in RAM - option _RAMBASE=0x00100000 - option _RAMSTART=0x00100000 + option CONFIG_RAMBASE=0x00100000 + option CONFIG_RAMSTART=0x00100000 option CONFIG_BRIQ_750FX=1 #option CONFIG_BRIQ_7400=1 end -buildrom ./coreboot.rom ROM_SIZE "normal" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" diff --git a/targets/tyan/s1846/Config.lb b/targets/tyan/s1846/Config.lb index dcc48ef1bf..4ebccfc52d 100644 --- a/targets/tyan/s1846/Config.lb +++ b/targets/tyan/s1846/Config.lb @@ -21,31 +21,31 @@ target s1846 mainboard tyan/s1846 -option ROM_SIZE = 256 * 1024 +option CONFIG_ROM_SIZE = 256 * 1024 -option MAINBOARD_VENDOR = "Tyan" -option MAINBOARD_PART_NUMBER = "S1846" +option CONFIG_MAINBOARD_VENDOR = "Tyan" +option CONFIG_MAINBOARD_PART_NUMBER = "S1846" # TODO: Add/fix PIRQ table. -option HAVE_PIRQ_TABLE = 0 -option IRQ_SLOT_COUNT = 0 # FIXME +option CONFIG_HAVE_PIRQ_TABLE = 0 +option CONFIG_IRQ_SLOT_COUNT = 0 # FIXME -option DEFAULT_CONSOLE_LOGLEVEL = 9 -option MAXIMUM_CONSOLE_LOGLEVEL = 9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 romimage "normal" - option USE_FALLBACK_IMAGE = 0 + option CONFIG_USE_FALLBACK_IMAGE = 0 option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE = 1 + option CONFIG_USE_FALLBACK_IMAGE = 1 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/tyan/s2735/Config.lb b/targets/tyan/s2735/Config.lb index cd2f774cee..a67f24f69e 100644 --- a/targets/tyan/s2735/Config.lb +++ b/targets/tyan/s2735/Config.lb @@ -8,14 +8,14 @@ mainboard tyan/s2735 # Tyan s2735 romimage "normal" # 48K for SCSI FW -# option ROM_SIZE = 512*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024 # 64K for Etherboot -# option ROM_SIZE = 512*1024-64*1024 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x11800 - option XIP_ROM_SIZE=0x20000 +# option CONFIG_ROM_SIZE = 512*1024-64*1024 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x11800 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -28,9 +28,9 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x11800 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x11800 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -42,4 +42,4 @@ romimage "fallback" payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/tyan/s2850/Config.lb b/targets/tyan/s2850/Config.lb index 66b873c5e8..f6e6f3cf8c 100644 --- a/targets/tyan/s2850/Config.lb +++ b/targets/tyan/s2850/Config.lb @@ -8,18 +8,18 @@ mainboard tyan/s2850 # Tyan s2850 romimage "normal" # 48K for SCSI FW or ATI ROM - option ROM_SIZE = 512*1024-48*1024 + option CONFIG_ROM_SIZE = 512*1024-48*1024 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024 # 64K for Etherboot -# option ROM_SIZE = 512*1024-64*1024 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x16000 -# option ROM_IMAGE_SIZE=0x17800 -# option ROM_IMAGE_SIZE=0x13c00 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 +# option CONFIG_ROM_SIZE = 512*1024-64*1024 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x16000 +# option CONFIG_ROM_IMAGE_SIZE=0x17800 +# option CONFIG_ROM_IMAGE_SIZE=0x13c00 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -36,13 +36,13 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x16000 -# option ROM_IMAGE_SIZE=0x17800 -# option ROM_IMAGE_SIZE=0x13c00 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x16000 +# option CONFIG_ROM_IMAGE_SIZE=0x17800 +# option CONFIG_ROM_IMAGE_SIZE=0x13c00 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -58,4 +58,4 @@ romimage "fallback" # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/tyan/s2875/Config.lb b/targets/tyan/s2875/Config.lb index b4388d1a1a..50346f776f 100644 --- a/targets/tyan/s2875/Config.lb +++ b/targets/tyan/s2875/Config.lb @@ -8,18 +8,18 @@ mainboard tyan/s2875 # Tyan s2875 romimage "normal" # 48K for SCSI FW or ATI ROM - option ROM_SIZE = 512*1024-48*1024 + option CONFIG_ROM_SIZE = 512*1024-48*1024 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024 # 64K for Etherboot -# option ROM_SIZE = 512*1024-64*1024 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x16000 -# option ROM_IMAGE_SIZE=0x17800 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 +# option CONFIG_ROM_SIZE = 512*1024-64*1024 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x16000 +# option CONFIG_ROM_IMAGE_SIZE=0x17800 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -35,13 +35,13 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x16000 -# option ROM_IMAGE_SIZE=0x17800 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x16000 +# option CONFIG_ROM_IMAGE_SIZE=0x17800 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -56,4 +56,4 @@ romimage "fallback" # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/tyan/s2880/Config.lb b/targets/tyan/s2880/Config.lb index f1e2960ccd..fc40941f46 100644 --- a/targets/tyan/s2880/Config.lb +++ b/targets/tyan/s2880/Config.lb @@ -8,18 +8,18 @@ mainboard tyan/s2880 # Tyan s2880 romimage "normal" # 48K for SCSI FW or ATI ROM - option ROM_SIZE = 512*1024-48*1024 + option CONFIG_ROM_SIZE = 512*1024-48*1024 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024 # 64K for Etherboot -# option ROM_SIZE = 512*1024-64*1024 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x16000 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x17800 - option XIP_ROM_SIZE=0x20000 +# option CONFIG_ROM_SIZE = 512*1024-64*1024 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x16000 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x17800 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -35,13 +35,13 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x16000 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x17800 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x16000 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x17800 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -56,4 +56,4 @@ romimage "fallback" # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/tyan/s2881/Config-lab.lb b/targets/tyan/s2881/Config-lab.lb index bc7ecf1188..ad42a5d388 100644 --- a/targets/tyan/s2881/Config-lab.lb +++ b/targets/tyan/s2881/Config-lab.lb @@ -5,19 +5,19 @@ target s2881 mainboard tyan/s2881 -option ROM_SIZE=0x100000 +option CONFIG_ROM_SIZE=0x100000 # 36K for ATI ROM in 1M -option FALLBACK_SIZE=(ROM_SIZE-0x9000) +option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x9000) # Tyan s2881 romimage "fallback" - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 option CONFIG_PRECOMPRESSED_PAYLOAD=1 - option ROM_IMAGE_SIZE=0x17000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_ROM_IMAGE_SIZE=0x17000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ../payload.elf.lzma end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/tyan/s2881/Config.lb b/targets/tyan/s2881/Config.lb index 112236d347..010e704613 100644 --- a/targets/tyan/s2881/Config.lb +++ b/targets/tyan/s2881/Config.lb @@ -8,19 +8,19 @@ mainboard tyan/s2881 # Tyan s2881 romimage "normal" # 36K for ATI ROM - option ROM_SIZE = 512*1024-36*1024 + option CONFIG_ROM_SIZE = 512*1024-36*1024 # 48K for SCSI FW -# option ROM_SIZE = 512*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024 # 48K for SCSI FW and 36K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-36*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024-36*1024 # 64K for Etherboot -# option ROM_SIZE = 512*1024-64*1024 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x13000 -# option ROM_IMAGE_SIZE=0x16000 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 +# option CONFIG_ROM_SIZE = 512*1024-64*1024 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x13000 +# option CONFIG_ROM_IMAGE_SIZE=0x16000 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -37,12 +37,12 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x13000 -# option ROM_IMAGE_SIZE=0x16000 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x13000 +# option CONFIG_ROM_IMAGE_SIZE=0x16000 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -58,4 +58,4 @@ romimage "fallback" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/tyan/s2882/Config-lab.lb b/targets/tyan/s2882/Config-lab.lb index b54dcd8d43..f72ee2da59 100644 --- a/targets/tyan/s2882/Config-lab.lb +++ b/targets/tyan/s2882/Config-lab.lb @@ -5,19 +5,19 @@ target s2882 mainboard tyan/s2882 -option ROM_SIZE=0x100000 +option CONFIG_ROM_SIZE=0x100000 # 36K for ATI ROM in 1M -option FALLBACK_SIZE=(ROM_SIZE-0x9000) +option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x9000) # Tyan s2882 romimage "fallback" - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 option CONFIG_PRECOMPRESSED_PAYLOAD=1 - option ROM_IMAGE_SIZE=0x17000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_ROM_IMAGE_SIZE=0x17000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ../payload.elf.lzma end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/tyan/s2882/Config.lb b/targets/tyan/s2882/Config.lb index 404d9d95a8..a6d37479c4 100644 --- a/targets/tyan/s2882/Config.lb +++ b/targets/tyan/s2882/Config.lb @@ -8,16 +8,16 @@ mainboard tyan/s2882 # Tyan s2882 romimage "normal" # 36K for ATI ROM - option ROM_SIZE = 512*1024-36*1024 + option CONFIG_ROM_SIZE = 512*1024-36*1024 # 48K for SCSI FW and 36K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-36*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024-36*1024 # 64K for Etherboot -# option ROM_SIZE = 512*1024-64*1024 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x16000 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 +# option CONFIG_ROM_SIZE = 512*1024-64*1024 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x16000 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -32,11 +32,11 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x16000 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x16000 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -50,4 +50,4 @@ romimage "fallback" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/tyan/s2885/Config.lb b/targets/tyan/s2885/Config.lb index 8f29db17ac..72877d2dff 100644 --- a/targets/tyan/s2885/Config.lb +++ b/targets/tyan/s2885/Config.lb @@ -8,17 +8,17 @@ mainboard tyan/s2885 # Tyan s2895 romimage "normal" # 48K for SCSI FW -# option ROM_SIZE = 512*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024 # 64K for Etherboot -# option ROM_SIZE = 512*1024-64*1024 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x17800 -# option ROM_IMAGE_SIZE=0x16200 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 +# option CONFIG_ROM_SIZE = 512*1024-64*1024 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x17800 +# option CONFIG_ROM_IMAGE_SIZE=0x16200 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -37,12 +37,12 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x17800 -# option ROM_IMAGE_SIZE=0x16200 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x17800 +# option CONFIG_ROM_IMAGE_SIZE=0x16200 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -60,4 +60,4 @@ romimage "fallback" # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/tyan/s2891/Config-abuild.lb b/targets/tyan/s2891/Config-abuild.lb index 95f4366ab1..bc651b964d 100644 --- a/targets/tyan/s2891/Config-abuild.lb +++ b/targets/tyan/s2891/Config-abuild.lb @@ -4,24 +4,24 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/tyan/s2891/Config-lab.lb b/targets/tyan/s2891/Config-lab.lb index 24b5d066b6..8253b038c9 100644 --- a/targets/tyan/s2891/Config-lab.lb +++ b/targets/tyan/s2891/Config-lab.lb @@ -5,19 +5,19 @@ target s2891 mainboard tyan/s2891 -option ROM_SIZE=0x100000 +option CONFIG_ROM_SIZE=0x100000 # 36K for ATI ROM in 1M -option FALLBACK_SIZE=(ROM_SIZE-0x9000) +option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x9000) # Tyan s2891 romimage "fallback" - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 option CONFIG_PRECOMPRESSED_PAYLOAD=1 - option ROM_IMAGE_SIZE=0x17000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_ROM_IMAGE_SIZE=0x17000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ../payload.elf.lzma end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/tyan/s2891/Config.lb b/targets/tyan/s2891/Config.lb index fe91c36f7f..cab355e1b2 100644 --- a/targets/tyan/s2891/Config.lb +++ b/targets/tyan/s2891/Config.lb @@ -8,19 +8,19 @@ mainboard tyan/s2891 # Tyan s2891 romimage "normal" # 36K for ATI ROM in 1M - option ROM_SIZE = 1024*1024-36*1024 + option CONFIG_ROM_SIZE = 1024*1024-36*1024 # 48K for SCSI FW -# option ROM_SIZE = 512*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024 # 48K for SCSI FW and 36K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-36*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024-36*1024 # 64K for Etherboot -# option ROM_SIZE = 512*1024-64*1024 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x13000 -# option ROM_IMAGE_SIZE=0x16000 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 +# option CONFIG_ROM_SIZE = 512*1024-64*1024 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x13000 +# option CONFIG_ROM_IMAGE_SIZE=0x16000 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -38,12 +38,12 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x13000 -# option ROM_IMAGE_SIZE=0x16000 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x13000 +# option CONFIG_ROM_IMAGE_SIZE=0x16000 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -60,4 +60,4 @@ romimage "fallback" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/tyan/s2891/Config.lb.com2 b/targets/tyan/s2891/Config.lb.com2 index eee6b0af56..24251e19cf 100644 --- a/targets/tyan/s2891/Config.lb.com2 +++ b/targets/tyan/s2891/Config.lb.com2 @@ -8,16 +8,16 @@ mainboard tyan/s2891 # Tyan s2891 romimage "normal" # 48K for SCSI FW or ATI ROM - option ROM_SIZE = 512*1024-48*1024 + option CONFIG_ROM_SIZE = 512*1024-48*1024 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024 # 64K for Etherboot -# option ROM_SIZE = 512*1024-64*1024 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x13000 - option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x20000 +# option CONFIG_ROM_SIZE = 512*1024-64*1024 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x13000 + option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -34,11 +34,11 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x13000 - option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x13000 + option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -54,4 +54,4 @@ romimage "fallback" # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/tyan/s2892/Config-abuild.lb b/targets/tyan/s2892/Config-abuild.lb index 95f4366ab1..bc651b964d 100644 --- a/targets/tyan/s2892/Config-abuild.lb +++ b/targets/tyan/s2892/Config-abuild.lb @@ -4,24 +4,24 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/tyan/s2892/Config-lab.lb b/targets/tyan/s2892/Config-lab.lb index 169023f783..c9d8584085 100644 --- a/targets/tyan/s2892/Config-lab.lb +++ b/targets/tyan/s2892/Config-lab.lb @@ -6,21 +6,21 @@ target s2892 mainboard tyan/s2892 # Leave Space for VGA BIOS -option ROM_SIZE = 1024*1024-36*1024 -#option ROM_SIZE = 1024*1024 +option CONFIG_ROM_SIZE = 1024*1024-36*1024 +#option CONFIG_ROM_SIZE = 1024*1024 option CONFIG_CONSOLE_SERIAL8250 = 1 option CONFIG_CONSOLE_VGA = 1 -option XIP_ROM_SIZE = 0x20000 -option ROM_IMAGE_SIZE = 0x18000 -option FALLBACK_SIZE = ROM_SIZE +option CONFIG_XIP_ROM_SIZE = 0x20000 +option CONFIG_ROM_IMAGE_SIZE = 0x18000 +option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE # Tyan s2892 romimage "fallback" option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 option CONFIG_PRECOMPRESSED_PAYLOAD=1 - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=1 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ../payload.elf.lzma end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/tyan/s2892/Config.lb b/targets/tyan/s2892/Config.lb index 8dc2225561..82e4ca4f47 100644 --- a/targets/tyan/s2892/Config.lb +++ b/targets/tyan/s2892/Config.lb @@ -8,20 +8,20 @@ mainboard tyan/s2892 # Tyan s2892 romimage "normal" # 36K for ATI ROM in 1M - option ROM_SIZE = 1024*1024-36*1024 + option CONFIG_ROM_SIZE = 1024*1024-36*1024 # 48K for SCSI FW or ATI ROM -# option ROM_SIZE = 512*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024 # 64K for Etherboot -# option ROM_SIZE = 512*1024-64*1024 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x16380 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x17800 - option XIP_ROM_SIZE=0x20000 +# option CONFIG_ROM_SIZE = 512*1024-64*1024 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x16380 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x17800 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -38,13 +38,13 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x16380 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x17800 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x16380 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x17800 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -60,4 +60,4 @@ romimage "fallback" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/tyan/s2895/Config-abuild.lb b/targets/tyan/s2895/Config-abuild.lb index 88dd1684e3..b1c927705b 100644 --- a/targets/tyan/s2895/Config-abuild.lb +++ b/targets/tyan/s2895/Config-abuild.lb @@ -4,33 +4,33 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "normal" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/tyan/s2895/Config-lab.lb b/targets/tyan/s2895/Config-lab.lb index fa4bbf0cc8..e5368925d9 100644 --- a/targets/tyan/s2895/Config-lab.lb +++ b/targets/tyan/s2895/Config-lab.lb @@ -7,19 +7,19 @@ mainboard tyan/s2895 option CONFIG_CONSOLE_SERIAL8250 = 1 option CONFIG_CONSOLE_VGA = 1 -option XIP_ROM_SIZE = 0x20000 -option ROM_IMAGE_SIZE = 0x18000 -option HAVE_FAILOVER_BOOT = 0 -option FAILOVER_SIZE = 0 -option FALLBACK_SIZE = ROM_SIZE +option CONFIG_XIP_ROM_SIZE = 0x20000 +option CONFIG_ROM_IMAGE_SIZE = 0x18000 +option CONFIG_HAVE_FAILOVER_BOOT = 0 +option CONFIG_FAILOVER_SIZE = 0 +option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE option CONFIG_COMPRESSED_PAYLOAD_LZMA = 1 option CONFIG_PRECOMPRESSED_PAYLOAD = 1 # Tyan s2895 romimage "fallback" - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=1 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ../payload.elf.lzma end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/tyan/s2895/Config.lb b/targets/tyan/s2895/Config.lb index 0b5d73a300..69a83f1fe7 100644 --- a/targets/tyan/s2895/Config.lb +++ b/targets/tyan/s2895/Config.lb @@ -8,21 +8,21 @@ mainboard tyan/s2895 # Tyan s2895 romimage "normal" # 48K for SCSI FW -# option ROM_SIZE = 475136 +# option CONFIG_ROM_SIZE = 475136 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 425984 +# option CONFIG_ROM_SIZE = 425984 # 64K for Etherboot -# option ROM_SIZE = 458752 +# option CONFIG_ROM_SIZE = 458752 # 64K for NIC option 48K for Raid option rom -# option ROM_SIZE = 409600 - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x15000 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x17800 - option XIP_ROM_SIZE=0x20000 +# option CONFIG_ROM_SIZE = 409600 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x15000 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x17800 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -46,14 +46,14 @@ romimage "normal" end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x11800 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x15000 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x17800 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x11800 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x15000 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x17800 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -74,13 +74,13 @@ romimage "fallback" end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/tyan/s2912/Config-abuild.lb b/targets/tyan/s2912/Config-abuild.lb index 88dd1684e3..b1c927705b 100644 --- a/targets/tyan/s2912/Config-abuild.lb +++ b/targets/tyan/s2912/Config-abuild.lb @@ -4,33 +4,33 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "normal" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/tyan/s2912/Config.lb b/targets/tyan/s2912/Config.lb index 28deabcf6c..d31438869a 100644 --- a/targets/tyan/s2912/Config.lb +++ b/targets/tyan/s2912/Config.lb @@ -27,20 +27,20 @@ mainboard tyan/s2912 # serengeti_leopard romimage "normal" # 48K for SCSI FW -# option ROM_SIZE = 475136 +# option CONFIG_ROM_SIZE = 475136 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 425984 +# option CONFIG_ROM_SIZE = 425984 # 64K for Etherboot -# option ROM_SIZE = 458752 +# option CONFIG_ROM_SIZE = 458752 # 44k for atixx.rom -# option ROM_SIZE = 479232 - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x18800 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x40000 +# option CONFIG_ROM_SIZE = 479232 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x18800 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -62,13 +62,13 @@ romimage "normal" end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x19800 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x40000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 +# option CONFIG_ROM_IMAGE_SIZE=0x19800 + option CONFIG_ROM_IMAGE_SIZE=0x20000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -95,12 +95,12 @@ romimage "fallback" end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/tyan/s2912/Config.lb.kernel b/targets/tyan/s2912/Config.lb.kernel index 3ca4f324d7..e09a5580c0 100644 --- a/targets/tyan/s2912/Config.lb.kernel +++ b/targets/tyan/s2912/Config.lb.kernel @@ -24,19 +24,19 @@ target s2912 mainboard tyan/s2912 -option ROM_SIZE=0x200000 -option FALLBACK_SIZE=(ROM_SIZE-0x1000) +option CONFIG_ROM_SIZE=0x200000 +option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x1000) romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 option CONFIG_PRECOMPRESSED_PAYLOAD=1 -# option ROM_IMAGE_SIZE=0x19800 - option ROM_IMAGE_SIZE=0x17000 -# option ROM_IMAGE_SIZE=0x15800 -# option ROM_IMAGE_SIZE=0x13800 - option XIP_ROM_SIZE=0x40000 +# option CONFIG_ROM_IMAGE_SIZE=0x19800 + option CONFIG_ROM_IMAGE_SIZE=0x17000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -65,13 +65,13 @@ romimage "fallback" end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover" +#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/tyan/s2912_fam10/Config-abuild.lb b/targets/tyan/s2912_fam10/Config-abuild.lb index 7431783fb4..6c075c3d11 100644 --- a/targets/tyan/s2912_fam10/Config-abuild.lb +++ b/targets/tyan/s2912_fam10/Config-abuild.lb @@ -22,36 +22,36 @@ target tyan_s2912_fam10 mainboard tyan/s2912_fam10 option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ romimage "normal" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x34000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x34000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION=".0-Normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x34000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x34000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION=".0-Failover" end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/tyan/s2912_fam10/Config.lb b/targets/tyan/s2912_fam10/Config.lb index 5c9dfcd1e5..e08f657081 100644 --- a/targets/tyan/s2912_fam10/Config.lb +++ b/targets/tyan/s2912_fam10/Config.lb @@ -25,34 +25,34 @@ target s2912_fam10 mainboard tyan/s2912_fam10 # Make room for ATI ES1000 VGA ROM -option ROM_SIZE=ROM_SIZE-44*1024 +option CONFIG_ROM_SIZE=ROM_SIZE-44*1024 romimage "normal" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf payload ../payload.elf end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x40000 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf payload ../payload.elf end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" diff --git a/targets/tyan/s2912_fam10/Config.lb.kernel b/targets/tyan/s2912_fam10/Config.lb.kernel index 3ca4f324d7..e09a5580c0 100644 --- a/targets/tyan/s2912_fam10/Config.lb.kernel +++ b/targets/tyan/s2912_fam10/Config.lb.kernel @@ -24,19 +24,19 @@ target s2912 mainboard tyan/s2912 -option ROM_SIZE=0x200000 -option FALLBACK_SIZE=(ROM_SIZE-0x1000) +option CONFIG_ROM_SIZE=0x200000 +option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x1000) romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 option CONFIG_PRECOMPRESSED_PAYLOAD=1 -# option ROM_IMAGE_SIZE=0x19800 - option ROM_IMAGE_SIZE=0x17000 -# option ROM_IMAGE_SIZE=0x15800 -# option ROM_IMAGE_SIZE=0x13800 - option XIP_ROM_SIZE=0x40000 +# option CONFIG_ROM_IMAGE_SIZE=0x19800 + option CONFIG_ROM_IMAGE_SIZE=0x17000 +# option CONFIG_ROM_IMAGE_SIZE=0x15800 +# option CONFIG_ROM_IMAGE_SIZE=0x13800 + option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -65,13 +65,13 @@ romimage "fallback" end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover" +#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/tyan/s4880/Config.lb b/targets/tyan/s4880/Config.lb index abb9912713..6b98702f49 100644 --- a/targets/tyan/s4880/Config.lb +++ b/targets/tyan/s4880/Config.lb @@ -8,16 +8,16 @@ mainboard tyan/s4880 # Tyan s4880 romimage "normal" # 48K for SCSI FW or ATI ROM - option ROM_SIZE = 512*1024-48*1024 + option CONFIG_ROM_SIZE = 512*1024-48*1024 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024 # 64K for Etherboot -# option ROM_SIZE = 512*1024-64*1024 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x19000 -# option ROM_IMAGE_SIZE=0x19c00 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 +# option CONFIG_ROM_SIZE = 512*1024-64*1024 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x19000 +# option CONFIG_ROM_IMAGE_SIZE=0x19c00 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -32,11 +32,11 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x19000 -# option ROM_IMAGE_SIZE=0x19c00 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x19000 +# option CONFIG_ROM_IMAGE_SIZE=0x19c00 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -50,4 +50,4 @@ romimage "fallback" # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/tyan/s4882/Config.lb b/targets/tyan/s4882/Config.lb index bcf903db9b..cc44c1b32c 100644 --- a/targets/tyan/s4882/Config.lb +++ b/targets/tyan/s4882/Config.lb @@ -8,18 +8,18 @@ mainboard tyan/s4882 # Tyan s4882 romimage "normal" # 48K for SCSI FW or ATI ROM - option ROM_SIZE = 512*1024-48*1024 + option CONFIG_ROM_SIZE = 512*1024-48*1024 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024 # 64K for Etherboot -# option ROM_SIZE = 512*1024-64*1024 - option USE_FALLBACK_IMAGE=0 -# option ROM_IMAGE_SIZE=0x19000 -# option ROM_IMAGE_SIZE=0x19c00 -# option ROM_IMAGE_SIZE=0x18800 -# option ROM_IMAGE_SIZE=0x16200 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 +# option CONFIG_ROM_SIZE = 512*1024-64*1024 + option CONFIG_USE_FALLBACK_IMAGE=0 +# option CONFIG_ROM_IMAGE_SIZE=0x19000 +# option CONFIG_ROM_IMAGE_SIZE=0x19c00 +# option CONFIG_ROM_IMAGE_SIZE=0x18800 +# option CONFIG_ROM_IMAGE_SIZE=0x16200 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -36,13 +36,13 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x19000 -# option ROM_IMAGE_SIZE=0x19c00 -# option ROM_IMAGE_SIZE=0x18800 -# option ROM_IMAGE_SIZE=0x16200 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 +# option CONFIG_ROM_IMAGE_SIZE=0x19000 +# option CONFIG_ROM_IMAGE_SIZE=0x19c00 +# option CONFIG_ROM_IMAGE_SIZE=0x18800 +# option CONFIG_ROM_IMAGE_SIZE=0x16200 + option CONFIG_ROM_IMAGE_SIZE=0x20000 + option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf @@ -58,4 +58,4 @@ romimage "fallback" # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/via/epia-cn/Config-abuild.lb b/targets/via/epia-cn/Config-abuild.lb index d364cb7cbd..2a65acae0d 100644 --- a/targets/via/epia-cn/Config-abuild.lb +++ b/targets/via/epia-cn/Config-abuild.lb @@ -4,18 +4,18 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ -option ROM_SIZE=512*1024 +option CONFIG_ROM_SIZE=512*1024 romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/via/epia-cn/Config.lb b/targets/via/epia-cn/Config.lb index c6d82e5b5d..3d51302956 100644 --- a/targets/via/epia-cn/Config.lb +++ b/targets/via/epia-cn/Config.lb @@ -22,22 +22,22 @@ target via_epia_cn mainboard via/epia-cn -option MAXIMUM_CONSOLE_LOGLEVEL=8 -option DEFAULT_CONSOLE_LOGLEVEL=8 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 option CONFIG_CONSOLE_SERIAL8250=1 # coreboot C code runs at this location in RAM -option _RAMBASE=0x00004000 +option CONFIG_RAMBASE=0x00004000 # # Generate the final ROM like this: # cat vgabios bochsbios coreboot.rom > coreboot.rom.final # -option ROM_SIZE = (512 * 1024) - (64 * 1024) - (64 * 1024) +option CONFIG_ROM_SIZE = (512 * 1024) - (64 * 1024) - (64 * 1024) romimage "image" option COREBOOT_EXTRA_VERSION = "-epiacn" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "image" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "image" diff --git a/targets/via/epia-m/Config-abuild.lb b/targets/via/epia-m/Config-abuild.lb index 52c1711bd2..85066ba0d7 100644 --- a/targets/via/epia-m/Config-abuild.lb +++ b/targets/via/epia-m/Config-abuild.lb @@ -2,26 +2,26 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ -option ROM_SIZE=256*1024 +option CONFIG_ROM_SIZE=256*1024 romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=64*1024 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=64*1024 option COREBOOT_EXTRA_VERSION=".0-Normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=64*1024 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=64*1024 option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/via/epia-m/Config.512kflash.lb b/targets/via/epia-m/Config.512kflash.lb index 88d13821ff..0cf7e1c593 100644 --- a/targets/via/epia-m/Config.512kflash.lb +++ b/targets/via/epia-m/Config.512kflash.lb @@ -5,25 +5,25 @@ target epia-m.512kflash mainboard via/epia-m -option MAXIMUM_CONSOLE_LOGLEVEL=8 -option DEFAULT_CONSOLE_LOGLEVEL=8 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 option CONFIG_CONSOLE_SERIAL8250=1 -option ROM_SIZE=512*1024 +option CONFIG_ROM_SIZE=512*1024 -option HAVE_OPTION_TABLE=1 +option CONFIG_HAVE_OPTION_TABLE=1 option CONFIG_ROM_PAYLOAD=1 -option HAVE_FALLBACK_BOOT=1 +option CONFIG_HAVE_FALLBACK_BOOT=1 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -option FALLBACK_SIZE=131072 +option CONFIG_FALLBACK_SIZE=131072 ## Coreboot C code runs at this location in RAM -option _RAMBASE=0x00004000 +option CONFIG_RAMBASE=0x00004000 # ### @@ -35,8 +35,8 @@ option _RAMBASE=0x00004000 # Via EPIA M # romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -44,12 +44,12 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf payload ../../../../../lnxieepro100.ebi end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/via/epia-m/Config.etherboot.lb b/targets/via/epia-m/Config.etherboot.lb index 6e59424be8..0ceaf171ec 100644 --- a/targets/via/epia-m/Config.etherboot.lb +++ b/targets/via/epia-m/Config.etherboot.lb @@ -5,24 +5,24 @@ target epia-m mainboard via/epia-m -option MAXIMUM_CONSOLE_LOGLEVEL=8 -option DEFAULT_CONSOLE_LOGLEVEL=8 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 option CONFIG_CONSOLE_SERIAL8250=1 -option ROM_SIZE=256*1024 +option CONFIG_ROM_SIZE=256*1024 -option HAVE_OPTION_TABLE=1 +option CONFIG_HAVE_OPTION_TABLE=1 option CONFIG_ROM_PAYLOAD=1 -option HAVE_FALLBACK_BOOT=1 +option CONFIG_HAVE_FALLBACK_BOOT=1 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -option FALLBACK_SIZE=131072 +option CONFIG_FALLBACK_SIZE=131072 ## Coreboot C code runs at this location in RAM -option _RAMBASE=0x00004000 +option CONFIG_RAMBASE=0x00004000 # ### @@ -34,8 +34,8 @@ option _RAMBASE=0x00004000 # Via EPIA-M # romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -43,12 +43,12 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf payload ../../../../../lnxieepro100.ebi end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/via/epia-m/Config.filo.lb b/targets/via/epia-m/Config.filo.lb index bb5bc62a0e..02313ff15a 100644 --- a/targets/via/epia-m/Config.filo.lb +++ b/targets/via/epia-m/Config.filo.lb @@ -5,24 +5,24 @@ target epia-m mainboard via/epia-m -option MAXIMUM_CONSOLE_LOGLEVEL=8 -option DEFAULT_CONSOLE_LOGLEVEL=8 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 option CONFIG_CONSOLE_SERIAL8250=1 -option ROM_SIZE=256*1024 +option CONFIG_ROM_SIZE=256*1024 -option HAVE_OPTION_TABLE=1 +option CONFIG_HAVE_OPTION_TABLE=1 option CONFIG_ROM_PAYLOAD=1 -option HAVE_FALLBACK_BOOT=1 +option CONFIG_HAVE_FALLBACK_BOOT=1 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -option FALLBACK_SIZE=131072 +option CONFIG_FALLBACK_SIZE=131072 ## Coreboot C code runs at this location in RAM -option _RAMBASE=0x00004000 +option CONFIG_RAMBASE=0x00004000 # ### @@ -34,8 +34,8 @@ option _RAMBASE=0x00004000 # EPIA-M # romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -44,8 +44,8 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -53,4 +53,4 @@ romimage "fallback" payload ../../../../../../filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/via/epia-m/Config.lb b/targets/via/epia-m/Config.lb index 19f26d26cb..2f9d6e1d3d 100644 --- a/targets/via/epia-m/Config.lb +++ b/targets/via/epia-m/Config.lb @@ -3,16 +3,16 @@ target via_epia-m mainboard via/epia-m -option MAXIMUM_CONSOLE_LOGLEVEL=8 -option DEFAULT_CONSOLE_LOGLEVEL=8 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 option CONFIG_CONSOLE_SERIAL8250=1 -option ROM_SIZE=256*1024 +option CONFIG_ROM_SIZE=256*1024 -option HAVE_OPTION_TABLE=1 +option CONFIG_HAVE_OPTION_TABLE=1 option CONFIG_ROM_PAYLOAD=1 -option HAVE_FALLBACK_BOOT=1 +option CONFIG_HAVE_FALLBACK_BOOT=1 #option CONFIG_COMPRESSED_PAYLOAD_NRV2B=1 option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 @@ -21,28 +21,28 @@ option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -option FALLBACK_SIZE=131072 +option CONFIG_FALLBACK_SIZE=131072 ## Coreboot C code runs at this location in RAM -option _RAMBASE=0x00004000 +option CONFIG_RAMBASE=0x00004000 # # Via EPIA M # romimage "normal" - option USE_FALLBACK_IMAGE=0 -#option ROM_IMAGE_SIZE=128*1024 - option ROM_IMAGE_SIZE=64*1024 + option CONFIG_USE_FALLBACK_IMAGE=0 +#option CONFIG_ROM_IMAGE_SIZE=128*1024 + option CONFIG_ROM_IMAGE_SIZE=64*1024 option COREBOOT_EXTRA_VERSION=".0-Normal" payload $(HOME)/svn/payload.elf end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - #option ROM_IMAGE_SIZE=128*1024 - option ROM_IMAGE_SIZE=60*1024 + option CONFIG_USE_FALLBACK_IMAGE=1 + #option CONFIG_ROM_IMAGE_SIZE=128*1024 + option CONFIG_ROM_IMAGE_SIZE=60*1024 option COREBOOT_EXTRA_VERSION=".0-Fallback" payload $(HOME)/svn/payload.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/via/epia-m/Config.vga.filo b/targets/via/epia-m/Config.vga.filo index c1f88b0bd9..86b4fb29b9 100644 --- a/targets/via/epia-m/Config.vga.filo +++ b/targets/via/epia-m/Config.vga.filo @@ -5,23 +5,23 @@ target epia-m mainboard via/epia-m -option MAXIMUM_CONSOLE_LOGLEVEL=8 -option DEFAULT_CONSOLE_LOGLEVEL=8 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 option CONFIG_CONSOLE_SERIAL8250=1 -option ROM_SIZE=256*1024 -option HAVE_OPTION_TABLE=1 +option CONFIG_ROM_SIZE=256*1024 +option CONFIG_HAVE_OPTION_TABLE=1 option CONFIG_ROM_PAYLOAD=1 -option HAVE_FALLBACK_BOOT=1 +option CONFIG_HAVE_FALLBACK_BOOT=1 ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -option FALLBACK_SIZE=0x18000 +option CONFIG_FALLBACK_SIZE=0x18000 ## Coreboot C code runs at this location in RAM -option _RAMBASE=0x00004000 +option CONFIG_RAMBASE=0x00004000 ### ### Compute the start location and size size of @@ -32,19 +32,19 @@ option _RAMBASE=0x00004000 # EPIA-M # romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0xc000 - option ROM_SECTION_OFFSET=0x10000 - option ROM_SECTION_SIZE=0x18000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0xc000 + option CONFIG_ROM_SECTION_OFFSET=0x10000 + option CONFIG_ROM_SECTION_SIZE=0x18000 option COREBOOT_EXTRA_VERSION=".0-Normal" payload $(HOME)/svn/filo.elf end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0xc000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0xc000 option COREBOOT_EXTRA_VERSION=".0-Fallback" payload $(HOME)/svn/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/via/epia-m700/Config.lb b/targets/via/epia-m700/Config.lb index 4cb630882a..ecedd02070 100644 --- a/targets/via/epia-m700/Config.lb +++ b/targets/via/epia-m700/Config.lb @@ -26,4 +26,4 @@ romimage "image" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "image" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "image" diff --git a/targets/via/epia/Config.512kflash.lb b/targets/via/epia/Config.512kflash.lb index ff2e4da303..c904b414d8 100644 --- a/targets/via/epia/Config.512kflash.lb +++ b/targets/via/epia/Config.512kflash.lb @@ -4,13 +4,13 @@ target epia.512kflash mainboard via/epia -option ROM_SIZE=512*1024 +option CONFIG_ROM_SIZE=512*1024 # # Via Epia romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -18,12 +18,12 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf payload ../../../../../lnxieepro100.ebi end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/via/epia/Config.512kflash.linuxtiny.lb b/targets/via/epia/Config.512kflash.linuxtiny.lb index 4a7702e4ce..b6b184b5d0 100644 --- a/targets/via/epia/Config.512kflash.linuxtiny.lb +++ b/targets/via/epia/Config.512kflash.linuxtiny.lb @@ -4,18 +4,18 @@ target epia.512kflash.linuxtiny mainboard via/epia -option ROM_SIZE=512*1024 -option FALLBACK_SIZE=ROM_SIZE -option MAXIMUM_CONSOLE_LOGLEVEL=9 -option DEFAULT_CONSOLE_LOGLEVEL=9 +option CONFIG_ROM_SIZE=512*1024 +option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=64*1024 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=64*1024 option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf payload /tmp/linux.elf end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" diff --git a/targets/via/epia/Config.filo.lb b/targets/via/epia/Config.filo.lb index 0657cdb7e6..5107037135 100644 --- a/targets/via/epia/Config.filo.lb +++ b/targets/via/epia/Config.filo.lb @@ -7,8 +7,8 @@ mainboard via/epia # # Via Epia romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -17,8 +17,8 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -26,4 +26,4 @@ romimage "fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/via/epia/Config.ituner.filo.lb b/targets/via/epia/Config.ituner.filo.lb index 799dae3965..ddfec5e08c 100644 --- a/targets/via/epia/Config.ituner.filo.lb +++ b/targets/via/epia/Config.ituner.filo.lb @@ -4,13 +4,13 @@ target epia-ituner-filo mainboard via/epia -option MAXIMUM_CONSOLE_LOGLEVEL=9 -option DEFAULT_CONSOLE_LOGLEVEL=9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 # # Via Epia romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -19,8 +19,8 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -28,4 +28,4 @@ romimage "fallback" payload /tmp/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/via/epia/Config.lb b/targets/via/epia/Config.lb index f93088da90..72440e1538 100644 --- a/targets/via/epia/Config.lb +++ b/targets/via/epia/Config.lb @@ -8,13 +8,13 @@ target epia mainboard via/epia -option MAXIMUM_CONSOLE_LOGLEVEL=9 -option DEFAULT_CONSOLE_LOGLEVEL=9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 # # Via Epia romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -23,8 +23,8 @@ romimage "normal" end romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x10000 + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf @@ -32,4 +32,4 @@ romimage "fallback" payload /etc/hosts end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/targets/via/pc2500e/Config-abuild.lb b/targets/via/pc2500e/Config-abuild.lb index c590daaa5e..b7bd85b8af 100644 --- a/targets/via/pc2500e/Config-abuild.lb +++ b/targets/via/pc2500e/Config-abuild.lb @@ -22,19 +22,19 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC = "CROSSCC" -option CROSS_COMPILE = "CROSS_PREFIX" -option HOSTCC = "CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE = "CROSS_PREFIX" +option CONFIG_HOSTCC = "CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ -option ROM_SIZE = 512 * 1024 +option CONFIG_ROM_SIZE = 512 * 1024 romimage "image" - option USE_FALLBACK_IMAGE = 1 - option ROM_IMAGE_SIZE = 128 * 1024 + option CONFIG_USE_FALLBACK_IMAGE = 1 + option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "image" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "image" diff --git a/targets/via/pc2500e/Config.lb b/targets/via/pc2500e/Config.lb index 9846b4cdf1..4d8fa8ebe6 100644 --- a/targets/via/pc2500e/Config.lb +++ b/targets/via/pc2500e/Config.lb @@ -26,4 +26,4 @@ romimage "image" payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "image" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "image" diff --git a/targets/via/vt8454c/Config-abuild.lb b/targets/via/vt8454c/Config-abuild.lb index a6c5ef1553..eb67dfae96 100644 --- a/targets/via/vt8454c/Config-abuild.lb +++ b/targets/via/vt8454c/Config-abuild.lb @@ -25,19 +25,19 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" -option ROM_SIZE=512*1024 +option CONFIG_ROM_SIZE=512*1024 __COMPRESSION__ __LOGLEVEL__ romimage "fallback" - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=1 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" #pci_rom $(TOP)/via-cx700.rom vendor_id=0x1106 device_id=0x3157 diff --git a/targets/via/vt8454c/Config.lb b/targets/via/vt8454c/Config.lb index b98352b8d3..cb42703260 100644 --- a/targets/via/vt8454c/Config.lb +++ b/targets/via/vt8454c/Config.lb @@ -23,21 +23,21 @@ target via_vt8454c mainboard via/vt8454c -option MAXIMUM_CONSOLE_LOGLEVEL=5 -option DEFAULT_CONSOLE_LOGLEVEL=5 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5 -option ROM_SIZE=(512-64)*1024 +option CONFIG_ROM_SIZE=(512-64)*1024 romimage "normal" - option USE_FALLBACK_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 option COREBOOT_EXTRA_VERSION=".0-normal" payload $(HOME)/payload.elf end romimage "fallback" - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=1 option COREBOOT_EXTRA_VERSION=".0-fallback" payload $(HOME)/payload.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" diff --git a/util/abuild/abuild b/util/abuild/abuild index 47decf61eb..7dc7cf10d0 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -165,8 +165,8 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ @@ -175,25 +175,25 @@ EOF if [ "$TARCH" == i386 ] ; then cat <<EOF romimage "normal" - option USE_FALLBACK_IMAGE=0 + option CONFIG_USE_FALLBACK_IMAGE=0 if CONFIG_CBFS else - option ROM_IMAGE_SIZE=0x17000 + option CONFIG_ROM_IMAGE_SIZE=0x17000 end option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=1 if CONFIG_CBFS else - option ROM_IMAGE_SIZE=0x17000 + option CONFIG_ROM_IMAGE_SIZE=0x17000 end option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" EOF else cat <<EOF @@ -208,8 +208,8 @@ EOF fi if [ "$loglevel" != "default" ]; then - LOGLEVEL1="option MAXIMUM_CONSOLE_LOGLEVEL=$loglevel" - LOGLEVEL2="option DEFAULT_CONSOLE_LOGLEVEL=$loglevel" + LOGLEVEL1="option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=$loglevel" + LOGLEVEL2="option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=$loglevel" else LOGLEVEL1="# no loglevel override" LOGLEVEL2="" diff --git a/util/analysis/Makefile b/util/analysis/Makefile index add976f312..91b11864fa 100644 --- a/util/analysis/Makefile +++ b/util/analysis/Makefile @@ -23,7 +23,7 @@ $(foreach VENDOR, $(VENDORS), $(eval $(VENDOR)_BOARDS := $(shell ls $(TOP)/targe TARGETS := $(foreach VENDOR, $(VENDORS), $(addprefix $(VENDOR)/, $($(VENDOR)_BOARDS))) # The following delayed-evalutate variables are only to be used in rule commands. -MAINBOARD = $(TOP)/src/mainboard/$(shell grep ^mainboard $(dir $*)/Config.lb|grep -Eo [-[:alnum:]_/]+[[:space:]]?$$) +CONFIG_MAINBOARD = $(TOP)/src/mainboard/$(shell grep ^mainboard $(dir $*)/Config.lb|grep -Eo [-[:alnum:]_/]+[[:space:]]?$$) IMAGE_DIR = $(firstword $(shell grep -Eo ^romimage[[:space:]]+\"[[:alnum:]_-/]+ $(dir $*)/Config.lb|sed -r s/romimage[[:space:]]+\"//)) # Evaluate one assignment to variable "$1" from file "$2" diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile index 50f97961bc..7dc83fd2e4 100644 --- a/util/cbfstool/Makefile +++ b/util/cbfstool/Makefile @@ -8,7 +8,7 @@ COMMANDS=create.o bootblock.o delete.o extract.o add.o print.o resize.o OBJ=$(COMMANDS) cbfstool.o util.o fs.o INC=cbfstool.h cbfs.h -HOSTCC ?= gcc +CONFIG_HOSTCC ?= gcc HOSTCXX ?= g++ CFLAGS=-g -Wall -W -Werror @@ -18,7 +18,7 @@ DESTDIR ?= /usr/local/bin all: $(obj)/cbfstool $(obj)/tools/cbfs-mkpayload $(obj)/tools/cbfs-mkstage $(obj)/cbfstool: $(patsubst %,$(obj)/%,$(OBJ)) - $(HOSTCC) -o $@ $(patsubst %,$(obj)/%,$(OBJ)) + $(CONFIG_HOSTCC) -o $@ $(patsubst %,$(obj)/%,$(OBJ)) tobj = $(obj)/tools tsrc = $(shell pwd)/tools @@ -26,7 +26,7 @@ tsrc = $(shell pwd)/tools include $(tsrc)/Makefile $(obj)/%.o: %.c $(INC) - $(HOSTCC) $(CFLAGS) -c -o $@ $< + $(CONFIG_HOSTCC) $(CFLAGS) -c -o $@ $< install: $(obj)/cbfstool $(obj)/tools/cbfs-mkpayload $(obj)/tools/cbfs-mkstage @ install -d $(DESTDIR) diff --git a/util/cbfstool/tools/Makefile b/util/cbfstool/tools/Makefile index e750c21bd7..3bb8f5dff5 100644 --- a/util/cbfstool/tools/Makefile +++ b/util/cbfstool/tools/Makefile @@ -18,7 +18,7 @@ $(tobj)/cbfs-mkpayload: $(tobj)/cbfs-mkpayload.o $(patsubst %,$(tobj)/%,$(COMMON $(HOSTCXX) $(CFLAGS) -o $@ $^ $(tobj)/%.o: %.c - $(HOSTCC) $(CFLAGS) -c -o $@ $< + $(CONFIG_HOSTCC) $(CFLAGS) -c -o $@ $< tools-clean: rm -f $(tobj)/cbfs-mkpayload.o $(tobj)/cbfs-mkstage.o $(patsubst %,$(tobj)/%,$(COMMON)) diff --git a/util/newconfig/config.g b/util/newconfig/config.g index 1a8d1b9380..81ce429021 100644 --- a/util/newconfig/config.g +++ b/util/newconfig/config.g @@ -329,7 +329,7 @@ class romimage: if (type == 'S'): # for .S, .o depends on .s file.write("%s: %s.s\n" % (obj[0], obj[3])) - file.write("\t$(CC) -c $(CPU_OPT) -o $@ $<\n") + file.write("\t$(CC) -c $(CONFIG_CPU_OPT) -o $@ $<\n") # and .s depends on .S file.write("%s.s: %s\n" % (obj[3], source)) # Note: next 2 lines are ONE output line! @@ -1386,7 +1386,7 @@ def endromimage(): global curimage global bootblocksize mainboard() - imagesize = getoption("ROM_IMAGE_SIZE", curimage) + imagesize = getoption("CONFIG_ROM_IMAGE_SIZE", curimage) bootblocksize += imagesize print "End ROMIMAGE" curimage = 0 @@ -1399,9 +1399,9 @@ def mainboardsetup(path): full_mainboard_path = os.path.join(treetop, 'src', 'mainboard', path) vendor = re.sub("/.*", "", path) part_number = re.sub("[^/]*/", "", path) - setdefault('MAINBOARD', full_mainboard_path, 0) - setdefault('MAINBOARD_VENDOR', vendor, 0) - setdefault('MAINBOARD_PART_NUMBER', part_number, 0) + setdefault('CONFIG_MAINBOARD', full_mainboard_path, 0) + setdefault('CONFIG_MAINBOARD_VENDOR', vendor, 0) + setdefault('CONFIG_MAINBOARD_PART_NUMBER', part_number, 0) def mainboard(): global curimage, dirstack, partstack @@ -1571,9 +1571,9 @@ def adddep(id, str): def setarch(my_arch): """arch is 'different' ... darn it.""" global curimage - print "SETTING ARCH %s\n" % my_arch + print "SETTING CONFIG_ARCH %s\n" % my_arch curimage.setarch(my_arch) - setdefault('ARCH', my_arch, 1) + setdefault('CONFIG_ARCH', my_arch, 1) part('arch', my_arch, 'Config.lb', 0) def doconfigfile(path, confdir, file, rule): @@ -1647,7 +1647,7 @@ parser Config: token ACTION: 'action' token ADDACTION: 'addaction' token ALWAYS: 'always' - token ARCH: 'arch' + token CONFIG_ARCH: 'arch' token BUILDROM: 'buildrom' token COMMENT: 'comment' token CONFIG: 'config' @@ -1677,7 +1677,7 @@ parser Config: token IRQ: 'irq' token LDSCRIPT: 'ldscript' token LOADOPTIONS: 'loadoptions' - token MAINBOARD: 'mainboard' + token CONFIG_MAINBOARD: 'mainboard' token MAINBOARDINIT: 'mainboardinit' token MAKEDEFINE: 'makedefine' token MAKERULE: 'makerule' @@ -1777,7 +1777,7 @@ parser Config: ] {{ if (C): part(parttype, partid, 'Config.lb', name) }} partend<<C>> - rule arch<<C>>: ARCH ID {{ if (C): setarch(ID) }} + rule arch<<C>>: CONFIG_ARCH ID {{ if (C): setarch(ID) }} partend<<C>> rule mainboardinit<<C>>: @@ -1969,7 +1969,7 @@ parser Config: rule payload<<C>>: PAYLOAD DIRPATH {{ if (C): payload(DIRPATH) }} rule mainboard: - MAINBOARD PATH {{ mainboardsetup(PATH) }} + CONFIG_MAINBOARD PATH {{ mainboardsetup(PATH) }} rule romif<<C>>: IF ID {{ c = lookup(ID) }} (romstmt<<C and c>>)* @@ -2287,7 +2287,7 @@ def writemakefile(path): file.write(" %s/coreboot.rom " % j) file.write("\n") - romsize = getoption("ROM_SIZE", image) + romsize = getoption("CONFIG_ROM_SIZE", image) file.write("\n\trm -f %s\n" %(i.name)) diff --git a/util/options/build_opt_tbl.c b/util/options/build_opt_tbl.c index 075387d1d8..f4aa8af7ec 100644 --- a/util/options/build_opt_tbl.c +++ b/util/options/build_opt_tbl.c @@ -459,17 +459,17 @@ int main(int argc, char **argv) exit(1); } /* And since we are not ready to be fully general purpose yet.. */ - if ((cs->range_start/8) != LB_CKS_RANGE_START) { + if ((cs->range_start/8) != CONFIG_LB_CKS_RANGE_START) { fprintf(stderr, "Error - Range start(%d) does not match define(%d) in line\n%s\n", - cs->range_start/8, LB_CKS_RANGE_START, line); + cs->range_start/8, CONFIG_LB_CKS_RANGE_START, line); exit(1); } - if ((cs->range_end/8) != LB_CKS_RANGE_END) { + if ((cs->range_end/8) != CONFIG_LB_CKS_RANGE_END) { fprintf(stderr, "Error - Range end (%d) does not match define (%d) in line\n%s\n", - (cs->range_end/8), LB_CKS_RANGE_END, line); + (cs->range_end/8), CONFIG_LB_CKS_RANGE_END, line); exit(1); } - if ((cs->location/8) != LB_CKS_LOC) { + if ((cs->location/8) != CONFIG_LB_CKS_LOC) { fprintf(stderr, "Error - Location does not match define in line\n%s\n", line); exit(1); } diff --git a/util/romcc/tests/hello_world.c b/util/romcc/tests/hello_world.c index 6dd80d89b8..b5ce540dc9 100644 --- a/util/romcc/tests/hello_world.c +++ b/util/romcc/tests/hello_world.c @@ -9,31 +9,31 @@ unsigned char inb(unsigned short port) } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#if TTYS0_BAUD == 115200 -#define TTYS0_DIV (1) +#if CONFIG_TTYS0_BAUD == 115200 +#define CONFIG_TTYS0_DIV (1) #else -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) #endif /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -55,7 +55,7 @@ unsigned char inb(unsigned short port) int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -66,14 +66,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } static void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -82,14 +82,14 @@ static void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } diff --git a/util/romcc/tests/hello_world1.c b/util/romcc/tests/hello_world1.c index 6dd80d89b8..b5ce540dc9 100644 --- a/util/romcc/tests/hello_world1.c +++ b/util/romcc/tests/hello_world1.c @@ -9,31 +9,31 @@ unsigned char inb(unsigned short port) } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#if TTYS0_BAUD == 115200 -#define TTYS0_DIV (1) +#if CONFIG_TTYS0_BAUD == 115200 +#define CONFIG_TTYS0_DIV (1) #else -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) #endif /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -55,7 +55,7 @@ unsigned char inb(unsigned short port) int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -66,14 +66,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } static void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -82,14 +82,14 @@ static void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } diff --git a/util/romcc/tests/hello_world2.c b/util/romcc/tests/hello_world2.c index 7990dcb518..18380d37e8 100644 --- a/util/romcc/tests/hello_world2.c +++ b/util/romcc/tests/hello_world2.c @@ -9,31 +9,31 @@ unsigned char inb(unsigned short port) } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#if TTYS0_BAUD == 115200 -#define TTYS0_DIV (1) +#if CONFIG_TTYS0_BAUD == 115200 +#define CONFIG_TTYS0_DIV (1) #else -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) #endif /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -55,7 +55,7 @@ unsigned char inb(unsigned short port) int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -66,14 +66,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } static void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -82,14 +82,14 @@ static void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } diff --git a/util/romcc/tests/raminit_test.c b/util/romcc/tests/raminit_test.c index 9b6cf5d31c..2c6fa8c750 100644 --- a/util/romcc/tests/raminit_test.c +++ b/util/romcc/tests/raminit_test.c @@ -83,27 +83,27 @@ static void pcibios_write_config_dword( } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -125,7 +125,7 @@ static void pcibios_write_config_dword( int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -136,14 +136,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -151,14 +151,14 @@ void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } void __console_tx_char(unsigned char byte) diff --git a/util/romcc/tests/raminit_test1.c b/util/romcc/tests/raminit_test1.c index 9b6cf5d31c..2c6fa8c750 100644 --- a/util/romcc/tests/raminit_test1.c +++ b/util/romcc/tests/raminit_test1.c @@ -83,27 +83,27 @@ static void pcibios_write_config_dword( } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -125,7 +125,7 @@ static void pcibios_write_config_dword( int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -136,14 +136,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -151,14 +151,14 @@ void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } void __console_tx_char(unsigned char byte) diff --git a/util/romcc/tests/raminit_test2.c b/util/romcc/tests/raminit_test2.c index 68747a7a91..2294b34e78 100644 --- a/util/romcc/tests/raminit_test2.c +++ b/util/romcc/tests/raminit_test2.c @@ -83,27 +83,27 @@ static void pcibios_write_config_dword( } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -125,7 +125,7 @@ static void pcibios_write_config_dword( int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -136,14 +136,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -151,14 +151,14 @@ void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } void __console_tx_char(unsigned char byte) diff --git a/util/romcc/tests/simple_test.c b/util/romcc/tests/simple_test.c index feacbfdc38..4065c51a2f 100644 --- a/util/romcc/tests/simple_test.c +++ b/util/romcc/tests/simple_test.c @@ -25,27 +25,27 @@ static unsigned int config_cmd2(unsigned char bus, unsigned devfn, unsigned wher } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -67,7 +67,7 @@ static unsigned int config_cmd2(unsigned char bus, unsigned devfn, unsigned wher int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -78,14 +78,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } diff --git a/util/romcc/tests/simple_test1.c b/util/romcc/tests/simple_test1.c index feacbfdc38..4065c51a2f 100644 --- a/util/romcc/tests/simple_test1.c +++ b/util/romcc/tests/simple_test1.c @@ -25,27 +25,27 @@ static unsigned int config_cmd2(unsigned char bus, unsigned devfn, unsigned wher } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -67,7 +67,7 @@ static unsigned int config_cmd2(unsigned char bus, unsigned devfn, unsigned wher int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -78,14 +78,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } diff --git a/util/romcc/tests/simple_test20.c b/util/romcc/tests/simple_test20.c index 71af19cf2f..1998853af1 100644 --- a/util/romcc/tests/simple_test20.c +++ b/util/romcc/tests/simple_test20.c @@ -33,27 +33,27 @@ static unsigned int pcibios_read_config_dword( /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -75,7 +75,7 @@ static unsigned int pcibios_read_config_dword( int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -86,14 +86,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -101,14 +101,14 @@ void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } void __console_tx_char(unsigned char byte) diff --git a/util/romcc/tests/simple_test27.c b/util/romcc/tests/simple_test27.c index d40e43f1c4..f278f62e8a 100644 --- a/util/romcc/tests/simple_test27.c +++ b/util/romcc/tests/simple_test27.c @@ -9,31 +9,31 @@ unsigned char inb(unsigned short port) } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#if TTYS0_BAUD == 115200 -#define TTYS0_DIV (1) +#if CONFIG_TTYS0_BAUD == 115200 +#define CONFIG_TTYS0_DIV (1) #else -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) #endif /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -55,7 +55,7 @@ unsigned char inb(unsigned short port) int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -66,14 +66,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } static void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -82,14 +82,14 @@ static void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } diff --git a/util/romcc/tests/simple_test4.c b/util/romcc/tests/simple_test4.c index 57af2af390..4f72dcad67 100644 --- a/util/romcc/tests/simple_test4.c +++ b/util/romcc/tests/simple_test4.c @@ -96,27 +96,27 @@ int log2(int value) /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -138,7 +138,7 @@ int log2(int value) int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -149,14 +149,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -164,14 +164,14 @@ void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } void __console_tx_char(unsigned char byte) diff --git a/util/vgabios/helper_mem.c b/util/vgabios/helper_mem.c index 50a303b45e..3e201c00a8 100644 --- a/util/vgabios/helper_mem.c +++ b/util/vgabios/helper_mem.c @@ -24,7 +24,7 @@ static const OptionInfoRec INT10Options[] = { }; #endif -#ifdef DEBUG +#ifdef CONFIG_DEBUG void dprint(unsigned long start, unsigned long size) { int i, j; @@ -44,7 +44,7 @@ void dprint(unsigned long start, unsigned long size) } printf("\n"); } -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ #if 0 #ifndef _PC diff --git a/util/vgabios/x86emu/include/x86emu.h b/util/vgabios/x86emu/include/x86emu.h index 6ddf39e24d..d1133029d4 100755 --- a/util/vgabios/x86emu/include/x86emu.h +++ b/util/vgabios/x86emu/include/x86emu.h @@ -155,7 +155,7 @@ void X86EMU_prepareForInt(int num); void X86EMU_exec(void); void X86EMU_halt_sys(void); -#ifdef DEBUG +#ifdef CONFIG_DEBUG #define HALT_SYS() \ printk("halt_sys: file %s, line %d\n", __FILE__, __LINE__), \ X86EMU_halt_sys() diff --git a/util/vgabios/x86emu/include/x86emu/fpu_regs.h b/util/vgabios/x86emu/include/x86emu/fpu_regs.h index 56e9a04d75..efc13ef2be 100755 --- a/util/vgabios/x86emu/include/x86emu/fpu_regs.h +++ b/util/vgabios/x86emu/include/x86emu/fpu_regs.h @@ -102,7 +102,7 @@ struct x86_fpu_registers { #endif /* X86_FPU_SUPPORT */ -#ifdef DEBUG +#ifdef CONFIG_DEBUG # define DECODE_PRINTINSTR32(t,mod,rh,rl) \ DECODE_PRINTF(t[(mod<<3)+(rh)]); # define DECODE_PRINTINSTR256(t,mod,rh,rl) \ diff --git a/util/vgabios/x86emu/include/x86emu/regs.h b/util/vgabios/x86emu/include/x86emu/regs.h index e77c56435b..ba6ea1ce2d 100755 --- a/util/vgabios/x86emu/include/x86emu/regs.h +++ b/util/vgabios/x86emu/include/x86emu/regs.h @@ -275,7 +275,7 @@ typedef struct { u32 mode; volatile int intr; /* mask of pending interrupts */ int debug; -#ifdef DEBUG +#ifdef CONFIG_DEBUG int check; u16 saved_ip; u16 saved_cs; diff --git a/util/vgabios/x86emu/src/x86emu/debug.c b/util/vgabios/x86emu/src/x86emu/debug.c index b69b86f8be..b39c30fa1b 100644 --- a/util/vgabios/x86emu/src/x86emu/debug.c +++ b/util/vgabios/x86emu/src/x86emu/debug.c @@ -42,7 +42,7 @@ /*----------------------------- Implementation ----------------------------*/ -#ifdef DEBUG +#ifdef CONFIG_DEBUG static void print_encoded_bytes (u16 s, u16 o); static void print_decoded_instruction (void); @@ -90,7 +90,7 @@ static void disassemble_forward (u16 seg, u16 off, int n) * flag associated with the "execution", and we are using a copy * of the register struct. All the major opcodes, once fully * decoded, have the following two steps: TRACE_REGS(r,m); - * SINGLE_STEP(r,m); which disappear if DEBUG is not defined to + * SINGLE_STEP(r,m); which disappear if CONFIG_DEBUG is not defined to * the preprocessor. The TRACE_REGS macro expands to: * * if (debug&DEBUG_DISASSEMBLE) @@ -354,7 +354,7 @@ static int parse_line (char *s, int *ps, int *n) } } -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ void x86emu_dump_regs (void) { diff --git a/util/vgabios/x86emu/src/x86emu/decode.c b/util/vgabios/x86emu/src/x86emu/decode.c index 910d1e9796..f31768c720 100644 --- a/util/vgabios/x86emu/src/x86emu/decode.c +++ b/util/vgabios/x86emu/src/x86emu/decode.c @@ -283,7 +283,7 @@ _INLINE u32 get_data_segment(void) case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS: return M.x86.R_SS; default: -#ifdef DEBUG +#ifdef CONFIG_DEBUG printk("error: should not happen: multiple overrides.\n"); #endif HALT_SYS(); @@ -303,7 +303,7 @@ NOTE: Do not inline this function as (*sys_rdX) is already inline! u8 fetch_data_byte( uint offset) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -322,7 +322,7 @@ NOTE: Do not inline this function as (*sys_rdX) is already inline! u16 fetch_data_word( uint offset) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -341,7 +341,7 @@ NOTE: Do not inline this function as (*sys_rdX) is already inline! u32 fetch_data_long( uint offset) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -362,7 +362,7 @@ u8 fetch_data_byte_abs( uint segment, uint offset) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -383,7 +383,7 @@ u16 fetch_data_word_abs( uint segment, uint offset) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -404,7 +404,7 @@ u32 fetch_data_long_abs( uint segment, uint offset) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -426,7 +426,7 @@ void store_data_byte( uint offset, u8 val) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -448,7 +448,7 @@ void store_data_word( uint offset, u16 val) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -470,7 +470,7 @@ void store_data_long( uint offset, u32 val) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -493,7 +493,7 @@ void store_data_byte_abs( uint offset, u8 val) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -516,7 +516,7 @@ void store_data_word_abs( uint offset, u16 val) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -539,7 +539,7 @@ void store_data_long_abs( uint offset, u32 val) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif diff --git a/util/vgabios/x86emu/src/x86emu/fpu.c b/util/vgabios/x86emu/src/x86emu/fpu.c index 5da363d6d5..54ca69bee6 100644 --- a/util/vgabios/x86emu/src/x86emu/fpu.c +++ b/util/vgabios/x86emu/src/x86emu/fpu.c @@ -50,7 +50,7 @@ void x86emuOp_esc_coprocess_d8(u8 X86EMU_UNUSED(op1)) END_OF_INSTR_NO_TRACE(); } -#ifdef DEBUG +#ifdef CONFIG_DEBUG static char *x86emu_fpu_op_d9_tab[] = { "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", @@ -89,7 +89,7 @@ static char *x86emu_fpu_op_d9_tab1[] = { "FRNDINT", "FSCALE", "ESC_D9", "ESC_D9", }; -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ /* opcode=0xd9 */ void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1)) @@ -100,7 +100,7 @@ void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (mod != 3) { DECODE_PRINTINSTR32(x86emu_fpu_op_d9_tab, mod, rh, rl); } else { @@ -294,7 +294,7 @@ void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1)) END_OF_INSTR_NO_TRACE(); } -#ifdef DEBUG +#ifdef CONFIG_DEBUG char *x86emu_fpu_op_da_tab[] = { "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", @@ -316,7 +316,7 @@ char *x86emu_fpu_op_da_tab[] = { "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", }; -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ /* opcode=0xda */ void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1)) @@ -384,7 +384,7 @@ void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1)) END_OF_INSTR_NO_TRACE(); } -#ifdef DEBUG +#ifdef CONFIG_DEBUG char *x86emu_fpu_op_db_tab[] = { "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", @@ -397,7 +397,7 @@ char *x86emu_fpu_op_db_tab[] = { "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", }; -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ /* opcode=0xdb */ void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1)) @@ -407,7 +407,7 @@ void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (mod != 3) { DECODE_PRINTINSTR32(x86emu_fpu_op_db_tab, mod, rh, rl); } else if (rh == 4) { /* === 11 10 0 nnn */ @@ -428,7 +428,7 @@ void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1)) } else { DECODE_PRINTF2("ESC_DB %0x\n", (mod << 6) + (rh << 3) + (rl)); } -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ switch (mod) { case 0: destoffset = decode_rm00_address(rl); @@ -504,7 +504,7 @@ void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1)) END_OF_INSTR_NO_TRACE(); } -#ifdef DEBUG +#ifdef CONFIG_DEBUG char *x86emu_fpu_op_dc_tab[] = { "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", "FCOMP\tQWORD PTR ", @@ -524,7 +524,7 @@ char *x86emu_fpu_op_dc_tab[] = { "FADD\t", "FMUL\t", "FCOM\t", "FCOMP\t", "FSUBR\t", "FSUB\t", "FDIVR\t", "FDIV\t", }; -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ /* opcode=0xdc */ void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1)) @@ -618,7 +618,7 @@ void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1)) END_OF_INSTR_NO_TRACE(); } -#ifdef DEBUG +#ifdef CONFIG_DEBUG static char *x86emu_fpu_op_dd_tab[] = { "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", @@ -634,7 +634,7 @@ static char *x86emu_fpu_op_dd_tab[] = { "ESC_DD\t2C,", "ESC_DD\t2D,", "ESC_DD\t2E,", "ESC_DD\t2F,", }; -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ /* opcode=0xdd */ void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1)) @@ -718,7 +718,7 @@ void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1)) END_OF_INSTR_NO_TRACE(); } -#ifdef DEBUG +#ifdef CONFIG_DEBUG static char *x86emu_fpu_op_de_tab[] = { @@ -741,7 +741,7 @@ static char *x86emu_fpu_op_de_tab[] = "FSUBRP\t", "FSUBP\t", "FDIVRP\t", "FDIVP\t", }; -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ /* opcode=0xde */ void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1)) @@ -837,7 +837,7 @@ void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1)) END_OF_INSTR_NO_TRACE(); } -#ifdef DEBUG +#ifdef CONFIG_DEBUG static char *x86emu_fpu_op_df_tab[] = { /* mod == 00 */ @@ -860,7 +860,7 @@ static char *x86emu_fpu_op_df_tab[] = { "ESC_DF\t3C,", "ESC_DF\t3D,", "ESC_DF\t3E,", "ESC_DF\t3F," }; -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ /* opcode=0xdf */ void x86emuOp_esc_coprocess_df(u8 X86EMU_UNUSED(op1)) diff --git a/util/vgabios/x86emu/src/x86emu/makefile b/util/vgabios/x86emu/src/x86emu/makefile index 3fbc363b34..2a82744e76 100644 --- a/util/vgabios/x86emu/src/x86emu/makefile +++ b/util/vgabios/x86emu/src/x86emu/makefile @@ -32,7 +32,7 @@ # ############################################################################# -.IMPORT .IGNORE: DEBUG +.IMPORT .IGNORE: CONFIG_DEBUG #---------------------------------------------------------------------------- # Define the lists of object files @@ -40,7 +40,7 @@ OBJECTS = sys$O decode$O ops$O ops2$O prim_ops$O fpu$O debug$O CFLAGS += -DSCITECH -.IF $(DEBUG) +.IF $(CONFIG_DEBUG) CFLAGS += -DDEBUG .ENDIF LIBCLEAN = *.dll *.lib *.a diff --git a/util/vgabios/x86emu/src/x86emu/ops.c b/util/vgabios/x86emu/src/x86emu/ops.c index 1b702500a4..b947e60bb8 100644 --- a/util/vgabios/x86emu/src/x86emu/ops.c +++ b/util/vgabios/x86emu/src/x86emu/ops.c @@ -76,7 +76,7 @@ /* constant arrays to do several instructions in just one function */ -#ifdef DEBUG +#ifdef CONFIG_DEBUG static char *x86emu_GenOpName[8] = { "ADD", "OR", "ADC", "SBB", "AND", "SUB", "XOR", "CMP"}; #endif @@ -157,7 +157,7 @@ static u32 (*opcD1_long_operation[])(u32 s, u8 d) = sar_long, }; -#ifdef DEBUG +#ifdef CONFIG_DEBUG static char *opF6_names[8] = { "TEST\t", "", "NOT\t", "NEG\t", "MUL\t", "IMUL\t", "DIV\t", "IDIV\t" }; @@ -1278,7 +1278,7 @@ void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -1356,7 +1356,7 @@ void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -1472,7 +1472,7 @@ void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -1548,7 +1548,7 @@ void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3080,7 +3080,7 @@ void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3155,7 +3155,7 @@ void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3632,7 +3632,7 @@ void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3703,7 +3703,7 @@ void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3805,7 +3805,7 @@ void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3878,7 +3878,7 @@ void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -4863,7 +4863,7 @@ void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) /* Yet another special case instruction. */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -4927,7 +4927,7 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) /* Yet another special case instruction. */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings diff --git a/util/vgabios/x86emu/src/x86emu/x86emu/debug.h b/util/vgabios/x86emu/src/x86emu/x86emu/debug.h index 95a109b261..7bf62c7995 100755 --- a/util/vgabios/x86emu/src/x86emu/x86emu/debug.h +++ b/util/vgabios/x86emu/src/x86emu/x86emu/debug.h @@ -48,7 +48,7 @@ #define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ #define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset*/ -#ifdef DEBUG +#ifdef CONFIG_DEBUG # define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) # define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) # define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) @@ -60,7 +60,7 @@ # define CHECK_DATA_ACCESS() #endif -#ifdef DEBUG +#ifdef CONFIG_DEBUG # define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) # define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) # define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) @@ -99,7 +99,7 @@ # define DEBUG_DECODE_NOPRINT() 0 #endif -#ifdef DEBUG +#ifdef CONFIG_DEBUG # define DECODE_PRINTF(x) if (DEBUG_DECODE()) \ x86emu_decode_printf(x) @@ -129,7 +129,7 @@ # define SAVE_IP_CS(x,y) #endif -#ifdef DEBUG +#ifdef CONFIG_DEBUG #define TRACE_REGS() \ if (DEBUG_DISASSEMBLE()) { \ x86emu_just_disassemble(); \ @@ -140,7 +140,7 @@ # define TRACE_REGS() #endif -#ifdef DEBUG +#ifdef CONFIG_DEBUG # define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() #else # define SINGLE_STEP() @@ -150,7 +150,7 @@ TRACE_REGS(); \ SINGLE_STEP() -#ifdef DEBUG +#ifdef CONFIG_DEBUG # define START_OF_INSTR() # define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); # define END_OF_INSTR_NO_TRACE() x86emu_end_instr(); @@ -160,7 +160,7 @@ # define END_OF_INSTR_NO_TRACE() #endif -#ifdef DEBUG +#ifdef CONFIG_DEBUG # define CALL_TRACE(u,v,w,x,s) \ if (DEBUG_TRACECALLREGS()) \ x86emu_dump_regs(); \ @@ -176,7 +176,7 @@ # define RETURN_TRACE(n,u,v) #endif -#ifdef DEBUG +#ifdef CONFIG_DEBUG #define DB(x) x #else #define DB(x) |