diff options
| author | Jon Murphy <jpmurphy@google.com> | 2023-03-29 18:28:42 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-19 21:50:59 +0000 |
| commit | fb5d1573c35876b0557b5a117d2dde025e88b956 (patch) | |
| tree | 065b3669d8d604ac90e204904540b31d8cc015ff | |
| parent | e4fd7dc9ff7ff6cd5dac32f27bd069d9d350f275 (diff) | |
mb/google/myst: Add initial fch irq routing
Add initial fch irq routing table for Myst.
BUG=b:275946702
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ic81c3cbfbb30a0beb3c4083624cf19abe6d1e694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74109
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/myst/mainboard.c | 40 |
1 files changed, 39 insertions, 1 deletions
diff --git a/src/mainboard/google/myst/mainboard.c b/src/mainboard/google/myst/mainboard.c index e433c98035..3a25e8c834 100644 --- a/src/mainboard/google/myst/mainboard.c +++ b/src/mainboard/google/myst/mainboard.c @@ -5,10 +5,48 @@ #include <baseboard/variants.h> #include <console/console.h> #include <device/device.h> +#include <soc/acpi.h> #include <variant/ec.h> +/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is + accessed via I/O ports 0xc00/0xc01. */ + +/* + * This controls the device -> IRQ routing. + * + * Hardcoded IRQs: + * 0: timer < soc/amd/common/acpi/lpc.asl + * 1: i8042 - Keyboard + * 2: cascade + * 8: rtc0 <- soc/amd/common/acpi/lpc.asl + * 9: acpi <- soc/amd/common/acpi/lpc.asl + */ + static const struct fch_irq_routing fch_irq_map[] = { - { 0, 0x00, 0x00 }, + { PIRQ_A, 12, PIRQ_NC }, + { PIRQ_B, 14, PIRQ_NC }, + { PIRQ_C, 15, PIRQ_NC }, + { PIRQ_D, 12, PIRQ_NC }, + { PIRQ_E, 14, PIRQ_NC }, + { PIRQ_F, 15, PIRQ_NC }, + { PIRQ_G, 12, PIRQ_NC }, + { PIRQ_H, 14, PIRQ_NC }, + + { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, + { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIO, 11, 11 }, + { PIRQ_I2C0, 10, 10 }, + { PIRQ_I2C1, 7, 7 }, + { PIRQ_I2C2, 6, 6 }, + { PIRQ_I2C3, 5, 5 }, + { PIRQ_UART0, 4, 4 }, + { PIRQ_UART1, 3, 3 }, + + /* The MISC registers are not interrupt numbers */ + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0x91, 0x00 }, + { PIRQ_HPET_L, 0x00, 0x00 }, + { PIRQ_HPET_H, 0x00, 0x00 }, }; const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) |