nb/intel/sandybridge: add macros for byte lane register offsets

This patch doesn't change the resulting binary of a timeless build.

Change-Id: Ife0e70699df3efa162f8f6c0fd8c2928887fda2d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

2 files changed, 19 insertions, 14 deletions

diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 702addaf92..c69c827136 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -1155,8 +1155,7 @@ void program_timings(ramctr_timing *ctrl, int channel)
 		     shift_402x) << (8 * slotrank);
 
 		FOR_ALL_LANES {
-			MCHBAR32(lane_base[lane] +
-				(0x10 + (channel * 0x100) + (slotrank * 4))) =
+			MCHBAR32(lane_base[lane] + GDCRRX(channel, slotrank)) =
 			    (((ctrl->timings[channel][slotrank].lanes[lane].
 			       timA + shift) & 0x3f)
 			     |
@@ -1169,8 +1168,7 @@ void program_timings(ramctr_timing *ctrl, int channel)
 			     | ((ctrl->timings[channel][slotrank].lanes[lane].
 				falling + shift) << 20));
 
-			MCHBAR32(lane_base[lane] +
-				(0x20 + (channel * 0x100) + (slotrank * 4))) =
+			MCHBAR32(lane_base[lane] + GDCRTX(channel, slotrank)) =
 			    (((ctrl->timings[channel][slotrank].lanes[lane].
 			       timC + shift) & 0x3f)
 			     |
@@ -1230,8 +1228,8 @@ static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank,
 			  int lane)
 {
 	u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA;
-	return ((MCHBAR32(lane_base[lane] + (4 + (channel * 0x100) +
-		  (((timA / 32) & 1) * 4))) >> (timA % 32)) & 1);
+	return ((MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT(channel, (timA / 32) & 1)) >>
+		(timA % 32)) & 1);
 }
 
 struct run {
@@ -1891,10 +1889,9 @@ static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank)
 		test_timB(ctrl, channel, slotrank);
 
 		FOR_ALL_LANES {
-			statistics[lane][timB] =
-			    !((MCHBAR32(lane_base[lane] + (4 +
-				(channel * 0x100) + (((timB / 32) & 1) * 4)))
-			       >> (timB % 32)) & 1);
+			statistics[lane][timB] =  !((MCHBAR32(lane_base[lane] +
+				GDCRTRAININGRESULT(channel, (timB / 32) & 1)) >>
+				(timB % 32)) & 1);
 		}
 	}
 	FOR_ALL_LANES {
@@ -2015,9 +2012,9 @@ static void adjust_high_timB(ramctr_timing *ctrl)
 
 		wait_for_iosav(channel);
 		FOR_ALL_LANES {
-			u64 res = MCHBAR32(lane_base[lane] + 4 + (channel * 0x100) + (0 * 4));
+			u64 res = MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT1(channel));
 			res |= ((u64) MCHBAR32(lane_base[lane] +
-				(4 + (channel * 0x100) + (1 * 4)))) << 32;
+				GDCRTRAININGRESULT2(channel))) << 32;
 			old = ctrl->timings[channel][slotrank].lanes[lane].timB;
 			ctrl->timings[channel][slotrank].lanes[lane].timB +=
 				get_timB_high_adjust(res) * 64;
@@ -3023,9 +3020,9 @@ void write_controller_mr(ramctr_timing *ctrl)
 	int channel, slotrank;
 
 	FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
-		MCHBAR32(lane_base[slotrank] + (0x0004 + (channel * 0x100) + (0 * 4))) =
+		MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT1(channel)) =
 			make_mr0(ctrl, slotrank);
-		MCHBAR32(lane_base[slotrank] + (0x0004 + (channel * 0x100) + (1 * 4))) =
+		MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT2(channel)) =
 			make_mr1(ctrl, slotrank, channel);
 	}
 }
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 53fb3eb9b0..ef1df061d6 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -132,6 +132,7 @@ enum platform_type {
 #define Ly(r, y)	((r) + ((y) * 4))
 #define Cx(r, x)	((r) + ((x) * 0x400))
 #define CxLy(r, x, y)	((r) + ((x) * 0x400) + ((y) * 4))
+#define GzLy(r, z, y)	((r) + ((z) * 0x100) + ((y) * 4))
 
 /* byte lane training register base addresses */
 #define LANEBASE_B0	0x0000
@@ -144,6 +145,13 @@ enum platform_type {
 #define LANEBASE_B7	0x1600
 #define LANEBASE_ECC	0x0800 /* ECC lane is in the middle of the data lanes */
 
+/* byte lane register offsets */
+#define GDCRTRAININGRESULT(ch, y)	GzLy(0x0004, ch, y) /* Test results for PI config */
+#define GDCRTRAININGRESULT1(ch)		GDCRTRAININGRESULT(ch, 0) /* 0x0004 */
+#define GDCRTRAININGRESULT2(ch)		GDCRTRAININGRESULT(ch, 1) /* 0x0008 */
+#define GDCRRX(ch, rank)		GzLy(0x10, ch, rank) /* Time setting for lane Rx */
+#define GDCRTX(ch, rank)		GzLy(0x20, ch, rank) /* Time setting for lane Tx */
+
 /* Register definitions */
 #define GDCRCLKRANKSUSED_ch(ch)		Gz(0x0c00, ch) /* Indicates which rank is populated */
 #define GDCRCLKCOMP_ch(ch)		Gz(0x0c04, ch) /* RCOMP result register */