diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-04-22 13:31:05 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-04-23 17:15:23 +0000 |
| commit | fa2854d3dc6d5a56f465e6aef4621503ca5f5e34 (patch) | |
| tree | e23b22dec7ecdd8e6e9dd3927fd5d549c83ca709 | |
| parent | ecc165b789f87d7713381014b79875282135c95f (diff) | |
soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg
Typically, the SPIBAR_HSFSTS_W1C_BITS macro is used to clear all HSFSTS
register bit-fields with the W1C attribute.
So far SPIBAR_HSFSTS_W1C_BITS is 1 byte width hence, missed to clear
SAF_CE (bit 8).
This patch expands the `SPIBAR_HSFSTS_W1C_BITS` macro to include
SAF_CE (bit 8).
BUG=b:211954778
TEST=Able to build google/brya with this patch and clear SPI controller
HSFSTS_CTL register Bits 0 to 4 and 8.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ifb58cef61118ca967e85226c1cf9db585e9ae4f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
| -rw-r--r-- | src/soc/intel/common/block/fast_spi/fast_spi_def.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index 0be3dcd255..4012c29624 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -75,7 +75,7 @@ #define SPIBAR_HSFSTS_AEL (1 << 2) #define SPIBAR_HSFSTS_FCERR (1 << 1) #define SPIBAR_HSFSTS_FDONE (1 << 0) -#define SPIBAR_HSFSTS_W1C_BITS 0xff +#define SPIBAR_HSFSTS_W1C_BITS 0x1ff /* Bit definitions for FADDR (0x08) register */ #define SPIBAR_FADDR_MASK 0x7ffffff |