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authorArthur Heymans <arthur@aheymans.xyz>2022-05-13 14:50:38 +0200
committerMartin L Roth <gaumless@gmail.com>2023-11-23 17:50:55 +0000
commitf9b6f2d3558903ec8a0fec055d363ac6fb24c0df (patch)
tree7d944935cdc1acf6e9722a10097f3afb814b1069
parent62f788e24469c0e12dbf427594cc8150ffa4336f (diff)
arch/riscv/romstage: Start from assembly
Without this it would use the exception handler from the previous stage. Change-Id: I79d875aca6cd0cffe482e4ebb5f388af0adf6aed Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68840 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/arch/riscv/Makefile.inc2
-rw-r--r--src/arch/riscv/include/arch/header.ld4
-rw-r--r--src/arch/riscv/include/arch/stages.h11
-rw-r--r--src/arch/riscv/romstage.S38
-rw-r--r--src/arch/riscv/romstage.c21
5 files changed, 39 insertions, 37 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index e912120d85..bbd39590d2 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -96,7 +96,7 @@ endif #CONFIG_ARCH_BOOTBLOCK_RISCV
################################################################################
ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y)
-romstage-y += romstage.c
+romstage-y += romstage.S
# Build the romstage
diff --git a/src/arch/riscv/include/arch/header.ld b/src/arch/riscv/include/arch/header.ld
index ddb618c293..bca852c8e2 100644
--- a/src/arch/riscv/include/arch/header.ld
+++ b/src/arch/riscv/include/arch/header.ld
@@ -8,8 +8,4 @@ PHDRS
to_load PT_LOAD;
}
-#if ENV_BOOTBLOCK || ENV_RAMSTAGE
ENTRY(_start)
-#else
-ENTRY(stage_entry)
-#endif
diff --git a/src/arch/riscv/include/arch/stages.h b/src/arch/riscv/include/arch/stages.h
deleted file mode 100644
index f9de2b5502..0000000000
--- a/src/arch/riscv/include/arch/stages.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __ARCH_STAGES_H
-#define __ARCH_STAGES_H
-
-#include <main_decl.h>
-
-void stage_entry(int hart_id, void *fdt)
- __attribute__((section(".text.stage_entry")));
-
-#endif
diff --git a/src/arch/riscv/romstage.S b/src/arch/riscv/romstage.S
new file mode 100644
index 0000000000..bf85acbb8f
--- /dev/null
+++ b/src/arch/riscv/romstage.S
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/encoding.h>
+#include <bits.h>
+#include <mcall.h>
+
+.section ".text._start", "ax", %progbits
+.globl _start
+_start:
+ # initialize stack point for each hart
+ # and the stack must be page-aligned.
+ # 0xDEADBEEF used to check stack overflow
+ csrr a0, mhartid
+ la t0, _stack
+ slli t1, a0, RISCV_PGSHIFT
+ add t0, t0, t1
+ li t1, 0xDEADBEEF
+ STORE t1, 0(t0)
+ li t1, RISCV_PGSIZE - HLS_SIZE
+ add sp, t0, t1
+
+ # initialize hart-local storage
+ csrr a0, mhartid
+ call hls_init
+
+ li a0, CONFIG_RISCV_WORKING_HARTID
+ call smp_pause
+
+ # initialize entry of interrupt/exception
+ la t0, trap_entry
+ csrw mtvec, t0
+
+ # clear any pending interrupts
+ csrwi mip, 0
+
+ # set up the mstatus register
+ call mstatus_init
+ tail main
diff --git a/src/arch/riscv/romstage.c b/src/arch/riscv/romstage.c
deleted file mode 100644
index c7340b2719..0000000000
--- a/src/arch/riscv/romstage.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * Entry points must be placed at the location the previous stage jumps
- * to (the lowest address in the stage image). This is done by giving
- * stage_entry() its own section in .text and placing it first in the
- * linker script.
- */
-
-#include <arch/stages.h>
-#include <arch/smp/smp.h>
-#include <mcall.h>
-
-void stage_entry(int hart_id, void *fdt)
-{
- HLS()->hart_id = hart_id;
- HLS()->fdt = fdt;
- smp_pause(CONFIG_RISCV_WORKING_HARTID);
-
- main();
-}