diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-05-23 11:53:17 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-05-24 05:09:25 +0000 |
| commit | f8d4b50a67858f020bc83a4176cca1e3d40bf703 (patch) | |
| tree | b46a63d772d2337297c448d02ddc216bab483919 | |
| parent | b60e69bde852b59db41df047794086ef25ff5f43 (diff) | |
soc/intel/alderlake: Drop unused `PCH_DEV_SLOT_LPC` macro
This patch drops the unused `PCH_DEV_SLOT_LPC` macro from the
Alder Lake SoC PCI device list.
BUG=none
TEST=Able to build and boot taeko, google board.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib2ae40fcc4499de34534f27f03b4c359c37409e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/pci_devs.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index b7196df0c3..ea1053b84f 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -211,7 +211,6 @@ #define PCH_DEV_GSPI1 _PCH_DEV(SIO5, 3) #define PCH_DEV_SLOT_ESPI 0x1f -#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI #define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0) #define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1) #define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2) |