diff options
| author | Reka Norman <rekanorman@google.com> | 2022-12-16 15:20:44 +1100 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-12-17 20:33:52 +0000 |
| commit | f7bb72333a56c2df111dd1f94b5bbc54ffabe4bd (patch) | |
| tree | 532b97500d0312037f773f7fc85f434e2921896b | |
| parent | e8bef613df5e6967250e155eed6635c1f6288a56 (diff) | |
soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE for ADL-N
On nissa, sending EOP late improves boot time by about 57ms.
Before (SOC_INTEL_CSE_SEND_EOP_EARLY):
943:after sending EOP to ME 931,206 (58,431)
943:after sending EOP to ME 932,911 (58,427)
943:after sending EOP to ME 930,908 (58,429)
943:after sending EOP to ME 941,357 (61,748)
943:after sending EOP to ME 933,289 (62,050)
943:after sending EOP to ME 939,578 (62,453)
943:after sending EOP to ME 932,491 (62,050)
943:after sending EOP to ME 929,693 (62,655)
943:after sending EOP to ME 942,247 (62,654)
943:after sending EOP to ME 936,984 (61,751)
After (SOC_INTEL_CSE_SEND_EOP_LATE):
943:after sending EOP to ME 1,107,816 (3,498)
943:after sending EOP to ME 1,053,286 (25,212)
943:after sending EOP to ME 1,124,095 (3,511)
943:after sending EOP to ME 1,098,591 (3,498)
943:after sending EOP to ME 1,107,772 (3,499)
943:after sending EOP to ME 1,080,008 (45,969)
943:after sending EOP to ME 1,081,754 (8,024)
943:after sending EOP to ME 1,109,193 (4,102)
943:after sending EOP to ME 1,088,866 (4,201)
943:after sending EOP to ME 1,081,684 (4,203)
BUG=b:247902068
TEST=EOP time is improved on nissa (measurements above).
Change-Id: I2389831b4ab62f247193b5b0c5ec201e12eaa3db
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70849
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 5f24e37036..3526929a22 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -117,6 +117,8 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET + select SOC_INTEL_CSE_SEND_EOP_EARLY if !SOC_INTEL_ALDERLAKE_PCH_N + select SOC_INTEL_CSE_SEND_EOP_LATE if SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select HAVE_INTEL_COMPLIANCE_TEST_MODE @@ -458,9 +460,6 @@ config USE_COREBOOT_MP_INIT endchoice -config SOC_INTEL_CSE_SEND_EOP_EARLY - default y - if STITCH_ME_BIN config CSE_BPDT_VERSION |