diff options
| author | Husni Faiz <ahamedhusni73@gmail.com> | 2022-09-05 15:28:53 +0530 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-09-16 17:02:39 +0000 |
| commit | f571ce5c67170037bb864465d96972fb63116561 (patch) | |
| tree | ac07e8f4db857ee031397ad4e9e36c4542706198 | |
| parent | 67300f88cd1e950ca18c4e7bdd770ef18b8c06dd (diff) | |
bd82x6x/early_pch: enable smbus in bootblock stage
SMBus is typically enabled in the ROMSTAGE. To get the
BOOTBLOCK console message, the SMBus should be enabled
in the BOOTBLOCK stage.
Change-Id: I97d0afb013ede428383acaa0aa97ab04fe80e2a4
Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67340
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_pch.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/common/Makefile.inc | 7 |
2 files changed, 8 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index bbbc5e6f7a..e4e002d805 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -310,6 +310,6 @@ void early_pch_init(void) setup_pch_gpios(&mainboard_gpio_map); - if (ENV_RAMINIT) + if (ENV_RAMINIT || (CONFIG(CONSOLE_I2C_SMBUS) && ENV_INITIAL_STAGE)) enable_smbus(); } diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 1fc3a63066..fe61af101f 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -9,10 +9,17 @@ all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET) += hpet.c all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME) += me.c +ifeq ($(CONFIG_CONSOLE_I2C_SMBUS),y) +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c +endif romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c +ifeq ($(CONFIG_CONSOLE_I2C_SMBUS),y) +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c +else romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c +endif ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus_ops.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c |