diff options
| author | Tony Huang <tony-huang@quanta.corp-partner.google.com> | 2022-07-29 10:10:44 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-03 12:45:52 +0000 |
| commit | f3e5f9966f2598e51f52e8d06c543958327a7913 (patch) | |
| tree | 408507b08ef0adc34bb6ffdac9fc3d7870c67f88 | |
| parent | d307d0d2fb69f960ba300e27937105135f1a1a9c (diff) | |
mb/google/brya/variants/agah: set tcc_offset to 3
Set tcc_offset value to 3 in devicetree for Thermal Control Circuit
(TCC) activation feature. This value is suggested by Thermal team.
BUG=b:240600260
TEST=emerge-draco coreboot
verified by thermal team
Change-Id: I3044643d52f1d6e883beb3ec87a77f32d086f46c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/agah/overridetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb index ae6ad4a22d..c459e034f3 100644 --- a/src/mainboard/google/brya/variants/agah/overridetree.cb +++ b/src/mainboard/google/brya/variants/agah/overridetree.cb @@ -39,6 +39,7 @@ chip soc/intel/alderlake }, }" + register "tcc_offset" = "3" # TCC of 97 register "sagv" = "SaGv_Disabled" register "tcss_aux_ori" = "0x10" register "typec_aux_bias_pads[2]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" |