diff options
| author | Mariusz Szafrański <mariuszx.szafranski@intel.com> | 2021-08-26 06:07:48 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-28 21:27:46 +0000 |
| commit | f3c84024b18239bacef6ed30923fe68ac44c0749 (patch) | |
| tree | d392a51f344df58fdc6566f0ac2aaab0b7622984 | |
| parent | f8df08213d8abff2e53e90cc8f03056ff5a8e24a (diff) | |
mainboard/intel/harcuvar: Remove hardcoded lapic 0 from devicetree.cb
This change follows other Intel SoCs common way to support SKUs with
bsp lapic_id != 0 by removing hardcoded lapic 0 from devicetree.cb and
allowing its detection at boottime. It completes support for HCV/DNV
after base SoC patch: commit ba936ce5db819d5ecb34e83a998b2390ecbdc4b9
soc/intel/denverton_ns: Ensure CPU device has a valid link
Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/
"A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538)."
Change-Id: I88f60f64d2beb2768ec9833de582d7901f456b11
Signed-off-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/mainboard/intel/harcuvar/devicetree.cb | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/mainboard/intel/harcuvar/devicetree.cb b/src/mainboard/intel/harcuvar/devicetree.cb index 57e25bc35f..e19cc5ec96 100644 --- a/src/mainboard/intel/harcuvar/devicetree.cb +++ b/src/mainboard/intel/harcuvar/devicetree.cb @@ -31,9 +31,7 @@ chip soc/intel/denverton_ns register "ipc2" = "0x00000000" # IPC2 register "ipc3" = "0x00000000" # IPC3 - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge |