mb/google/nissa/var/nivviks: Add support for NVMe and UFS

Enable either eMMC, NVMe or UFS based on fw_config. NVMe and UFS are
only supported on nirwen, an additional nissa variant based on nivviks
and sharing the nivviks coreboot target.

BUG=b:218929856
TEST=Boot to OS on nivviks to check that eMMC still works. NVMe and UFS
will be tested once nirwen boards are available.

Change-Id: Ibdb122ef35920c962d7bd9f3f238a5d548112282
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

4 files changed, 84 insertions, 1 deletions

diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
index dfc0a85b41..2ce9a7d68d 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
@@ -1,3 +1,11 @@
+fw_config
+	field STORAGE 30 31
+		option STORAGE_EMMC		0
+		option STORAGE_NVME		1
+		option STORAGE_UFS		2
+	end
+end
+
 chip soc/intel/alderlake
 
 	# GPE configuration
diff --git a/src/mainboard/google/brya/variants/nivviks/fw_config.c b/src/mainboard/google/brya/variants/nivviks/fw_config.c
index 6d8bab3ea8..4c7c626b9e 100644
--- a/src/mainboard/google/brya/variants/nivviks/fw_config.c
+++ b/src/mainboard/google/brya/variants/nivviks/fw_config.c
@@ -56,10 +56,48 @@ static const struct pad_config wfc_disable_pads[] = {
 	PAD_NC(GPP_R7, NONE),
 };
 
+static const struct pad_config emmc_disable_pads[] = {
+	/* I7  : EMMC_CMD */
+	PAD_NC(GPP_I7, NONE),
+	/* I8  : EMMC_D0 */
+	PAD_NC(GPP_I8, NONE),
+	/* I9  : EMMC_D1 */
+	PAD_NC(GPP_I9, NONE),
+	/* I10 : EMMC_D2 */
+	PAD_NC(GPP_I10, NONE),
+	/* I11 : EMMC_D3 */
+	PAD_NC(GPP_I11, NONE),
+	/* I12 : EMMC_D4 */
+	PAD_NC(GPP_I12, NONE),
+	/* I13 : EMMC_D5 */
+	PAD_NC(GPP_I13, NONE),
+	/* I14 : EMMC_D6 */
+	PAD_NC(GPP_I14, NONE),
+	/* I15 : EMMC_D7 */
+	PAD_NC(GPP_I15, NONE),
+	/* I16 : EMMC_RCLK */
+	PAD_NC(GPP_I16, NONE),
+	/* I17 : EMMC_CLK */
+	PAD_NC(GPP_I17, NONE),
+	/* I18 : EMMC_RST_L */
+	PAD_NC(GPP_I18, NONE),
+};
+
+static const struct pad_config nvme_disable_pads[] = {
+	/* B4  : SSD_PERST_L */
+	PAD_NC(GPP_B4, NONE),
+	/* D6  : SSD_CLKREQ_ODL */
+	PAD_NC(GPP_D6, NONE),
+	/* D11 : EN_PP3300_SSD */
+	PAD_NC(GPP_D11, NONE),
+	/* E17 : SSD_PLN_L */
+	PAD_NC(GPP_E17, NONE),
+};
+
 static void fw_config_handle(void *unused)
 {
 	if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
-		if (board_id() == 2) {
+		if (board_id() >= 2) {
 			printk(BIOS_INFO, "Disable LTE-related GPIO pins on nirwen.\n");
 			gpio_configure_pads(
 				lte_disable_pads_nirwen,
@@ -83,5 +121,15 @@ static void fw_config_handle(void *unused)
 		printk(BIOS_INFO, "Disable MIPI WFC GPIO pins.\n");
 		gpio_configure_pads(wfc_disable_pads, ARRAY_SIZE(wfc_disable_pads));
 	}
+
+	if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) {
+		printk(BIOS_INFO, "Disable eMMC SSD GPIO pins.\n");
+		gpio_configure_pads(emmc_disable_pads, ARRAY_SIZE(emmc_disable_pads));
+	}
+
+	if (board_id() >= 2 && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) {
+		printk(BIOS_INFO, "Disable NVMe SSD GPIO pins.\n");
+		gpio_configure_pads(nvme_disable_pads, ARRAY_SIZE(nvme_disable_pads));
+	}
 }
 BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brya/variants/nivviks/gpio.c b/src/mainboard/google/brya/variants/nivviks/gpio.c
index 2eceb8661a..6d07a37bfc 100644
--- a/src/mainboard/google/brya/variants/nivviks/gpio.c
+++ b/src/mainboard/google/brya/variants/nivviks/gpio.c
@@ -32,10 +32,16 @@ static const struct pad_config board_id0_overrides[] = {
 
 /* Pad configuration in ramstage for nirwen */
 static const struct pad_config override_gpio_table_nirwen[] = {
+	/* B4  : SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
 	/* D6  : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */
 	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	/* D11 : EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_D11, 1, DEEP),
 	/* E13  : SRCCLKREQ1# ==> WWAN_EN */
 	PAD_CFG_GPO(GPP_E13, 1, DEEP),
+	/* E17 : SSD_PLN_L */
+	PAD_CFG_GPO(GPP_E17, 1, PLTRST),
 };
 
 /* Early pad configuration in bootblock for nivviks */
@@ -66,6 +72,8 @@ static const struct pad_config early_gpio_table[] = {
 
 /* Early pad configuration in bootblock for nirwen */
 static const struct pad_config early_gpio_table_nirwen[] = {
+	/* B4  : SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
 	/* F12 : GSXDOUT ==> WWAN_RST_L */
 	PAD_CFG_GPO(GPP_F12, 0, DEEP),
 	/* H12 : UART0_RTS# ==> SD_PERST_L */
@@ -86,11 +94,15 @@ static const struct pad_config early_gpio_table_nirwen[] = {
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* D11 : EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_D11, 1, DEEP),
 	/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
 	PAD_CFG_GPO(GPP_H13, 1, DEEP),
 };
 
 static const struct pad_config romstage_gpio_table[] = {
+	/* B4  : SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
 	/* H12 : UART0_RTS# ==> SD_PERST_L */
 	PAD_CFG_GPO(GPP_H12, 1, DEEP),
 };
diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
index 66c88740d4..cb0c46bd81 100644
--- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
@@ -267,6 +267,21 @@ chip soc/intel/alderlake
 			end
 			probe SD_CARD SD_GL9750S
 		end
+		device ref pcie_rp9 on
+			# Enable NVMe SSD PCIe 9-12 using clk 1
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src = 1,
+				.clk_req = 1,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			probe STORAGE STORAGE_NVME
+		end
+		device ref emmc on
+			probe STORAGE STORAGE_EMMC
+		end
+		device ref ufs on
+			probe STORAGE STORAGE_UFS
+		end
 		device ref pch_espi on
 			chip ec/google/chromeec
 				use conn0 as mux_conn[0]