diff options
| author | Yidi Lin <yidi.lin@mediatek.com> | 2021-01-26 21:31:56 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-28 09:25:00 +0000 |
| commit | ef5c235541a630fd5e6ab90c3913db55313e64d2 (patch) | |
| tree | 482f4a5db92271742232226a19d2de7afa158478 | |
| parent | 0bea950a479cc5b3b3bc8f362fc356ad43f9f892 (diff) | |
mb/google/asurada: Improve boot time by raising little CPU frequency
Raise little CPU to 2GHz at romstage to improve boot time.
BUG=b:177389446
TEST=observe boot time by `cbmem`
Before: 1,062,359 us
After: 907,458 us
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I723a916d7f708627525ef11e3c5ea0b381f269aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
| -rw-r--r-- | src/mainboard/google/asurada/romstage.c | 14 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/Makefile.inc | 2 |
2 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/google/asurada/romstage.c b/src/mainboard/google/asurada/romstage.c index 47c1fb2268..67b43e227a 100644 --- a/src/mainboard/google/asurada/romstage.c +++ b/src/mainboard/google/asurada/romstage.c @@ -2,11 +2,14 @@ #include <arch/stages.h> #include <console/console.h> +#include <delay.h> #include <fmap.h> #include <soc/dramc_param.h> #include <soc/emi.h> #include <soc/mmu_operations.h> +#include <soc/mt6315.h> #include <soc/mt6359p.h> +#include <soc/pll_common.h> /* This must be defined in chromeos.fmd in same name and size. */ #define CALIBRATION_REGION "RW_DDR_TRAINING" @@ -42,9 +45,20 @@ static struct dramc_param_ops dparam_ops = { .write_to_flash = &write_calibration_data_to_flash, }; +static void raise_little_cpu_freq(void) +{ + mt6359p_buck_set_voltage(MT6359P_SRAM_PROC2, 1000 * 1000); + mt6315_buck_set_voltage(MT6315_CPU, MT6315_BUCK_3, 925 * 1000); + udelay(200); + mt_pll_raise_little_cpu_freq(2000 * MHz); + mt_pll_raise_cci_freq(1400 * MHz); +} + void platform_romstage_main(void) { mt6359p_romstage_init(); + mt6315_romstage_init(); + raise_little_cpu_freq(); mt_mem_init(&dparam_ops); mtk_mmu_after_dram(); } diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index ad8b3d984f..9d22ef2b64 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -36,10 +36,12 @@ romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += memory.c dramc_param.c ../common/memory_test.c +romstage-y += ../common/pll.c pll.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c romstage-y += ../common/uart.c romstage-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c +romstage-y += mt6315.c romstage-y += mt6359p.c ramstage-y += ../common/auxadc.c |