cpu/x86: Link page tables in stage if possible

When switching back and forth between 32 to 64 bit mode, for example to
call a 32-bits FSP or to call the payload, new page tables in the
respective stage will be linked.

The advantages of this approach are:
- No need to determine a good place for page tables in CBFS that does
  not overlap.
- Works with non memory mapped flash (however all coreboot targets
  currently do support this)
- If later stages can use their own page tables which fits better with
  the vboot RO/RW flow

A disadvantage is that it increases the stage size. This could be
improved upon by using 1G pages and generating the pages at runtime.

Note: qemu cannot have the page tables in the RO boot medium and needs
to relocate them at runtime. This is why keeping the existing code with
page tables in CBFS is done for now.

TEST: Booted to payload on google/vilbox and qemu/q35

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80337
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

13 files changed, 28 insertions, 10 deletions

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 610321f9a0..3f97644567 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -83,9 +83,13 @@ config USE_EXP_X86_64_SUPPORT
 	  is an experimental option: do not enable unless one wants to test it
 	  and has the means to recover a system when coreboot fails to boot.
 
+config PAGE_TABLES_IN_CBFS
+	bool
+	default n
+
 config ARCH_X86_64_PGTBL_LOC
 	hex "x86_64 page table location in CBFS"
-	depends on ARCH_BOOTBLOCK_X86_64
+	depends on ARCH_BOOTBLOCK_X86_64 && PAGE_TABLES_IN_CBFS
 	default 0xfffe9000
 	help
 	  The position where to place pagetables. Needs to be known at
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
index 2e4d9c8074..227ddf4c22 100644
--- a/src/cpu/intel/car/core2/cache_as_ram.S
+++ b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -163,7 +163,7 @@ addrsize_set_high:
 	subl	$4, %esp
 
 #if ENV_X86_64
-	setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
+	setup_longmode $PM4LE
 
 	movd	%mm2, %rdi
 	shlq	$32, %rdi
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index 578bf03afd..9485cd44fb 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -214,7 +214,7 @@ end_microcode_update:
 	andl	$0xfffffff0, %esp
 
 #if ENV_X86_64
-	setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
+	setup_longmode $PM4LE
 
 	movd	%mm2, %rdi
 	shlq	$32, %rdi
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 32fddd6810..1cb422dbfc 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -363,7 +363,7 @@ fill_cache:
 	subl	$4, %esp
 
 #if ENV_X86_64
-	setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
+	setup_longmode $PM4LE
 
 	movd	%mm2, %rdi
 	shlq	$32, %rdi	/* BIST */
diff --git a/src/cpu/x86/64bit/Makefile.mk b/src/cpu/x86/64bit/Makefile.mk
index a8dc1a286a..b24e4d7de0 100644
--- a/src/cpu/x86/64bit/Makefile.mk
+++ b/src/cpu/x86/64bit/Makefile.mk
@@ -9,13 +9,15 @@ else
 PAGETABLE_SRC := pt.S
 endif
 
+all_x86-y += $(PAGETABLE_SRC)
+
 # Add --defsym=_start=0 to suppress a linker warning.
 $(objcbfs)/pt: $(dir)/$(PAGETABLE_SRC) $(obj)/config.h
 	$(CC_bootblock) $(CFLAGS_bootblock) $(CPPFLAGS_bootblock) -o $@.tmp $< -Wl,--section-start=.rodata=$(CONFIG_ARCH_X86_64_PGTBL_LOC),--defsym=_start=0
 	$(OBJCOPY_ramstage) -Obinary -j .rodata $@.tmp $@
 	rm $@.tmp
 
-cbfs-files-y += pagetables
+cbfs-files-$(CONFIG_PAGE_TABLES_IN_CBFS) += pagetables
 pagetables-file := $(objcbfs)/pt
 pagetables-type := raw
 pagetables-compression := none
diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc
index 878f310843..52da6037d5 100644
--- a/src/cpu/x86/64bit/entry64.inc
+++ b/src/cpu/x86/64bit/entry64.inc
@@ -11,9 +11,11 @@
 
 #if ENV_X86_64
 	.code32
+#if CONFIG(PAGE_TABLES_IN_CBFS)
 #if (CONFIG_ARCH_X86_64_PGTBL_LOC & 0xfff) > 0
 #error pagetables must be 4KiB aligned!
 #endif
+#endif
 
 #include <cpu/x86/msr.h>
 #if defined(__RAMSTAGE__)
diff --git a/src/cpu/x86/64bit/mode_switch.S b/src/cpu/x86/64bit/mode_switch.S
index 01fe003cb1..9555cefbbb 100644
--- a/src/cpu/x86/64bit/mode_switch.S
+++ b/src/cpu/x86/64bit/mode_switch.S
@@ -44,7 +44,7 @@ protected_mode_call_wrapper:
 	movl	%eax, %ebx
 
 	/* Preserves ebx */
-	setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
+	setup_longmode $PM4LE
 
 	/* Place return value in rax */
 	movl	%ebx, %eax
diff --git a/src/cpu/x86/64bit/mode_switch2.S b/src/cpu/x86/64bit/mode_switch2.S
index 1807d2e404..18c6425d7f 100644
--- a/src/cpu/x86/64bit/mode_switch2.S
+++ b/src/cpu/x86/64bit/mode_switch2.S
@@ -21,7 +21,7 @@ long_mode_call_3arg:
 	mov	%esp, %ebp
 
 	/* Enter long mode, preserves ebx */
-	setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
+	setup_longmode $PM4LE
 
 	/* Align stack */
 	movabs	$0xfffffffffffffff0, %rax
diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S
index b105528e5e..67e4b1b8bf 100644
--- a/src/cpu/x86/64bit/pt.S
+++ b/src/cpu/x86/64bit/pt.S
@@ -18,7 +18,7 @@
 #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A +  _D + (a))
 
 .global PM4LE
-.align 32
+.align 4096
 PM4LE:
 .quad _GEN_DIR(PDPE_table)
 
diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig
index cec6f97839..24dfa7a2fc 100644
--- a/src/mainboard/emulation/qemu-i440fx/Kconfig
+++ b/src/mainboard/emulation/qemu-i440fx/Kconfig
@@ -30,6 +30,11 @@ config VBOOT
 	select GBB_FLAG_DISABLE_FWMP
 
 if ARCH_BOOTBLOCK_X86_64
+
+config PAGE_TABLES_IN_CBFS
+	bool
+	default y
+
 # Need to install page tables in DRAM as the virtual MMU has problems translating paging
 # request when the page table resides in emulated ROM. This causes undefined behaviour
 # when handling data requests, as well as fetching and decoding instructions
diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig
index d68a5462bf..11ea750496 100644
--- a/src/mainboard/emulation/qemu-q35/Kconfig
+++ b/src/mainboard/emulation/qemu-q35/Kconfig
@@ -32,6 +32,11 @@ config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab-16M.fmd" if VBOOT_SLOTS_RW_AB
 
 if ARCH_BOOTBLOCK_X86_64
+
+config PAGE_TABLES_IN_CBFS
+	bool
+	default y
+
 # Need to install page tables in DRAM as the virtual MMU has problems translating paging
 # request when the page table resides in emulated ROM. This causes undefined behaviour
 # when handling data requests, as well as fetching and decoding instructions
diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S
index bb2203b805..0e0be524f2 100644
--- a/src/soc/amd/common/block/cpu/noncar/pre_c.S
+++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S
@@ -28,7 +28,7 @@ bootblock_pre_c_entry:
 	post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY)
 
 #if ENV_X86_64
-	setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
+	setup_longmode $PM4LE
 #endif
 
 	/* Clear .bss section */
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index c22e7d9a5e..ba98f1b75c 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -280,7 +280,7 @@ car_init_done:
 	andl	$0xfffffff0, %esp
 
 #if ENV_X86_64
-	setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
+	setup_longmode $PM4LE
 
 	movd	%mm2, %rdi
 	shlq	$32, %rdi