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authorLean Sheng Tan <sheng.tan@9elements.com>2022-09-12 15:26:43 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-12-02 14:47:36 +0000
commite98dd0aad81723c9c428e43fc396f0f413cc5a4c (patch)
tree10562de3548a7170c580a480187ddf2bfb98711e
parent998fdc06cbe5524653eb0ca295d319d9cfb065ce (diff)
mb/prodrive/atlas: Enable GPP_B14 buzzer support
Per Intel doc 621483, 26.1.1 - NMI_STS_CNT, 8254 timer is required for Speaker Data output (buzzer) at GPP_B14 NF1, as it is using 8254 timer counter 2 output. However when 8254 timer is used, S0ix will not work as 8254 has to be gated instead. For further info on s0ix requirements, refer to Intel doc 610002 (Modern Standby Unified Checklist). This CL also disables s0ix because it is not required by the platform. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ib5e7787a47509ed09818d8515d21a80196fb1ec6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67553 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/prodrive/atlas/Kconfig9
-rw-r--r--src/mainboard/prodrive/atlas/devicetree.cb3
2 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/prodrive/atlas/Kconfig b/src/mainboard/prodrive/atlas/Kconfig
index 814c1e057c..3900f4db15 100644
--- a/src/mainboard/prodrive/atlas/Kconfig
+++ b/src/mainboard/prodrive/atlas/Kconfig
@@ -54,6 +54,15 @@ config CBFS_SIZE
config NO_POST
default y
+config ENABLE_BUZZER_SUPPORT
+ bool "Enable Buzzer support"
+ default y
+ select USE_LEGACY_8254_TIMER
+ help
+ 8254 timer is required for buzzer support on GPP_B14 (based on Intel doc 621483,
+ 26.1.1 - NMI_STS_CNT). However since 8254 timer clock gating has to be enabled for
+ S0ix support, enabling buzzer will disable s0ix.
+
config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS
int
default 32
diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb
index 0d91bb63bc..c90c69c4f6 100644
--- a/src/mainboard/prodrive/atlas/devicetree.cb
+++ b/src/mainboard/prodrive/atlas/devicetree.cb
@@ -17,6 +17,9 @@ chip soc/intel/alderlake
# SaGv Configuration
register "sagv" = "CONFIG(ATLAS_ENABLE_SAGV) ? SaGv_Enabled : SaGv_Disabled"
+ # Disable S0ix
+ register "s0ix_enable" = "0"
+
# Display configuration (4 DPs)
register "ddi_ports_config" = "{
[DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,