diff options
| author | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2022-03-10 09:43:02 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-14 15:46:49 +0000 |
| commit | e6f71a5d283ad91f626721c7f311d3945dda4480 (patch) | |
| tree | ebda335357a94450f3fe0b2d1dd5649d367b649c | |
| parent | 232dcb938a08179291b1ff60b65e8244b4fc4827 (diff) | |
mb/google/nissa/var/nivviks: Hook up SD host controller GL9750
Select GL9750 driver and add power sequence according to datasheet:
GL9750S-OIY04 rev1.22.
BUG=b:223304292
TEST=check GL9750 can get enumerated by kernel 5.15.
01:00.0 SD Host controller: Genesys Logic, Inc Device 9750 (rev 01)
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib6d461a56f6aeba30994daafe8993c36df4b309d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
| -rw-r--r-- | src/mainboard/google/brya/Kconfig.name | 1 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/nivviks/gpio.c | 16 |
2 files changed, 17 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 186ca6f6d1..9bf50ae5bd 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -84,6 +84,7 @@ config BOARD_GOOGLE_NIVVIKS bool "-> Nivviks" select BOARD_GOOGLE_BASEBOARD_NISSA select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_INTEL_MIPI_CAMERA select HAVE_WWAN_POWER_SEQUENCE diff --git a/src/mainboard/google/brya/variants/nivviks/gpio.c b/src/mainboard/google/brya/variants/nivviks/gpio.c index f0700ab138..a5f9cb8d24 100644 --- a/src/mainboard/google/brya/variants/nivviks/gpio.c +++ b/src/mainboard/google/brya/variants/nivviks/gpio.c @@ -31,6 +31,8 @@ static const struct pad_config override_gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ @@ -45,6 +47,13 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 1, DEEP), }; const struct pad_config *variant_gpio_override_table(size_t *num) @@ -58,3 +67,10 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} |