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authorSubrata Banik <subratabanik@google.com>2024-07-18 23:40:11 +0530
committerSubrata Banik <subratabanik@google.com>2024-07-22 06:41:45 +0000
commite60989db3670d02a6d67bcaa76d00b00ef593f68 (patch)
tree408e8a0073562e56a4317bcbefbcbbda5a8f5d08
parent3b3a05259640b2c80c500193c5c93e7a1d432a91 (diff)
mb/google/brya/var/trulo: Add LSIO descriptions
This patch adds descriptions for Low Speed I/O (I2Cx, GSPIx, UARTx) to the device tree. It also includes entries that will generate ACPI code at runtime with LSIO end-point device. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I94a3a7f6f85d84407f32ab4c879b236a80859f2d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83550 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/brya/variants/trulo/overridetree.cb98
1 files changed, 98 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb
index 03f7f9e552..febc1ded58 100644
--- a/src/mainboard/google/brya/variants/trulo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb
@@ -24,6 +24,67 @@ chip soc/intel/alderlake
# Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
register "tcss_aux_ori" = "0"
+ register "serial_io_i2c_mode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ }"
+
+ register "serial_io_gspi_mode" = "{
+ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+ [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+ }"
+
+ register "serial_io_uart_mode" = "{
+ [PchSerialIoIndexUART0] = PchSerialIoPci,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoDisabled,
+ }"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| I2C0 | TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| I2C1 | Trackpad |
+ #| I2C5 | Touchscreen |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .i2c[0] = {
+ .early_init = 1,
+ .speed = I2C_SPEED_FAST_PLUS,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST_PLUS,
+ .scl_lcnt = 55,
+ .scl_hcnt = 30,
+ .sda_hold = 7,
+ }
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 158,
+ .scl_hcnt = 79,
+ .sda_hold = 7,
+ }
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 158,
+ .scl_hcnt = 79,
+ .sda_hold = 7,
+ }
+ },
+ }"
+
device domain 0 on
device ref igpu on end
device ref tcss_xhci on
@@ -93,6 +154,42 @@ chip soc/intel/alderlake
end
end
device ref shared_sram on end
+ device ref i2c0 on
+ chip drivers/i2c/tpm
+ register "hid" = ""GOOG0005""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A17_IRQ)"
+ device i2c 50 on end
+ end
+ end #I2C0
+ device ref i2c1 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)"
+ register "wake" = "GPE0_DW1_03"
+ register "detect" = "1"
+ device i2c 15 on end
+ end
+ end #I2C1
+ device ref i2c5 on
+ chip drivers/i2c/hid
+ register "generic.hid" = ""ELAN9004""
+ register "generic.desc" = ""ELAN Touchscreen""
+ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)"
+ register "generic.detect" = "1"
+ register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
+ register "generic.reset_delay_ms" = "20"
+ register "generic.reset_off_delay_ms" = "2"
+ register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)"
+ register "generic.enable_delay_ms" = "1"
+ register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
+ register "generic.stop_delay_ms" = "150"
+ register "generic.stop_off_delay_ms" = "2"
+ register "generic.has_power_resource" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 10 on end
+ end
+ end #I2C5
device ref heci1 on end
device ref emmc on end
device ref ish on
@@ -102,6 +199,7 @@ chip soc/intel/alderlake
end
end
device ref ufs on end
+ device ref uart0 on end
device ref pch_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]