diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-14 13:22:01 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-09-17 19:58:00 +0000 |
| commit | e5ec50c2363602ccb72a988365063987b9ea3e09 (patch) | |
| tree | ff7c12cfe6abe6cc3059c5f1b28c2b8e64078005 | |
| parent | a3cb3220185cf47a59a1b8b74d3a4fcdef5e57b6 (diff) | |
nb/intel/haswell: Guard DMIBAR/EPBAR macro parameters
Add brackets around the parameters to avoid operation order problems.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I5e1a02ba2ebf468f0d80b7f1838766280b6b7b22
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45352
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/northbridge/intel/haswell/haswell.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 00cc885c9c..f3f525d770 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -57,9 +57,9 @@ * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) -#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) -#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + (x))) +#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x))) +#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x))) #define EPPVCCAP1 0x004 /* 32bit */ #define EPPVCCAP2 0x008 /* 32bit */ @@ -88,9 +88,9 @@ * DMIBAR */ -#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) -#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) -#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + (x))) +#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x))) +#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x))) #define DMIVCECH 0x000 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */ |