diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2022-02-14 13:04:34 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-24 01:18:03 +0000 |
| commit | e2531ffaa87be5c26005ff986db8492a03f809e3 (patch) | |
| tree | 843fb04a1551f4b5173aefbd9ad31e93eeead96c | |
| parent | fdb0294846cf18b1077e8b0a4b2fe29d6b5a0bb4 (diff) | |
nb/intel/ironlake: Move out HECI remainders into southbridge
Move the remaining HECI-related stuff to southbridge scope, as the HECI
hardware is in the southbridge. Note that HECI BAR is now enabled a bit
earlier than before, but this shouldn't matter.
Change-Id: I4a29d0b5d5c5e22508bcdfe34a1c5459ae967c75
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
| -rw-r--r-- | src/northbridge/intel/ironlake/early_init.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/ironlake/ironlake.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/early_pch.c | 5 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/pch.h | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/setup_heci_uma.c | 1 |
5 files changed, 7 insertions, 6 deletions
diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index 1e4d0dcc10..b765417274 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -106,10 +106,6 @@ void ironlake_early_initialization(int chipset_type) early_cpu_init(); - pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR); - pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - /* Magic for S3 resume. Must be done early. */ if (s3_resume) { mchbar_clrsetbits32(0x1e8, 1, 6); diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 9a8b21e003..be5f11ba14 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -3,8 +3,6 @@ #ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ #define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ -#define DEFAULT_HECIBAR ((u8 *)0xfed17000) - /* * D1:F0 PEG */ diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index 2fa4b52d23..9edbcf6aa7 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -2,6 +2,7 @@ #include <arch/io.h> #include <console/console.h> +#include <device/pci_def.h> #include <device/pci_ops.h> #include <device/smbus_host.h> #include <northbridge/intel/ironlake/ironlake.h> @@ -46,6 +47,10 @@ void ibexpeak_setup_bars(void) /* halt timer */ outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06); printk(BIOS_DEBUG, " done.\n"); + + pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR); + pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } void early_pch_init(void) diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 6565cd11f0..83e86c266c 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -22,6 +22,7 @@ /* TODO Make sure these don't get changed by stage2 */ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 +#define DEFAULT_HECIBAR ((u8 *)0xfed17000) #include <southbridge/intel/common/rcba.h> diff --git a/src/southbridge/intel/ibexpeak/setup_heci_uma.c b/src/southbridge/intel/ibexpeak/setup_heci_uma.c index 70219e1adb..3f8b6617c4 100644 --- a/src/southbridge/intel/ibexpeak/setup_heci_uma.c +++ b/src/southbridge/intel/ibexpeak/setup_heci_uma.c @@ -6,6 +6,7 @@ #include <device/pci_ops.h> #include <northbridge/intel/ironlake/ironlake.h> #include <southbridge/intel/ibexpeak/me.h> +#include <southbridge/intel/ibexpeak/pch.h> #include <types.h> #define HECIDEV PCI_DEV(0, 0x16, 0) |