diff options
author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-06-21 15:04:51 +0300 |
---|---|---|
committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-01-04 21:23:21 +0000 |
commit | de7f0736a16edb8d34df6e057b87a0bc1fbf7874 (patch) | |
tree | 9a412a0102208af69739300b58fbb5c85d46439a | |
parent | 1de326460eb240ba9780d8e1a2a2dc73d0f9f347 (diff) |
mb/*/chromeos.c: Fix PRE_RAM and unify style
Change-Id: I99b9c0452ed0e6d580edb5a4f3317d776085b382
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30399
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r-- | src/mainboard/google/beltino/chromeos.c | 25 | ||||
-rw-r--r-- | src/mainboard/google/butterfly/chromeos.c | 2 | ||||
-rw-r--r-- | src/mainboard/google/jecht/chromeos.c | 25 | ||||
-rw-r--r-- | src/mainboard/google/parrot/chromeos.c | 2 | ||||
-rw-r--r-- | src/mainboard/google/stout/chromeos.c | 2 | ||||
-rw-r--r-- | src/mainboard/intel/baskingridge/chromeos.c | 2 | ||||
-rw-r--r-- | src/mainboard/intel/emeraldlake2/chromeos.c | 2 | ||||
-rw-r--r-- | src/mainboard/samsung/lumpy/chromeos.c | 29 | ||||
-rw-r--r-- | src/mainboard/samsung/stumpy/chromeos.c | 29 |
9 files changed, 55 insertions, 63 deletions
diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index ad4eab98b1..0be19fa7b9 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -48,32 +48,32 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { -#ifdef __PRE_RAM__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 2); +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); + struct device *dev = pcidev_on_root(0x1f, 2); #endif return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } int get_recovery_mode_switch(void) { -#ifdef __PRE_RAM__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 2); +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); + struct device *dev = pcidev_on_root(0x1f, 2); #endif return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; } -#ifdef __PRE_RAM__ void init_bootmode_straps(void) { u32 flags = 0; +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); +#else + struct device *dev = pcidev_on_root(0x1f, 2); +#endif /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) @@ -85,9 +85,8 @@ void init_bootmode_straps(void) /* Developer: Virtual */ - pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); + pci_write_config32(dev, SATA_SP, flags); } -#endif static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 7a74ed5e47..da137b0080 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -37,7 +37,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe; int lidswitch = 0; diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index c2e5a2be0a..d7e48a0d40 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -50,32 +50,32 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { -#ifdef __PRE_RAM__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 2); +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); + struct device *dev = pcidev_on_root(0x1f, 2); #endif return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } int get_recovery_mode_switch(void) { -#ifdef __PRE_RAM__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 2); +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); + struct device *dev = pcidev_on_root(0x1f, 2); #endif return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; } -#ifdef __PRE_RAM__ void init_bootmode_straps(void) { u32 flags = 0; +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); +#else + struct device *dev = pcidev_on_root(0x1f, 2); +#endif /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) @@ -87,9 +87,8 @@ void init_bootmode_straps(void) /* Developer: Virtual */ - pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); + pci_write_config32(dev, SATA_SP, flags); } -#endif static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index b82efbaea9..bc605aaad4 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -34,7 +34,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 6d77a2aead..5301d30b67 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -101,7 +101,7 @@ int get_recovery_mode_switch(void) #else static int ec_in_rec_mode = 0; static int ec_rec_flag_good = 0; - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); #endif u8 ec_status = ec_read(EC_STATUS_REG); diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 2f8e27b187..0e58959081 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -29,7 +29,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; if (!gpio_base) diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index dc49725f91..8967a21d32 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -29,7 +29,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; if (!gpio_base) diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 0f672b6e5f..bc660b6bdc 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -40,7 +40,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); u8 lid = ec_read(0x83); @@ -88,11 +88,9 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { #ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 2); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); + struct device *dev = pcidev_on_root(0x1f, 2); #endif return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } @@ -100,11 +98,9 @@ int get_write_protect_state(void) int get_developer_mode_switch(void) { #ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 2); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); + struct device *dev = pcidev_on_root(0x1f, 2); #endif return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1; } @@ -112,19 +108,21 @@ int get_developer_mode_switch(void) int get_recovery_mode_switch(void) { #ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 2); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); + struct device *dev = pcidev_on_root(0x1f, 2); #endif return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; } void init_bootmode_straps(void) { -#ifdef __PRE_RAM__ u32 flags = 0; +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); +#else + struct device *dev = pcidev_on_root(0x1f, 2); +#endif /* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ if (get_gpio(GPIO_SPI_WP)) @@ -136,8 +134,7 @@ void init_bootmode_straps(void) if (get_gpio(GPIO_DEV_MODE)) flags |= (1 << FLAG_DEV_MODE); - pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); -#endif + pci_write_config32(dev, SATA_SP, flags); } static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 9c3499599c..f543da2256 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -37,7 +37,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); @@ -85,11 +85,9 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { #ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 2); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); + struct device *dev = pcidev_on_root(0x1f, 2); #endif return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } @@ -97,11 +95,9 @@ int get_write_protect_state(void) int get_developer_mode_switch(void) { #ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 2); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); + struct device *dev = pcidev_on_root(0x1f, 2); #endif return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1; } @@ -109,19 +105,21 @@ int get_developer_mode_switch(void) int get_recovery_mode_switch(void) { #ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 2); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); + struct device *dev = pcidev_on_root(0x1f, 2); #endif return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; } void init_bootmode_straps(void) { -#ifdef __PRE_RAM__ u32 flags = 0; +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); +#else + struct device *dev = pcidev_on_root(0x1f, 2); +#endif /* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) @@ -133,8 +131,7 @@ void init_bootmode_straps(void) if (get_gpio(GPIO_DEV_MODE)) flags |= (1 << FLAG_DEV_MODE); - pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); -#endif + pci_write_config32(dev, SATA_SP, flags); } static const struct cros_gpio cros_gpios[] = { |