diff options
| author | Nick Vaccaro <nvaccaro@google.com> | 2018-06-18 21:56:25 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-21 09:41:29 +0000 |
| commit | de31587a3a4834c18eab49aa7fd979a01f1fd3d1 (patch) | |
| tree | e57eec7a539b727771f4b7e3a18b63f2ec859aee | |
| parent | 97bdb9aa31ada2b4fbf0aa5e0e3744294427f927 (diff) | |
mb/google/poppy/variants/nocturne: disable p-states
Set register speed_shift_enable=0 in devicetree to disable
p-states in coreboot as a temporary workaround for an SoC hang.
BUG=b:79666828
BRANCH=none
TEST="emerge-nocturne depthcharge coreboot chromeos-bootimage",
flash spi image onto nocturne, boot to kernel and verify device
stays alive and responsive for several minutes without locking up.
Change-Id: I71ed4c80c109b28ffa85d48338ce3a62396d272e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index f746c080bf..0b30caae39 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -60,7 +60,8 @@ chip soc/intel/skylake register "PmTimerDisabled" = "1" register "VmxEnable" = "1" - register "speed_shift_enable" = "1" + # Disable P-States + register "speed_shift_enable" = "0" register "dptf_enable" = "1" register "tdp_pl2_override" = "15" register "psys_pmax" = "45" |