diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-07-30 15:40:10 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-08-03 18:54:11 +0000 |
| commit | dcf99b044571312bddfdd3491ce14612db073854 (patch) | |
| tree | cd768af01c02e17fe9ca3a13fb7e668fbdb9e5c0 | |
| parent | ea5336d24098e837c3a9c1dd9452f7edec8f60a9 (diff) | |
soc/intel/cannonlake: Sort Kconfig for Cannonlake
Look and feel update, sort the sequence in Kconfig.
Change-Id: I41d99979d9c7d081086aac8bfef27186b37a6e70
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 1c0f1bffbe..471fe6ca78 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -8,37 +8,37 @@ if SOC_INTEL_CANNONLAKE config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 - select SOC_INTEL_COMMON_BLOCK_TIMER - select HAVE_MONOTONIC_TIMER - select TSC_CONSTANT_RATE - select TSC_MONOTONIC_TIMER - select UDELAY_TSC - select REG_SCRIPT + select ARCH_VERSTAGE_X86_32 select C_ENVIRONMENT_BOOTBLOCK select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select HAVE_HARD_RESET select HAVE_INTEL_FIRMWARE + select HAVE_MONOTONIC_TIMER select INTEL_CAR_NEM_ENHANCED select PLATFORM_USES_FSP2_0 + select REG_SCRIPT select RELOCATABLE_RAMSTAGE select SOC_INTEL_COMMON - select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CPU - select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_BLOCK_LPSS - select SOC_INTEL_COMMON_BLOCK_UART + select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_FAST_SPI + select SOC_INTEL_COMMON_BLOCK_GPIO + select SOC_INTEL_COMMON_BLOCK_LPSS select SOC_INTEL_COMMON_BLOCK_PCR - select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_RTC - select SOC_INTEL_COMMON_BLOCK_CSE - select SOC_INTEL_COMMON_BLOCK_GPIO + select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SMBUS + select SOC_INTEL_COMMON_BLOCK_TIMER + select SOC_INTEL_COMMON_BLOCK_UART + select SOC_INTEL_COMMON_RESET select SUPPORT_CPU_UCODE_IN_CBFS + select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER + select UDELAY_TSC config UART_DEBUG bool "Enable UART debug port." |