diff options
| author | Weiyi Lu <weiyi.lu@mediatek.com> | 2020-10-15 14:25:01 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-16 06:29:24 +0000 |
| commit | dac4fa6ded89e104ace5283b519be2a70ff60e0b (patch) | |
| tree | 292fe1d9f4c77974103b97a01d1af1f3d9fb344d | |
| parent | 752fc6026f786818681a02c4144268a3a1a03391 (diff) | |
soc/mediatek/mt8192: Keep CONN MCU in reset state
Keep the CONN MCU in reset state to prevent CONN from asserting the
clk26m request to SPM.
TEST=clk26m request from conn has been released.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ia1b706da497ba2827341051459c3628e2ae9240f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/pll.h | 3 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/pll.c | 6 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 170196b035..52bf3c2f38 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -306,6 +306,9 @@ DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24) DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) +DEFINE_BITFIELD(WDT_SWSYSRST_KEY, 31, 24) +DEFINE_BITFIELD(WDT_SWSYSRST_CONN_MCU, 12, 12) + enum { INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = (0x1f << 12) | (0x1 << 17) | (0x1 << 18), INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON = (0x10 << 12) | (0x1 << 17) | (0x0 << 18), diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index afa7c85e02..6d61fb4d5a 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -10,6 +10,7 @@ #include <soc/infracfg.h> #include <soc/mcucfg.h> #include <soc/pll.h> +#include <soc/wdt.h> enum mux_id { TOP_AXI_SEL, @@ -467,6 +468,11 @@ void mt_pll_init(void) /* enable [14] dramc_pll104m_ck */ setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); + + /* reset CONNSYS MCU */ + SET32_BITFIELDS(&mtk_wdt->wdt_swsysrst, + WDT_SWSYSRST_KEY, 0x88, + WDT_SWSYSRST_CONN_MCU, 0x1); } void mt_pll_raise_little_cpu_freq(u32 freq) |