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authorKevin Chiu <kevin.chiu.17802@gmail.com>2021-02-04 19:56:41 +0800
committerMartin Roth <martinroth@google.com>2021-02-09 22:16:18 +0000
commitda996f893d56a4a46ca1ba97bc9b46c00de1a5dc (patch)
tree96142f75dc429c644a8480e8e6ea6407c79e3b9b
parent9a6fc577d1b6a877b30c623433fffee57c69c5da (diff)
mb/google/zork: update USB 3 controller phy Parameter for dirinboz
Recommendation from SOC to config IQ=8 for U3 port0, vboost for all U3 ports for passing ESD pin test. BUG=b:175192931 BRANCH=zork TEST=1. emerge-zork coreboot 2. run U3 SI/ESD pin test => pass Change-Id: I42a94e03fb6f8230d4356d16b8e0d2164bc61e3f Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
-rw-r--r--src/mainboard/google/zork/variants/dirinboz/overridetree.cb21
1 files changed, 21 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb
index fc9c5fdfb0..1bfea1d1c4 100644
--- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb
@@ -60,6 +60,27 @@ chip soc/amd/picasso
.tx_res_tune = 0x01,
}"
+ # USB3 phy parameter
+ register "usb3_phy_override" = "1"
+
+ # USB3 Port0 Default
+ register "usb3_phy_tune_params[0]" = "{
+ .rx_eq_delta_iq_ovrd_val = 0x8,
+ .rx_eq_delta_iq_ovrd_en = 0x1,
+ }"
+
+ # SUP_DIG_LVL_OVRD_IN Default
+ register "usb3_rx_vref_ctrl" = "0x10"
+ register "usb3_rx_vref_ctrl_en" = "0x00"
+ register "usb_3_tx_vboost_lvl" = "0x07"
+ register "usb_3_tx_vboost_lvl_en" = "0x01"
+
+ # SUPX_DIG_LVL_OVRD_IN Default
+ register "usb_3_rx_vref_ctrl_x" = "0x10"
+ register "usb_3_rx_vref_ctrl_en_x" = "0x00"
+ register "usb_3_tx_vboost_lvl_x" = "0x07"
+ register "usb_3_tx_vboost_lvl_en_x" = "0x01"
+
# I2C2 for touchscreen and trackpad
register "i2c[2]" = "{
.speed = I2C_SPEED_FAST,