mb/intel/dq67sw: Add LGA1155 microATX mainboard

This is a new port for the Intel DQ67SW desktop board. It is
microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3
SDRAM.

A list of tested working and non-working features is in the
documentation page.

Change-Id: Ifc703f2d0ad45495e71d3f7799347430f5196791
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

19 files changed, 759 insertions, 0 deletions

diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index eac31ccb12..272c6e0b47 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -86,6 +86,7 @@ The boards in this section are not real mainboards, but emulators.
 ## Intel
 
 - [DG43GT](intel/dg43gt.md)
+- [DQ67SW](intel/dq67sw.md)
 - [KBLRVP11](intel/kblrvp11.md)
 
 ## Kontron
diff --git a/Documentation/mainboard/intel/dq67sw.md b/Documentation/mainboard/intel/dq67sw.md
new file mode 100644
index 0000000000..b3ed9b8d0d
--- /dev/null
+++ b/Documentation/mainboard/intel/dq67sw.md
@@ -0,0 +1,170 @@
+# Intel DQ67SW
+
+The Intel DQ67SW is a microATX-sized desktop board for Intel Sandy Bridge CPUs.
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge      | Intel Q67 (bd82x6x)                              |
++------------------+--------------------------------------------------+
+| CPU socket       | LGA 1155                                         |
++------------------+--------------------------------------------------+
+| RAM              | 4 x DDR3-1333                                    |
++------------------+--------------------------------------------------+
+| Super I/O        | Nuvoton/Winbond W83677HG-i                       |
++------------------+--------------------------------------------------+
+| Audio            | Realtek ALC888S                                  |
++------------------+--------------------------------------------------+
+| Network          | Intel 82579LM Gigabit Ethernet                   |
++------------------+--------------------------------------------------+
+| Serial           | Internal header                                  |
++------------------+--------------------------------------------------+
+```
+
+## Status
+
+### Working
+
+- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
+- Native RAM initialization with four DIMMs
+- Integrated GPU with libgfxinit
+- PCIe graphics in the PEG slot
+- Additional PCIe slots
+- PCI slot
+- All rear (4x) and internal (8x) USB2 ports
+- Rear USB3 ports (2x)
+- All four internal SATA ports (two 6 Gb/s, two 3 Gb/s)
+- Two rear eSATA connectors (3 Gb/s)
+- SATA at 6 Gb/s
+- Gigabit Ethernet
+- SeaBIOS 1.16.1 + libgfxinit (legacy VGA) to boot slackware64 (Linux 5.15)
+- SeaBIOS 1.16.1 + extracted VGA BIOS to boot Windows 10 (21H2)
+- edk2 UefiPayload (uefipayload_202207) + libgfxinit (high-res) to boot:
+    - slackware64 (Linux 5.15)
+    - Windows 10 (22H2)
+- External in-circuit flashing with flashrom-1.2 and a Raspberry Pi 1
+- Poweroff
+- Resume from S3
+- Console output on the serial port
+
+### Not working
+
+- Automatic fan control. One can still use OS-based fan control programs,
+  such as fancontrol on Linux or SpeedFan on Windows.
+- Windows 10 booted from SeaBIOS + libgfxinit (high-res). The installation
+  works, but once Windows Update installs drivers, it crashes and enters a
+  bootloop.
+
+### Untested
+
+- Firewire (LSI L-FW3227-100)
+- EHCI debug
+- S/PDIF audio
+- Audio jacks other than the green one
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Model               | W25Q64.V   |
++---------------------+------------+
+| Size                | 8 MiB      |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Write protection    | yes        |
++---------------------+------------+
+| Dual BIOS feature   | no         |
++---------------------+------------+
+| Internal flashing   | see below  |
++---------------------+------------+
+| In circuit flashing | see below  |
++---------------------+------------+
+```
+
+The flash is divided into the following regions, as obtained with
+`ifdtool -f rom.layout backup.rom`:
+
+    00000000:00000fff fd
+    00580000:007fffff bios
+    00003000:0057ffff me
+    00001000:00002fff gbe
+
+Unfortunately the SPI interface to the chip is locked down by the vendor
+firmware. The BIOS Lock Enable (BLE) bit of the `BIOS_CNTL` register, part of
+the PCI configuration space of the LPC Interface Bridge, is set.
+
+It is possible to program the chip is to attach an external programmer
+with an SOIC-8 clip.
+
+```eval_rst
+Another way is to boot the vendor firmware in UEFI mode and exploit the
+unpatched S3 Boot Script vulnerability. See this page for a similar procedure:
+:doc:`../lenovo/ivb_internal_flashing`.
+```
+
+On this specific board it is possible to prevent the BLE bit from being set
+when it resumes from S3. One entry in the S3 Boot Script must be modified,
+e.g. with a patched version of [CHIPSEC](https://github.com/chipsec/chipsec)
+that supports this specific type of S3 Boot Script, for example from strobo5:
+
+    $ git clone -b headerless https://github.com/strobo5/chipsec.git
+    $ cd chipsec
+    $ python setup.py build_ext -i
+    $ sudo python chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,mmio_wr,0xe00f80dc,0x00,1
+
+The boot script contains an entry that writes 0x02 to memory at address
+0xe00f80dc. This address points at the PCIe configuration register at offset
+0xdc for the PCIe device 0:1f.0, which is the BIOS Control Register of the LPC
+Interface Bridge [0][1]. The value 0x02 sets the BLE bit, and the modification
+prevents this by making it write a 0 instead.
+
+```eval_rst
+After suspending and resuming the board, the BIOS region can be flashed with
+a coreboot image, e.g. using flashrom. Note that the ME region is not readable,
+so the `--noverify-all` flag is necessary. Please refer to the
+:doc:`../../tutorial/flashing_firmware/index`.
+```
+
+## Hardware monitoring and fan control
+
+Currently there is no automatic, OS-independent fan control.
+
+## Serial port header
+
+Serial port 1, provided by the Super I/O, is exposed on a pin header. The
+RS-232 signals are assigned to the header so that its pin numbers map directly
+to the pin numbers of a DE-9 connector. If your serial port doesn't seem to
+work, check if your bracket expects a different assignment.
+
+Here is a top view of the serial port header found on this board:
+
+                 +---+---+
+             N/C |   | 9 | RI  -> pin 9
+                 +---+---+
+    Pin 8 <- CTS | 8 | 7 | RTS -> pin 7
+                 +---+---+
+    Pin 6 <- DSR | 6 | 5 | GND -> pin 5
+                 +---+---+
+    Pin 4 <- DTR | 4 | 3 | TxD -> pin 3
+                 +---+---+
+    Pin 2 <- RxD | 2 | 1 | DCD -> pin 1
+                 +---+---+
+
+## References
+
+[0]: Intel 6 Series Chipset and Intel C200 Series Chipset Datasheet,
+May 2011,
+Document number 324645-006
+
+[1]: Accessing PCI Express Configuration Registers Using Intel Chipsets,
+December 2008,
+Document number 321090
+
diff --git a/src/mainboard/intel/dq67sw/Kconfig b/src/mainboard/intel/dq67sw/Kconfig
new file mode 100644
index 0000000000..676f041c14
--- /dev/null
+++ b/src/mainboard/intel/dq67sw/Kconfig
@@ -0,0 +1,27 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_INTEL_DQ67SW
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select GFX_GMA_ANALOG_I2C_HDMI_B
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select MAINBOARD_HAS_LIBGFXINIT
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_BD82X6X
+	select SUPERIO_WINBOND_W83667HG_A
+	select USE_NATIVE_RAMINIT
+
+config MAINBOARD_DIR
+	default "intel/dq67sw"
+
+config MAINBOARD_PART_NUMBER
+	default "DQ67SW"
+
+endif
diff --git a/src/mainboard/intel/dq67sw/Kconfig.name b/src/mainboard/intel/dq67sw/Kconfig.name
new file mode 100644
index 0000000000..a4e8e102ea
--- /dev/null
+++ b/src/mainboard/intel/dq67sw/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_INTEL_DQ67SW
+	bool "DQ67SW"
diff --git a/src/mainboard/intel/dq67sw/Makefile.inc b/src/mainboard/intel/dq67sw/Makefile.inc
new file mode 100644
index 0000000000..18391d8b18
--- /dev/null
+++ b/src/mainboard/intel/dq67sw/Makefile.inc
@@ -0,0 +1,5 @@
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/intel/dq67sw/acpi/ec.asl b/src/mainboard/intel/dq67sw/acpi/ec.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/intel/dq67sw/acpi/ec.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/intel/dq67sw/acpi/pci.asl b/src/mainboard/intel/dq67sw/acpi/pci.asl
new file mode 100644
index 0000000000..d5b264976b
--- /dev/null
+++ b/src/mainboard/intel/dq67sw/acpi/pci.asl
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Intel PCI to PCI bridge 0:1e.0 */
+
+Device (PCIB)
+{
+	Name (_ADR, 0x001E0000)
+
+	/* From vendor FW: Power Resources for Wake */
+	Name (_PRW, Package(){ 11, 4 })
+
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				/* PCI slot */
+				Package() { 0x0000ffff, 0, 0, 0x10 },
+				Package() { 0x0000ffff, 1, 0, 0x11 },
+				Package() { 0x0000ffff, 2, 0, 0x12 },
+				Package() { 0x0000ffff, 3, 0, 0x13 },
+
+				/* on-board IEEE1394 controller */
+				Package() { 0x0003ffff, 0, 0, 0x14 },
+			})
+		}
+		Return (Package() {
+			/* PCI slot */
+			Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+
+			/* on-board IEEE1394 controller */
+			Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+		})
+	}
+}
diff --git a/src/mainboard/intel/dq67sw/acpi/platform.asl b/src/mainboard/intel/dq67sw/acpi/platform.asl
new file mode 100644
index 0000000000..aff432b6f4
--- /dev/null
+++ b/src/mainboard/intel/dq67sw/acpi/platform.asl
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+	Return(Package() {0, 0})
+}
+
+Method(_PTS, 1)
+{
+}
diff --git a/src/mainboard/intel/dq67sw/acpi/superio.asl b/src/mainboard/intel/dq67sw/acpi/superio.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/intel/dq67sw/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/intel/dq67sw/board_info.txt b/src/mainboard/intel/dq67sw/board_info.txt
new file mode 100644
index 0000000000..eaca957ae0
--- /dev/null
+++ b/src/mainboard/intel/dq67sw/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://ark.intel.com/content/www/us/en/ark/products/51997/intel-desktop-board-dq67sw.html
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
+Release year: 2011
diff --git a/src/mainboard/intel/dq67sw/cmos.default b/src/mainboard/intel/dq67sw/cmos.default
new file mode 100644
index 0000000000..c7aa6208f4
--- /dev/null
+++ b/src/mainboard/intel/dq67sw/cmos.default
@@ -0,0 +1,6 @@
+boot_option=Fallback
+debug_level=Debug
+nmi=Disable
+power_on_after_fail=Disable
+sata_mode=AHCI
+gfx_uma_size=64M
diff --git a/src/mainboard/intel/dq67sw/cmos.layout b/src/mainboard/intel/dq67sw/cmos.layout
new file mode 100644
index 0000000000..d3676ae250
--- /dev/null
+++ b/src/mainboard/intel/dq67sw/cmos.layout
@@ -0,0 +1,88 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	2	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	3	debug_level
+
+# coreboot config options: southbridge
+408	1	e	1	nmi
+
+409	2	e	4	power_on_after_fail
+411	2	e	5	sata_mode
+
+# coreboot config options: northbridge
+416	5	e	6	gfx_uma_size
+
+# coreboot config options: mainboard-specific
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+#ID	value	text
+
+# Generic on/off enum
+1	0	Disable
+1	1	Enable
+
+# boot_option
+2	0	Fallback
+2	1	Normal
+
+# debug_level
+3	0	Emergency
+3	1	Alert
+3	2	Critical
+3	3	Error
+3	4	Warning
+3	5	Notice
+3	6	Info
+3	7	Debug
+3	8	Spew
+
+# power_on_after_fail
+4	0	Disable
+4	1	Enable
+4	2	Keep
+
+# sata_mode
+5	0	AHCI
+5	1	Compatible
+5	2	Legacy
+
+# gfx_uma_size (Intel IGP Video RAM size)
+6	0	32M
+6	1	64M
+6	2	96M
+6	3	128M
+6	4	160M
+6	5	192M
+6	6	224M
+6	7	256M
+6	8	288M
+6	9	320M
+6	10	352M
+6	11	384M
+6	12	416M
+6	13	448M
+6	14	480M
+6	15	512M
+6	16	1024M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 423 984
diff --git a/src/mainboard/intel/dq67sw/data.vbt b/src/mainboard/intel/dq67sw/data.vbt
new file mode 100644
index 0000000000..c529ae28b6
--- /dev/null
+++ b/src/mainboard/intel/dq67sw/data.vbt
diff --git a/src/mainboard/intel/dq67sw/devicetree.cb b/src/mainboard/intel/dq67sw/devicetree.cb
new file mode 100644
index 0000000000..544a525b97
--- /dev/null
+++ b/src/mainboard/intel/dq67sw/devicetree.cb
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		subsystemid 0x8086 0x2008 inherit
+		device ref host_bridge on end	# Host bridge
+		device ref peg10 on end		# PEG
+		device ref igd on end		# iGPU
+
+		chip southbridge/intel/bd82x6x	# Intel Series 6 Cougar Point PCH
+			register "gen1_dec" = "0x000c0291"
+			register "sata_interface_speed_support" = "0x3"
+			register "sata_port_map" = "0x3f"
+			register "spi_lvscc" = "0x2005"
+			register "spi_uvscc" = "0x2005"
+			device ref mei1 on end		# Management Engine Interface 1
+			device ref me_ide_r on end	# Management Engine IDE-R
+			device ref me_kt on end		# Management Engine KT
+			device ref gbe on end		# Intel Gigabit Ethernet
+			device ref ehci2 on end		# USB2 EHCI #2
+			device ref hda on end		# High Definition Audio
+			device ref pcie_rp1 on end	# PCIe Port #1
+			device ref pcie_rp5 on end	# PCIe Port #5
+			device ref pcie_rp7 on end	# PCIe Port #7
+			device ref ehci1 on end		# USB2 EHCI #1
+			device ref pci_bridge on end	# PCI bridge
+			device ref lpc on		# LPC bridge
+				chip superio/winbond/w83667hg-a	# Super I/O
+					device pnp 2e.0 off end		# FDC
+					device pnp 2e.1 off end		# LPT1
+					device pnp 2e.2 on		# COM1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 off end		# COM2
+					device pnp 2e.5 on		# PS/2 keyboard & mouse
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 2e.106 off end	# SPI1 (CIR?)
+					device pnp 2e.107 off end	# GPIO6
+					device pnp 2e.207 off end	# GPIO7
+					device pnp 2e.307 off end	# GPIO8
+					device pnp 2e.407 off end	# GPIO9
+					device pnp 2e.8 off end		# WDT
+					device pnp 2e.108 off end	# GPIO1
+					device pnp 2e.9 off end		# GPIO2
+					device pnp 2e.109 off end	# GPIO3
+					device pnp 2e.209 off end	# GPIO4
+					device pnp 2e.309 off end	# GPIO5
+					device pnp 2e.a on end		# ACPI
+					device pnp 2e.b on		# HW Monitor
+						io 0x60 = 0x290
+						irq 0x70 = 0
+					end
+					device pnp 2e.c on end		# PECI
+					device pnp 2e.d off end		# VID_BUSSEL
+					device pnp 2e.f on end		# GPIO_PP_OD
+				end
+			end
+			device ref sata1 on end		# SATA (AHCI)
+			device ref smbus on end		# SMBus
+		end
+	end
+end
diff --git a/src/mainboard/intel/dq67sw/dsdt.asl b/src/mainboard/intel/dq67sw/dsdt.asl
new file mode 100644
index 0000000000..0dcdf19681
--- /dev/null
+++ b/src/mainboard/intel/dq67sw/dsdt.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+		#include "acpi/pci.asl"
+	}
+}
diff --git a/src/mainboard/intel/dq67sw/early_init.c b/src/mainboard/intel/dq67sw/early_init.c
new file mode 100644
index 0000000000..683dbf8f66
--- /dev/null
+++ b/src/mainboard/intel/dq67sw/early_init.c
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/winbond/w83667hg-a/w83667hg-a.h>
+#include <superio/winbond/common/winbond.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 1, 0 },
+	{ 1, 1, 0 },
+	{ 1, 1, 1 },
+	{ 1, 1, 1 },
+	{ 1, 0, 2 },
+	{ 1, 0, 2 },
+	{ 1, 0, 3 },
+	{ 1, 0, 3 },
+	{ 1, 1, 4 },
+	{ 1, 1, 4 },
+	{ 0, 0, 5 },
+	{ 0, 0, 5 },
+	{ 1, 0, 6 },
+	{ 1, 0, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[1], 0x51, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+	read_spd(&spd[3], 0x53, id_only);
+}
diff --git a/src/mainboard/intel/dq67sw/gma-mainboard.ads b/src/mainboard/intel/dq67sw/gma-mainboard.ads
new file mode 100644
index 0000000000..a42948890d
--- /dev/null
+++ b/src/mainboard/intel/dq67sw/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP2,
+      HDMI1,
+      HDMI2,
+      HDMI3,
+      Analog,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/intel/dq67sw/gpio.c b/src/mainboard/intel/dq67sw/gpio.c
new file mode 100644
index 0000000000..9b50016a93
--- /dev/null
+++ b/src/mainboard/intel/dq67sw/gpio.c
@@ -0,0 +1,212 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_NATIVE,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_GPIO,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_GPIO,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio5 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio9 = GPIO_DIR_OUTPUT,
+	.gpio11 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio20 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio8 = GPIO_LEVEL_HIGH,
+	.gpio9 = GPIO_LEVEL_HIGH,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_GPIO,
+	.gpio46 = GPIO_MODE_GPIO,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_NATIVE,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_OUTPUT,
+	.gpio35 = GPIO_DIR_OUTPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_OUTPUT,
+	.gpio46 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio50 = GPIO_DIR_OUTPUT,
+	.gpio51 = GPIO_DIR_OUTPUT,
+	.gpio52 = GPIO_DIR_OUTPUT,
+	.gpio53 = GPIO_DIR_OUTPUT,
+	.gpio57 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_LOW,
+	.gpio33 = GPIO_LEVEL_LOW,
+	.gpio34 = GPIO_LEVEL_LOW,
+	.gpio35 = GPIO_LEVEL_LOW,
+	.gpio45 = GPIO_LEVEL_LOW,
+	.gpio46 = GPIO_LEVEL_HIGH,
+	.gpio50 = GPIO_LEVEL_HIGH,
+	.gpio51 = GPIO_LEVEL_HIGH,
+	.gpio52 = GPIO_LEVEL_HIGH,
+	.gpio53 = GPIO_LEVEL_HIGH,
+	.gpio57 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_GPIO,
+	.gpio65 = GPIO_MODE_GPIO,
+	.gpio66 = GPIO_MODE_GPIO,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio64 = GPIO_DIR_INPUT,
+	.gpio65 = GPIO_DIR_INPUT,
+	.gpio66 = GPIO_DIR_OUTPUT,
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+	.gpio66 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/intel/dq67sw/hda_verb.c b/src/mainboard/intel/dq67sw/hda_verb.c
new file mode 100644
index 0000000000..81794c15ad
--- /dev/null
+++ b/src/mainboard/intel/dq67sw/hda_verb.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0888, /* Codec Vendor / Device ID: Realtek ALC888 */
+	0x80862008, /* Subsystem ID */
+	15,	    /* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(2, 0x80862008),
+	AZALIA_PIN_CFG(2, 0x11, 0x411111f0),
+	AZALIA_PIN_CFG(2, 0x12, 0x411111f0),
+	AZALIA_PIN_CFG(2, 0x14, 0x01014410),
+	AZALIA_PIN_CFG(2, 0x15, 0x411111f0),
+	AZALIA_PIN_CFG(2, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(2, 0x17, 0x99130140),
+	AZALIA_PIN_CFG(2, 0x18, 0x01a19c50),
+	AZALIA_PIN_CFG(2, 0x19, 0x02a19960),
+	AZALIA_PIN_CFG(2, 0x1a, 0x0181345f),
+	AZALIA_PIN_CFG(2, 0x1b, 0x02214120),
+	AZALIA_PIN_CFG(2, 0x1c, 0x411111f0),
+	AZALIA_PIN_CFG(2, 0x1d, 0x4004c601),
+	AZALIA_PIN_CFG(2, 0x1e, 0x99430130),
+	AZALIA_PIN_CFG(2, 0x1f, 0x411111f0),
+
+	0x80862805, /* Codec Vendor / Device ID: Intel */
+	0x80862008, /* Subsystem ID */
+	4,	    /* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80862008),
+	AZALIA_PIN_CFG(3, 0x05, 0x58560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x58560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;