diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2022-03-16 11:13:27 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2022-03-21 03:11:44 +0000 |
| commit | d6727ba9723be806713320a7ff19e5d5c3bd1d3f (patch) | |
| tree | 4b3ace106c4c88302dc849358e4c58e88e4bfca8 | |
| parent | 5b51faaaea48adf49429d4bfb96d88d9e5d9e08c (diff) | |
mb/google/corsola: Revise power-on sequence of PS8640
Although the panel initializes fine and the fw recovery screen is
displayed without issues, the current power-on sequence of the
PS8640 violates the spec of the PS8640, which can be confirmed by
measuring it with an oscilloscope.
The sequence is:
- set VDD12 to be 1.2V
- set VDD33 to be 3.3V
- pull hign PD#
- pull down RST#
- delay 2ms
- pull high RST#
- delay more than 50ms (55ms for margin)
- pull down RST#
- delay more than 50ms (55ms for margin)
- pull high RST#
This flow will increase 110ms if firmware display is enabled in
krabby. For normal booting flow, the firmware will not be enabled,
so it will meet boot time requirements of Chrome OS. (Less than 1s.)
Datasheet name: PS8640_DS_V1.4_20200210.docx.
Chapter: 14.
BUG=b:222650141
TEST=show fw display normally in krabby.
TEST=result of waveform meets the spec.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7706c56dc7fc13ac84c0d52a6e534bc0988e8fd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
| -rw-r--r-- | src/mainboard/google/corsola/display.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/google/corsola/display.c b/src/mainboard/google/corsola/display.c index fd269eca35..48ab58e324 100644 --- a/src/mainboard/google/corsola/display.c +++ b/src/mainboard/google/corsola/display.c @@ -19,6 +19,20 @@ /* Bridge functions */ static void bridge_ps8640_power_on(void) { + /* + * PS8640 power-on sequence is described in chapter 14, PS8640_DS_V1.4_20200210.docx + * - set VDD12 to be 1.2V + * - set VDD33 to be 3.3V + * - pull hign PD# + * - pull down RST# + * - delay 2ms + * - pull high RST# + * - delay more than 50ms (55ms for margin) + * - pull down RST# + * - delay more than 50ms (55ms for margin) + * - pull high RST# + */ + /* Set VRF12 to 1.2V and VCN33 to 3.3V */ mainboard_set_regulator_vol(MTK_REGULATOR_VRF12, 1200000); mainboard_set_regulator_vol(MTK_REGULATOR_VCN33, 3300000); @@ -29,6 +43,10 @@ static void bridge_ps8640_power_on(void) gpio_output(GPIO_EDPBRDG_RST_L, 0); mdelay(2); gpio_output(GPIO_EDPBRDG_RST_L, 1); + mdelay(55); + gpio_output(GPIO_EDPBRDG_RST_L, 0); + mdelay(55); + gpio_output(GPIO_EDPBRDG_RST_L, 1); } static int bridge_ps8640_get_edid(u8 i2c_bus, struct edid *edid) |