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authorDtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>2021-05-31 13:32:28 +0800
committerWerner Zeh <werner.zeh@siemens.com>2021-06-28 04:29:30 +0000
commitd3230b5f7067db693386068247762bb8a4abe631 (patch)
tree8fcd94319f2f4e19e2443dc5a60a61f52fa55f1f
parent43fd0402265c0c1381fc3fcf04610ed9f2781f2f (diff)
mb/google/dedede/var/cret: Add ssfc codec cs42l42 support
Add cs42l42 codec support in cret. BUG=b:188623237, b:189073353 TEST=Build and boot to check functional with cs42l42 EV board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I2c53291e07fd785c1360c05171eed634788bc665 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55091 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/dedede/Kconfig1
-rw-r--r--src/mainboard/google/dedede/variants/cret/gpio.c14
-rw-r--r--src/mainboard/google/dedede/variants/cret/overridetree.cb32
3 files changed, 46 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index 758143a370..29be866ead 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -2,6 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE
def_bool n
select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768
select DRIVERS_GENERIC_GPIO_KEYS
+ select DRIVERS_I2C_CS42L42
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_GPIO_MUX
select DRIVERS_I2C_HID
diff --git a/src/mainboard/google/dedede/variants/cret/gpio.c b/src/mainboard/google/dedede/variants/cret/gpio.c
index 5acef69648..8cff3656ef 100644
--- a/src/mainboard/google/dedede/variants/cret/gpio.c
+++ b/src/mainboard/google/dedede/variants/cret/gpio.c
@@ -41,6 +41,8 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_H6, NONE),
/* H7 : AP_I2C_CAM_SCL ==> NC */
PAD_NC(GPP_H7, NONE),
+ /* H16 : AP_SUB_IO_L ==> HP_RST_ODL */
+ PAD_CFG_GPO(GPP_H16, 1, PWROK),
/* H17 : WWAN_RST_L */
PAD_CFG_GPO(GPP_H17, 1, PLTRST),
/* G0 : SD_CMD ==> NC */
@@ -67,6 +69,14 @@ static const struct pad_config lte_disable_pads[] = {
PAD_NC(GPP_H17, NONE),
};
+static const struct pad_config codec_da7219_pads[] = {
+ PAD_NC(GPP_H16, NONE),
+};
+
+static const struct pad_config codec_cs42l42_pads[] = {
+ PAD_NC(GPP_D18, NONE),
+};
+
const struct pad_config *variant_override_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(override_gpio_table);
@@ -77,5 +87,9 @@ static void fw_config_handle(void *unused)
{
if (!fw_config_probe(FW_CONFIG(LTE, LTE_PRESENT)))
gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads));
+ if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, AUDIO_CODEC_DA7219)))
+ gpio_configure_pads(codec_da7219_pads, ARRAY_SIZE(codec_da7219_pads));
+ if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, AUDIO_CODEC_CS42l42)))
+ gpio_configure_pads(codec_cs42l42_pads, ARRAY_SIZE(codec_cs42l42_pads));
}
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/dedede/variants/cret/overridetree.cb b/src/mainboard/google/dedede/variants/cret/overridetree.cb
index 9c2a73ec16..be84c79fde 100644
--- a/src/mainboard/google/dedede/variants/cret/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/cret/overridetree.cb
@@ -1,3 +1,12 @@
+fw_config
+ field AUDIO_CODEC_SOURCE 41 43
+ option AUDIO_CODEC_UNPROVISIONED 0
+ option AUDIO_CODEC_DA7219 1
+ option AUDIO_CODEC_RT5682 2
+ option AUDIO_CODEC_CS42l42 3
+ end
+end
+
chip soc/intel/jasperlake
# USB Port Configuration
@@ -202,7 +211,28 @@ chip soc/intel/jasperlake
register "adc_1bit_rpt" = "1"
register "micbias_lvl" = "2600"
register "mic_amp_in_sel" = ""diff""
- device i2c 1a on end
+ device i2c 1a on
+ probe AUDIO_CODEC_SOURCE AUDIO_CODEC_UNPROVISIONED
+ probe AUDIO_CODEC_SOURCE AUDIO_CODEC_DA7219
+ end
+ end
+ chip drivers/i2c/cs42l42
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H16)"
+ register "ts_inv" = "true"
+ register "ts_dbnc_rise" = "RISE_DEB_1000_MS"
+ register "ts_dbnc_fall" = "FALL_DEB_0_MS"
+ register "btn_det_init_dbnce" = "100"
+ register "btn_det_event_dbnce" = "10"
+ register "bias_lvls[0]" = "15"
+ register "bias_lvls[1]" = "8"
+ register "bias_lvls[2]" = "4"
+ register "bias_lvls[3]" = "1"
+ register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW"
+ register "hs_bias_sense_disable" = "true"
+ device i2c 48 on
+ probe AUDIO_CODEC_SOURCE AUDIO_CODEC_CS42l42
+ end
end
end #I2C 4
device pci 1f.3 on