Define global uma_memory variables

Use of the uma_memory_base and _size variables is very scattered.
Implementation of setup_uma_memory() will appear in each northbridge.

It should be possible to do this setup entirely in northbridge
code and get rid of the globals in a follow-up.

Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

50 files changed, 10 insertions, 105 deletions

diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index 5c48cfd96c..7fabb44eb3 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -6,10 +6,6 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/msr.h>
 
-#if CONFIG_GFXUMA
-extern uint64_t uma_memory_size;
-#endif
-
 static unsigned long resk(uint64_t value)
 {
 	unsigned long resultk;
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index f9e0716283..1ffec0eb76 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -40,10 +40,6 @@
 #include <arch/cpu.h>
 #include <arch/acpi.h>
 
-#if CONFIG_GFXUMA
-extern uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 static unsigned int mtrr_msr[] = {
 	MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
 	MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
diff --git a/src/devices/device.c b/src/devices/device.c
index fafa59924e..c378078de2 100644
--- a/src/devices/device.c
+++ b/src/devices/device.c
@@ -54,6 +54,11 @@ struct resource *free_resources = NULL;
 
 DECLARE_SPIN_LOCK(dev_lock)
 
+
+/* IGD UMA memory */
+uint64_t uma_memory_base = 0;
+uint64_t uma_memory_size = 0;
+
 /**
  * Allocate a new device structure.
  *
diff --git a/src/include/device/device.h b/src/include/device/device.h
index eb73c4ef53..819b789466 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -110,6 +110,11 @@ extern struct device	*all_devices;	/* list of all devices */
 extern struct resource	*free_resources;
 extern struct bus	*free_links;
 
+/* IGD UMA memory */
+void setup_uma_memory(void);
+extern uint64_t uma_memory_base;
+extern uint64_t uma_memory_size;
+
 /* Generic device interface functions */
 device_t alloc_dev(struct bus *parent, struct device_path *path);
 void dev_enumerate(void);
diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c
index afa82f3eeb..3504ac22de 100644
--- a/src/mainboard/advansus/a785e-i/mainboard.c
+++ b/src/mainboard/advansus/a785e-i/mainboard.c
@@ -28,7 +28,6 @@
 #include "SBPLATFORM.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
 
 u8 is_dev3_present(void);
 void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c
index 241d9057c0..4d685e2f02 100644
--- a/src/mainboard/amd/bimini_fam10/mainboard.c
+++ b/src/mainboard/amd/bimini_fam10/mainboard.c
@@ -28,7 +28,6 @@
 #include <southbridge/amd/sb800/sb800.h>
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
 
 u8 is_dev3_present(void);
 void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c
index 8841291c92..c5515b42a6 100644
--- a/src/mainboard/amd/dbm690t/mainboard.c
+++ b/src/mainboard/amd/dbm690t/mainboard.c
@@ -42,7 +42,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
 #define ADT7461_write_byte(address, val) \
 	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /********************************************************
 * dbm690t uses a BCM5789 as on-board NIC.
diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c
index 360e1df447..8eea6da799 100644
--- a/src/mainboard/amd/dinar/mainboard.c
+++ b/src/mainboard/amd/dinar/mainboard.c
@@ -67,7 +67,6 @@ void set_pcie_dereset(void *nbconfig)
 	}
 }
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /*************************************************
  * enable the dedicated function in dinar board.
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
index d35b1757f9..41aa907f37 100644
--- a/src/mainboard/amd/inagua/mainboard.c
+++ b/src/mainboard/amd/inagua/mainboard.c
@@ -71,7 +71,6 @@ void set_pcie_dereset(void)
 	RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG50, AccWidthUint8, ~(0xFF), 0x48);
 }
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /*************************************************
  * enable the dedicated function in INAGUA    board.
diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c
index 989070cb03..a263f6eeb4 100644
--- a/src/mainboard/amd/mahogany/mainboard.c
+++ b/src/mainboard/amd/mahogany/mainboard.c
@@ -29,8 +29,6 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);
diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c
index 1f1941b02d..16dff473ea 100644
--- a/src/mainboard/amd/mahogany_fam10/mainboard.c
+++ b/src/mainboard/amd/mahogany_fam10/mainboard.c
@@ -29,8 +29,6 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);
diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c
index 76a9ae6ae4..c0db1c051e 100644
--- a/src/mainboard/amd/persimmon/mainboard.c
+++ b/src/mainboard/amd/persimmon/mainboard.c
@@ -50,7 +50,6 @@ void set_pcie_dereset(void)
 {
 }
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /*************************************************
 * enable the dedicated function in persimmon board.
diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c
index e5d0efa807..6f62b58688 100644
--- a/src/mainboard/amd/pistachio/mainboard.c
+++ b/src/mainboard/amd/pistachio/mainboard.c
@@ -39,7 +39,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
 #define ADT7475_write_byte(address, val) \
 	do_smbus_write_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address, val)
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /********************************************************
 * pistachio uses a BCM5787 as on-board NIC.
diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c
index ed65b34622..bb6c52283c 100644
--- a/src/mainboard/amd/south_station/mainboard.c
+++ b/src/mainboard/amd/south_station/mainboard.c
@@ -28,7 +28,6 @@
 #include "SBPLATFORM.h" 	/* Platfrom Specific Definitions */
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
 
 void set_pcie_reset(void);
 void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c
index e2ef3f96bb..1777c2b15e 100644
--- a/src/mainboard/amd/tilapia_fam10/mainboard.c
+++ b/src/mainboard/amd/tilapia_fam10/mainboard.c
@@ -39,8 +39,6 @@
 #define ADT7461_write_byte(address, val) \
 	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);
diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c
index 7248bfb27f..ee9ffa43dc 100644
--- a/src/mainboard/amd/torpedo/mainboard.c
+++ b/src/mainboard/amd/torpedo/mainboard.c
@@ -50,7 +50,6 @@ void set_pcie_dereset(void)
 {
 }
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /*************************************************
 * enable the dedicated function in torpedo board.
diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c
index c5b481d5f0..81777d80c1 100644
--- a/src/mainboard/amd/union_station/mainboard.c
+++ b/src/mainboard/amd/union_station/mainboard.c
@@ -47,7 +47,6 @@ void set_pcie_dereset(void)
 {
 }
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /*************************************************
 * enable the dedicated function in unionstation board.
diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c
index 0b566e445f..d1b06c5afc 100644
--- a/src/mainboard/asrock/939a785gmh/mainboard.c
+++ b/src/mainboard/asrock/939a785gmh/mainboard.c
@@ -29,8 +29,6 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);
diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c
index 8642e28266..bf13746a87 100644
--- a/src/mainboard/asrock/e350m1/mainboard.c
+++ b/src/mainboard/asrock/e350m1/mainboard.c
@@ -46,7 +46,6 @@ void set_pcie_dereset(void)
 {
 }
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /*************************************************
 * enable the dedicated function in e350m1 board.
diff --git a/src/mainboard/asus/m2v-mx_se/mainboard.c b/src/mainboard/asus/m2v-mx_se/mainboard.c
index c936fa9042..d5b93048a8 100644
--- a/src/mainboard/asus/m2v-mx_se/mainboard.c
+++ b/src/mainboard/asus/m2v-mx_se/mainboard.c
@@ -24,10 +24,6 @@
 #include <southbridge/via/k8t890/k8t890.h>
 #include "chip.h"
 
-#if CONFIG_GFXUMA
-uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 int add_mainboard_resources(struct lb_memory *mem)
 {
 #if CONFIG_GFXUMA
diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c
index 10ecb64e36..2b4e97cae1 100644
--- a/src/mainboard/asus/m4a78-em/mainboard.c
+++ b/src/mainboard/asus/m4a78-em/mainboard.c
@@ -29,8 +29,6 @@
 #include "chip.h"
 
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);
diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c
index 3b681434c0..36933006c1 100644
--- a/src/mainboard/asus/m4a785-m/mainboard.c
+++ b/src/mainboard/asus/m4a785-m/mainboard.c
@@ -38,8 +38,6 @@
 #define ADT7461_write_byte(address, val) \
 	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);
diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c
index 38b964839a..291510cbe0 100644
--- a/src/mainboard/asus/m5a88-v/mainboard.c
+++ b/src/mainboard/asus/m5a88-v/mainboard.c
@@ -28,7 +28,6 @@
 #include "SBPLATFORM.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
 
 u8 is_dev3_present(void);
 void set_pcie_dereset(void);
diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c
index 52befa5a47..89a0e96252 100644
--- a/src/mainboard/avalue/eax-785e/mainboard.c
+++ b/src/mainboard/avalue/eax-785e/mainboard.c
@@ -28,7 +28,6 @@
 #include "SBPLATFORM.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
 
 u8 is_dev3_present(void);
 void set_pcie_dereset(void);
diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c
index 254df007ef..ea3f27ee50 100644
--- a/src/mainboard/gigabyte/ma785gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gm/mainboard.c
@@ -29,8 +29,6 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 int is_dev3_present(void);
diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c
index 8d669bab52..174c08de84 100644
--- a/src/mainboard/gigabyte/ma785gmt/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c
@@ -39,8 +39,6 @@
 #define ADT7461_write_byte(address, val) \
 	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 int is_dev3_present(void);
diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c
index ee353edc03..b81ebaa0ee 100644
--- a/src/mainboard/gigabyte/ma78gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma78gm/mainboard.c
@@ -30,8 +30,6 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);
diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c
index ef02c89a85..6d20523abf 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c
@@ -29,8 +29,6 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);
diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c
index e992f74e85..329b4f6c25 100644
--- a/src/mainboard/jetway/pa78vm5/mainboard.c
+++ b/src/mainboard/jetway/pa78vm5/mainboard.c
@@ -30,8 +30,6 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);
diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c
index c2a401e0c4..fcb24620c6 100644
--- a/src/mainboard/kontron/kt690/mainboard.c
+++ b/src/mainboard/kontron/kt690/mainboard.c
@@ -42,7 +42,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
 #define ADT7461_write_byte(address, val) \
 	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /********************************************************
 * dbm690t uses a BCM5789 as on-board NIC.
diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c
index 0d7b8da741..840e060995 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c
@@ -162,7 +162,6 @@
 extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
 extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
 
-uint64_t uma_memory_base, uma_memory_size;
 static u32 smbus_io_base = SMBUS_IO_BASE;
 static u32 adt7475_address = ADT7475_ADDRESS;
 
diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c
index 635023079b..ab21212223 100644
--- a/src/mainboard/technexion/tim5690/mainboard.c
+++ b/src/mainboard/technexion/tim5690/mainboard.c
@@ -83,7 +83,6 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
 #define ADT7461_write_byte(address, val) \
 	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the
    LDN the register belongs to, before you can access the register. */
diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c
index 18abbc930d..45b1b4d6f2 100644
--- a/src/mainboard/technexion/tim8690/mainboard.c
+++ b/src/mainboard/technexion/tim8690/mainboard.c
@@ -42,7 +42,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
 #define ADT7461_write_byte(address, val) \
 	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
 
-uint64_t uma_memory_base, uma_memory_size;
 
 
 
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index 3a1eb7ba04..12d83ad9d3 100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -908,10 +908,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
 }
 #endif
 
-#if CONFIG_GFXUMA
-extern uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 static void amdfam10_domain_set_resources(device_t dev)
 {
 #if CONFIG_PCI_64BIT_PREF_MEM
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index 50694c7416..6a591c5851 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -338,10 +338,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
 }
 #endif
 
-#if CONFIG_GFXUMA
-extern uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 static void read_resources(device_t dev)
 {
     u32 nodeid;
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index 9e6b257e0f..021a1db2bf 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -326,10 +326,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
 }
 #endif
 
-#if CONFIG_GFXUMA
-extern uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 static void read_resources(device_t dev)
 {
 	u32 nodeid;
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index c76c963620..d9da183bc0 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -626,10 +626,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
 }
 #endif
 
-#if CONFIG_GFXUMA
-extern uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 static void domain_set_resources(device_t dev)
 {
 #if CONFIG_PCI_64BIT_PREF_MEM
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index ef5f1d8416..efc8e685dd 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -613,10 +613,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
 }
 #endif
 
-#if CONFIG_GFXUMA == 1
-extern uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 static void domain_set_resources(device_t dev)
 {
 #if CONFIG_PCI_64BIT_PREF_MEM == 1
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index dd2a9aff16..41434e8fe5 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -847,10 +847,6 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id)
 #include <cbmem.h>
 #endif
 
-#if CONFIG_GFXUMA
-extern uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 static void amdfam10_domain_set_resources(device_t dev)
 {
 #if CONFIG_PCI_64BIT_PREF_MEM
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 621c0f183b..8b9140dd5f 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -822,10 +822,6 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id)
 #include <cbmem.h>
 #endif
 
-#if CONFIG_GFXUMA
-extern uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 static void amdk8_domain_set_resources(device_t dev)
 {
 #if CONFIG_PCI_64BIT_PREF_MEM
diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c
index 78e37285f7..3337417460 100644
--- a/src/northbridge/intel/i82810/northbridge.c
+++ b/src/northbridge/intel/i82810/northbridge.c
@@ -62,9 +62,6 @@ static const struct pci_driver i810e_northbridge_driver __pci_driver = {
 	.device = 0x7124,
 };
 
-/* IGD UMA memory */
-uint64_t uma_memory_base=0, uma_memory_size=0;
-
 int add_northbridge_resources(struct lb_memory *mem)
 {
 	printk(BIOS_DEBUG, "Adding IGD UMA memory area\n");
diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c
index 93bdc28196..22f59dc313 100644
--- a/src/northbridge/intel/i82830/northbridge.c
+++ b/src/northbridge/intel/i82830/northbridge.c
@@ -52,9 +52,6 @@ static const struct pci_driver northbridge_driver __pci_driver = {
 	.device = 0x3575,
 };
 
-/* IGD memory */
-uint64_t uma_memory_base=0, uma_memory_size=0;
-
 int add_northbridge_resources(struct lb_memory *mem)
 {
 	printk(BIOS_DEBUG, "Adding IGD UMA memory area\n");
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 40b1aaac96..58e70d7fa0 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -68,9 +68,6 @@ static int get_pcie_bar(u32 *base, u32 *len)
 	return 0;
 }
 
-/* IDG memory */
-uint64_t uma_memory_base=0, uma_memory_size=0;
-
 static void add_fixed_resources(struct device *dev, int index)
 {
 	struct resource *resource;
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 6419f8ce17..b261c9d805 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -118,9 +118,6 @@ static int get_pcie_bar(u32 *base, u32 *len)
 	return 0;
 }
 
-/* IDG memory */
-uint64_t uma_memory_base=0, uma_memory_size=0;
-
 static void add_fixed_resources(struct device *dev, int index)
 {
 	struct resource *resource;
diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c
index 57245b6bed..047d7dabc5 100644
--- a/src/northbridge/intel/sch/northbridge.c
+++ b/src/northbridge/intel/sch/northbridge.c
@@ -73,9 +73,6 @@ static int get_pcie_bar(u32 *base, u32 *len)
 	return 0;
 }
 
-/* IDG memory */
-u64 uma_memory_base = 0, uma_memory_size = 0;
-
 static void add_fixed_resources(struct device *dev, int index)
 {
 	struct resource *resource;
diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c
index 5e06d4f9d8..68c46e9728 100644
--- a/src/southbridge/amd/rs690/cmn.c
+++ b/src/southbridge/amd/rs690/cmn.c
@@ -315,8 +315,6 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 */
 void rs690_set_tom(device_t nb_dev)
 {
-	extern uint64_t uma_memory_base;
-
 	/* set TOM */
 	pci_write_config32(nb_dev, 0x90, uma_memory_base);
 	nbmc_write_index(nb_dev, 0x1e, uma_memory_base);
diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c
index 40a72627e0..5c72a04227 100644
--- a/src/southbridge/amd/rs780/cmn.c
+++ b/src/southbridge/amd/rs780/cmn.c
@@ -356,8 +356,6 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 */
 void rs780_set_tom(device_t nb_dev)
 {
-	extern uint64_t uma_memory_base;
-
 	/* set TOM */
 	pci_write_config32(nb_dev, 0x90, uma_memory_base);
 	//nbmc_write_index(nb_dev, 0x1e, uma_memory_base);
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index e07aa101d5..904e154de5 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -43,8 +43,6 @@ extern int is_dev3_present(void);
 void set_pcie_reset(void);
 void set_pcie_dereset(void);
 
-extern uint64_t uma_memory_base, uma_memory_size;
-
 /* Trust the original resource allocation. Don't do it again. */
 #undef DONT_TRUST_RESOURCE_ALLOCATION
 //#define DONT_TRUST_RESOURCE_ALLOCATION
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index 9b153aae1b..f1029cac82 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -221,7 +221,6 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
 	/* Program Straps. */
 	romstrap2 = 1 << 26; // enables audio function
 #if CONFIG_GFXUMA
-	extern uint64_t uma_memory_size;
 	// bits 7-9: aperture size
 	// 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g
 	if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7;
diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c
index 7e450cc69c..11c84812b7 100644
--- a/src/southbridge/via/k8t890/dram.c
+++ b/src/southbridge/via/k8t890/dram.c
@@ -71,10 +71,6 @@ static void dram_enable(struct device *dev)
 
 }
 
-#if CONFIG_GFXUMA
-extern uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 static void dram_enable_k8m890(struct device *dev)
 {
 #if CONFIG_GFXUMA