soc/amd/sabrina: drop CPPC code

The CPPC feature isn't available on the Sabrina SoC, so drop the
corresponding code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I71a1b0717571729ebca3600ac433e621cafc4e61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

7 files changed, 0 insertions, 114 deletions

diff --git a/src/soc/amd/sabrina/Makefile.inc b/src/soc/amd/sabrina/Makefile.inc
index 2beb6dec77..9ee6e81a08 100644
--- a/src/soc/amd/sabrina/Makefile.inc
+++ b/src/soc/amd/sabrina/Makefile.inc
@@ -33,7 +33,6 @@ romstage-y	+= uart.c
 ramstage-y	+= acpi.c
 ramstage-y	+= agesa_acpi.c
 ramstage-y	+= chip.c
-ramstage-y	+= cppc.c
 ramstage-y	+= cpu.c
 ramstage-y	+= data_fabric.c
 ramstage-y	+= fch.c
diff --git a/src/soc/amd/sabrina/acpi.c b/src/soc/amd/sabrina/acpi.c
index 8fbe624e6e..b10773b7d5 100644
--- a/src/soc/amd/sabrina/acpi.c
+++ b/src/soc/amd/sabrina/acpi.c
@@ -21,7 +21,6 @@
 #include <soc/msr.h>
 #include <types.h>
 #include "chip.h"
-#include <soc/cppc.h>
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
@@ -359,8 +358,6 @@ void generate_cpu_entries(const struct device *device)
 		acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
 					  CSD_HW_ALL, 0);
 
-		generate_cppc_entries(cpu);
-
 		acpigen_pop_len();
 	}
 
diff --git a/src/soc/amd/sabrina/chip.h b/src/soc/amd/sabrina/chip.h
index 6903180b88..a7acb7f29f 100644
--- a/src/soc/amd/sabrina/chip.h
+++ b/src/soc/amd/sabrina/chip.h
@@ -68,13 +68,6 @@ struct soc_amd_sabrina_config {
 
 	uint8_t system_configuration;
 
-	uint8_t cppc_ctrl;
-	uint8_t cppc_perf_limit_max_range;
-	uint8_t cppc_perf_limit_min_range;
-	uint8_t cppc_epp_max_range;
-	uint8_t cppc_epp_min_range;
-	uint8_t cppc_preferred_cores;
-
 	/* telemetry settings */
 	uint32_t telemetry_vddcrvddfull_scale_current_mA;
 	uint32_t telemetry_vddcrvddoffset;
diff --git a/src/soc/amd/sabrina/cppc.c b/src/soc/amd/sabrina/cppc.c
deleted file mode 100644
index d35e0a5a42..0000000000
--- a/src/soc/amd/sabrina/cppc.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* TODO: Check if this is still correct */
-
-#include <acpi/acpi_pm.h>
-#include <acpi/acpigen.h>
-#include <arch/cpu.h>
-#include <soc/cppc.h>
-#include <soc/msr.h>
-
-/*
- * version 2 is expected to be the typical use case.
- * For now this function 'punts' on version 3 and just
- * populates the additional fields with 'unsupported'.
- */
-void cpu_init_cppc_config(struct cppc_config *config, u32 version)
-{
-	config->version = version;
-
-	config->entries[CPPC_HIGHEST_PERF]		= CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8);
-	config->entries[CPPC_NOMINAL_PERF]		= CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8);
-	config->entries[CPPC_LOWEST_NONL_PERF]		= CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8);
-	config->entries[CPPC_LOWEST_PERF]		= CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8);
-	config->entries[CPPC_GUARANTEED_PERF]		= CPPC_UNSUPPORTED;
-	config->entries[CPPC_DESIRED_PERF]		= CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8);
-	config->entries[CPPC_MIN_PERF]			= CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8);
-	config->entries[CPPC_MAX_PERF]			= CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8);
-	config->entries[CPPC_PERF_REDUCE_TOLERANCE]	= CPPC_UNSUPPORTED;
-	config->entries[CPPC_TIME_WINDOW]		= CPPC_UNSUPPORTED;
-	config->entries[CPPC_COUNTER_WRAP]		= CPPC_UNSUPPORTED;
-	config->entries[CPPC_REF_PERF_COUNTER]		= CPPC_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
-	config->entries[CPPC_DELIVERED_PERF_COUNTER]	= CPPC_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
-	config->entries[CPPC_PERF_LIMITED]		= CPPC_REG_MSR(MSR_CPPC_STATUS, 1, 1);
-	config->entries[CPPC_ENABLE]			= CPPC_REG_MSR(MSR_CPPC_ENABLE, 0, 1);
-
-	if (version < 2)
-		return;
-
-	config->entries[CPPC_AUTO_SELECT]		= CPPC_UNSUPPORTED;
-	config->entries[CPPC_AUTO_ACTIVITY_WINDOW]	= CPPC_UNSUPPORTED;
-	config->entries[CPPC_PERF_PREF]			= CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8);
-	config->entries[CPPC_REF_PERF]			= CPPC_UNSUPPORTED;
-
-	if (version < 3)
-		return;
-
-	config->entries[CPPC_LOWEST_FREQ]		= CPPC_UNSUPPORTED;
-	config->entries[CPPC_NOMINAL_FREQ]		= CPPC_UNSUPPORTED;
-}
-
-
-void generate_cppc_entries(unsigned int core_id)
-{
-	/* Generate GCPC package in first logical core */
-	if (core_id == 0) {
-		struct cppc_config cppc_config;
-		cpu_init_cppc_config(&cppc_config, CPPC_VERSION_3);
-		acpigen_write_CPPC_package(&cppc_config);
-	}
-
-	/* Write _CPC entry for each logical core */
-	acpigen_write_CPPC_method();
-}
diff --git a/src/soc/amd/sabrina/fsp_m_params.c b/src/soc/amd/sabrina/fsp_m_params.c
index 95d2d1eb30..f069ba8f61 100644
--- a/src/soc/amd/sabrina/fsp_m_params.c
+++ b/src/soc/amd/sabrina/fsp_m_params.c
@@ -121,14 +121,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	/* 0 is default */
 	mcfg->system_configuration = config->system_configuration;
 
-	/* when cppc_ctrl is 0 the other values won't be used */
-	mcfg->cppc_ctrl = config->cppc_ctrl;
-	mcfg->cppc_perf_limit_max_range = config->cppc_perf_limit_max_range;
-	mcfg->cppc_perf_limit_min_range = config->cppc_perf_limit_min_range;
-	mcfg->cppc_epp_max_range = config->cppc_epp_max_range;
-	mcfg->cppc_epp_min_range = config->cppc_epp_min_range;
-	mcfg->cppc_preferred_cores = config->cppc_preferred_cores;
-
 	/* S0i3 enable */
 	mcfg->s0i3_enable = config->s0ix_enable;
 	mcfg->iommu_support = is_devfn_enabled(IOMMU_DEVFN);
diff --git a/src/soc/amd/sabrina/include/soc/cppc.h b/src/soc/amd/sabrina/include/soc/cppc.h
deleted file mode 100644
index 7ae94bfb3d..0000000000
--- a/src/soc/amd/sabrina/include/soc/cppc.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* TODO: Check if this is still correct */
-
-#ifndef AMD_SABRINA_CPPC_H
-#define AMD_SABRINA_CPPC_H
-
-#include <types.h>
-#include <acpi/acpigen.h>
-
-struct cppc_config;
-void cpu_init_cppc_config(struct cppc_config *config, u32 version);
-void generate_cppc_entries(unsigned int core_id);
-
-#endif /* AMD_SABRINA_CPPC_H */
diff --git a/src/soc/amd/sabrina/include/soc/msr.h b/src/soc/amd/sabrina/include/soc/msr.h
index 48c2fd13ec..bdc7a14c40 100644
--- a/src/soc/amd/sabrina/include/soc/msr.h
+++ b/src/soc/amd/sabrina/include/soc/msr.h
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Check if this is still correct */
-
 #ifndef AMD_SABRINA_MSR_H
 #define AMD_SABRINA_MSR_H
 
@@ -23,21 +21,6 @@
 #define PSTATE_DEF_LO_FREQ_MUL_MASK	(0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT)
 #define PSTATE_DEF_LO_CORE_FREQ_BASE	25
 
-#define MSR_CPPC_CAPABILITY_1				0xc00102b0
-#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF		24
-#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF		16
-#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF	8
-#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF		0
-
-#define MSR_CPPC_ENABLE				0xc00102b1
-#define MSR_CPPC_REQUEST			0xc00102b3
-#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF	24
-#define SHIFT_CPPC_REQUEST_DES_PERF		16
-#define SHIFT_CPPC_REQUEST_MIN_PERF		8
-#define SHIFT_CPPC_REQUEST_MAX_PERF		0
-
-#define MSR_CPPC_STATUS		0xc00102b4
-
 #define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe7
 #define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe8