diff options
| author | Fred Reitberger <reitbergerfred@gmail.com> | 2022-11-07 15:14:59 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-10 15:52:36 +0000 |
| commit | c989d3cd10fa71e19d98320c610efbaf12d4a122 (patch) | |
| tree | 73b00814d0860a302e9e3eee8d590a7971595fe2 | |
| parent | fdfd63be3a1ff2b8b866cae9d4f96b3878d8e577 (diff) | |
mb/amd/chausie/ec.c: Enable WLAN
Enable WLAN power and deassert the various radio disables.
TEST=boot chausie
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I2d21905001fa776c0d5c864d83dcd697e3febe0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
| -rw-r--r-- | src/mainboard/amd/chausie/ec.c | 39 |
1 files changed, 27 insertions, 12 deletions
diff --git a/src/mainboard/amd/chausie/ec.c b/src/mainboard/amd/chausie/ec.c index 78465fa013..fb96a4c721 100644 --- a/src/mainboard/amd/chausie/ec.c +++ b/src/mainboard/amd/chausie/ec.c @@ -7,27 +7,35 @@ #define CHAUSIE_EC_DATA 0x662 #define EC_GPIO_3_ADDR 0xA3 -#define EC_GPIO_LOM_RESET_AUX BIT(1) +#define EC_GPIO_LOM_RESET_AUX BIT(1) #define EC_GPIO_7_ADDR 0xA7 -#define EC_GPIO_DT_PWREN BIT(2) -#define EC_GPIO_WWAN_MODULE_RST BIT(5) +#define EC_GPIO_DT_PWREN BIT(2) +#define EC_GPIO_WWAN_MODULE_RST BIT(5) #define EC_GPIO_8_ADDR 0xA8 -#define EC_GPIO_SMBUS0_EN BIT(0) +#define EC_GPIO_SMBUS0_EN BIT(0) #define EC_GPIO_A_ADDR 0xAA -#define EC_GPIO_WWAN_PWREN BIT(3) -#define EC_GPIO_M2_SSD0_PWREN BIT(6) -#define EC_GPIO_LOM_PWREN BIT(7) +#define EC_GPIO_WWAN_PWREN BIT(3) +#define EC_GPIO_WLAN_PWREN BIT(4) +#define EC_GPIO_M2_SSD0_PWREN BIT(6) +#define EC_GPIO_LOM_PWREN BIT(7) + +#define EC_GPIO_B_ADDR 0xAB +#define EC_GPIO_WL_RADIO_DIS BIT(0) +#define EC_GPIO_BT_RADIO_DIS BIT(2) +#define EC_GPIO_GNSS_RADIO_DIS_N BIT(5) +#define EC_GPIO_MAIN_RADIO_DIS_N BIT(6) +#define EC_GPIO_WWAN_POWER_OFF_N BIT(7) #define EC_GPIO_C_ADDR 0xAC -#define EC_GPIO_DT_N_WLAN_SW BIT(1) -#define EC_GPIO_MP2_SEL BIT(2) -#define EC_GPIO_WWAN_N_LOM_SW BIT(3) +#define EC_GPIO_DT_N_WLAN_SW BIT(1) +#define EC_GPIO_MP2_SEL BIT(2) +#define EC_GPIO_WWAN_N_LOM_SW BIT(3) #define EC_SW02_ADDR 0xB7 -#define EC_SW02_MS BIT(7) +#define EC_SW02_MS BIT(7) static void configure_ec_gpio(void) { @@ -46,9 +54,16 @@ static void configure_ec_gpio(void) ec_write(EC_GPIO_8_ADDR, tmp); tmp = ec_read(EC_GPIO_A_ADDR); - tmp |= EC_GPIO_M2_SSD0_PWREN | EC_GPIO_LOM_PWREN | EC_GPIO_WWAN_PWREN; + tmp |= EC_GPIO_M2_SSD0_PWREN | EC_GPIO_LOM_PWREN; + tmp |= EC_GPIO_WLAN_PWREN | EC_GPIO_WWAN_PWREN; ec_write(EC_GPIO_A_ADDR, tmp); + tmp = ec_read(EC_GPIO_B_ADDR); + tmp |= EC_GPIO_GNSS_RADIO_DIS_N | EC_GPIO_MAIN_RADIO_DIS_N; + tmp |= EC_GPIO_WWAN_POWER_OFF_N; + tmp &= ~EC_GPIO_WL_RADIO_DIS & ~EC_GPIO_BT_RADIO_DIS; + ec_write(EC_GPIO_B_ADDR, tmp); + tmp = ec_read(EC_GPIO_C_ADDR); tmp |= EC_GPIO_WWAN_N_LOM_SW | EC_GPIO_MP2_SEL | EC_GPIO_DT_N_WLAN_SW; ec_write(EC_GPIO_C_ADDR, tmp); |