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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-12 23:50:37 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-14 18:54:35 +0000 |
| commit | c66e1c2a319a682a4616589901df301a816076ae (patch) | |
| tree | 9d05943ffb743a0a31f15e65c60efe6ab52d6481 | |
| parent | ed21df6cec49f2c7dd5ae8286eaee958104e781d (diff) | |
soc/intel/cnl: enable ACPI CPPC entries generation
Enable CPPC entries generation, needed for Intel SpeedShift.
Test: dumped SSDT from Clevo L140CU and checked decompiled version
Change-Id: I0c8066a31d3bec27776836aac54c335c0e5d74e6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47541
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 7b9b88be61..f4273407a8 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -103,6 +103,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU |