diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-01-13 17:03:58 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-01-24 02:09:18 +0000 |
| commit | c618b90119171f00886c170b3398a7ce9311d0d6 (patch) | |
| tree | 6d43a04cd07026aec535bcf1ecaf4d28fd0fa273 | |
| parent | eb7e6b5c8160f5edfda1ac080ab77c1ba2c48306 (diff) | |
AGESA f15 cimx/sb700: Remove unused chips code
Change-Id: Id4e05941122c8756f15d5d24482e4cdc04215c55
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
43 files changed, 0 insertions, 4054 deletions
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 77db54cb58..8c8c831a7a 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -17,7 +17,6 @@ config CPU_AMD_AGESA bool default y if CPU_AMD_AGESA_FAMILY12 default y if CPU_AMD_AGESA_FAMILY14 - default y if CPU_AMD_AGESA_FAMILY15 default y if CPU_AMD_AGESA_FAMILY15_TN default y if CPU_AMD_AGESA_FAMILY16_KB default n diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index e581661c06..daa3d50601 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -14,7 +14,6 @@ # subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 -subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig deleted file mode 100644 index 94a38398ca..0000000000 --- a/src/cpu/amd/agesa/family15/Kconfig +++ /dev/null @@ -1,58 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config CPU_AMD_AGESA_FAMILY15 - bool - select X86_AMD_FIXED_MTRRS - -if CPU_AMD_AGESA_FAMILY15 - -config CPU_ADDR_BITS - int - default 48 - -config CPU_AMD_SOCKET_G34 - bool - default n - help - AMD G34 Socket - -config CPU_AMD_SOCKET_C32 - bool - default n - help - AMD C32 Socket - -config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - -config XIP_ROM_SIZE - hex - default 0x80000 - -config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL - bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" - default n - help - This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. - - Warning: Only enable this option when debuging or tracing AMD AGESA code. - -endif #CPU_AMD_AGESA_FAMILY15 diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc deleted file mode 100644 index d01cb2aec5..0000000000 --- a/src/cpu/amd/agesa/family15/Makefile.inc +++ /dev/null @@ -1,29 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -subdirs-y += ../../mtrr -subdirs-y += ../../../x86/tsc -subdirs-y += ../../../x86/lapic -subdirs-y += ../../../x86/cache -subdirs-y += ../../../x86/mtrr -subdirs-y += ../../../x86/pae -subdirs-y += ../../../x86/smm - -romstage-y += fixme.c -romstage-y += romstage.c - -ramstage-y += fixme.c -ramstage-y += chip_name.c -ramstage-y += model_15_init.c diff --git a/src/cpu/amd/agesa/family15/chip_name.c b/src/cpu/amd/agesa/family15/chip_name.c deleted file mode 100644 index f044e4069a..0000000000 --- a/src/cpu/amd/agesa/family15/chip_name.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> - -struct chip_operations cpu_amd_agesa_family15_ops = { - CHIP_NAME("AMD CPU Family 15h Model 00h-0Fh") -}; diff --git a/src/cpu/amd/agesa/family15/fixme.c b/src/cpu/amd/agesa/family15/fixme.c deleted file mode 100644 index bf791b521f..0000000000 --- a/src/cpu/amd/agesa/family15/fixme.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesa_helper.h> -#include <AGESA.h> -#include "amdlib.h" - -UINT64 -MsrRead ( - IN UINT32 MsrAddress - ); - -VOID -MsrWrite ( - IN UINT32 MsrAddress, - IN UINT64 Value - ); - - -UINT64 -MsrRead ( - IN UINT32 MsrAddress - ) -{ - return __readmsr (MsrAddress); -} - -VOID -MsrWrite ( - IN UINT32 MsrAddress, - IN UINT64 Value - ) -{ - __writemsr (MsrAddress, Value); -} - -void amd_initcpuio(void) -{ - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - UINT32 nodes; - UINT32 node; - UINT32 sblink; - UINT32 i; - UINT32 TOM; - - /* get the number of coherent nodes in the system */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); - LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); - nodes = ((PciData >> 4) & 7) + 1; //NodeCnt[2:0] - - /* Find out the Link ID of Node0 that connects to the - * Southbridge (system IO hub). e.g. family10 MCM Processor, - * sbLink is Processor0 Link2, internal Node0 Link3 - */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); - LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); - sblink = (PciData >> 8) & 3; //assume ganged - - /* Enable MMIO on AMD CPU Address Map Controller for all nodes */ - for (node = 0; node < nodes; node++) { - /* clear all MMIO Mapped Base/Limit Registers */ - for (i = 0; i < 8; i++) { - PciData = 0x00000000; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } - - /* clear all IO Space Base/Limit Registers */ - for (i = 0; i < 4; i++) { - PciData = 0x00000000; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } - - /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84); - PciData = 0x00000B00; - PciData |= sblink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80); - PciData = 0x00000A03; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set TOM1-FFFFFFFF to Node0 sbLink. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C); - PciData = 0x00FFFF00; - PciData |= sblink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - TOM = (UINT32)MsrRead(TOP_MEM); - PciData = (TOM >> 8) | 0x03; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set MMCONF space to Node0 sbLink with NP set. - * default E0000000-EFFFFFFF - * Just have all mmio set to non-posted, - * coreboot not implemente the range by range setting yet. - */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC); - PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;//1MB each bus - PciData = (PciData >> 8) & 0xFFFFFF00; - PciData |= 0x80; //NP - PciData |= sblink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xB8); - PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x03; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - - /* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink and enabled VGA IO*/ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4); - PciData = 0x00FFF000; - PciData |= sblink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0); - PciData = 0x00000033; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } -} - -void amd_initmmio(void) -{ - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - * Set the MMIO Configuration Base Address and Bus Range onto - * MMIO configuration base Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000 - CACHE_ROM_SIZE) | 5; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); -} - -#if 0 -#include <cpuFamilyTranslation.h> - -void cpu_show_tsc(void) -{ - UINT32 TscRateInMhz; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **) & FamilySpecificServices, - &AmdParamStruct.StdHeader); - FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); - printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz); -} -#endif diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c deleted file mode 100644 index 531bf29ae9..0000000000 --- a/src/cpu/amd/agesa/family15/model_15_init.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> -#include <device/device.h> -#include <string.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/pae.h> - -#include <cpu/cpu.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/amdfam15.h> - -static void model_15_init(device_t dev) -{ - printk(BIOS_DEBUG, "Model 15 Init.\n"); - - u8 i; - msr_t msr; - int msrno; -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) - u32 siblings; -#endif - - disable_cache (); - /* Enable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr); - - // BSP: make a0000-bffff UC, c0000-fffff WB, same as ApMtrrSettingsList for APs - msr.lo = msr.hi = 0; - wrmsr (0x259, msr); - msr.lo = msr.hi = 0x1e1e1e1e; - for (msrno = 0x268; msrno <= 0x26f; msrno++) - wrmsr (msrno, msr); - - msr.lo = 0x04040404; msr.hi = 0x04040404; - wrmsr(0x259, msr); - - /* disable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr); - enable_cache (); - - /* zero the machine check error status registers */ - msr.lo = 0; - msr.hi = 0; - for (i = 0; i < 6; i++) { - wrmsr(MCI_STATUS + (i * 4), msr); - } - - /* Enable the local CPU APICs */ - setup_lapic(); - -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) - siblings = cpuid_ecx(0x80000008) & 0xff; - - if (siblings > 0) { - msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; - wrmsr_amd(CPU_ID_FEATURES_MSR, msr); - - msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1 << (33 - 32); - wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); - } - printk(BIOS_DEBUG, "siblings = %02d, ", siblings); -#endif - - /* DisableCf8ExtCfg */ - msr = rdmsr(NB_CFG_MSR); - msr.hi &= ~(1 << (46 - 32)); - wrmsr(NB_CFG_MSR, msr); - - - /* Write protect SMM space with SMMLOCK. */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); -} - -static struct device_operations cpu_dev_ops = { - .init = model_15_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */ - { X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */ - { X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */ - { X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */ - { X86_VENDOR_AMD, 0x600f00 }, /* OR_A0x */ - { X86_VENDOR_AMD, 0x600f01 }, /* OR_A0x */ - { X86_VENDOR_AMD, 0x600f10 }, /* OR_B0x */ - { X86_VENDOR_AMD, 0x600f11 }, /* OR_B1x */ - { X86_VENDOR_AMD, 0x600f12 }, /* OR_B2x */ - { X86_VENDOR_AMD, 0x600f13 }, /* OR_B3x */ - { X86_VENDOR_AMD, 0x600f20 }, /* OR_C0x */ - { 0, 0 }, -}; - -static const struct cpu_driver model_15 __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/amd/agesa/family15/romstage.c b/src/cpu/amd/agesa/family15/romstage.c deleted file mode 100644 index 46c03910f7..0000000000 --- a/src/cpu/amd/agesa/family15/romstage.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2017 Kyösti Mälkki - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <lib.h> -#include <reset.h> - -#include <console/console.h> -#include <cpu/amd/car.h> - -#include <northbridge/amd/agesa/state_machine.h> - -#include "northbridge/amd/agesa/family15/reset_test.h" -#include <nb_cimx.h> -#include <sb_cimx.h> - -void platform_once(struct sysinfo *cb) -{ - /* - * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, - * Disable all Pcie Bridges to work around It. - */ - sr56x0_rd890_disable_pcie_bridge(); - - nb_Poweron_Init(); - - sb_Poweron_Init(); - - board_BeforeAgesa(cb); -} - -#if 0 - /* Was between EARLY and POST */ - - nb_Ht_Init(); - post_code(0x3D); - /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - distinguish_cpu_resets(0); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - -#endif diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index b6ac7a4354..338f99a637 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -17,7 +17,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_AGESA),y) subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14 -subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb diff --git a/src/northbridge/amd/agesa/family15/Kconfig b/src/northbridge/amd/agesa/family15/Kconfig deleted file mode 100644 index c895b5d7ab..0000000000 --- a/src/northbridge/amd/agesa/family15/Kconfig +++ /dev/null @@ -1,40 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -config NORTHBRIDGE_AMD_AGESA_FAMILY15 - bool - select HAVE_DEBUG_RAM_SETUP - select HAVE_DEBUG_SMBUS - select HYPERTRANSPORT_PLUGIN_SUPPORT - -if NORTHBRIDGE_AMD_AGESA_FAMILY15 - -config HW_MEM_HOLE_SIZEK - hex - default 0x100000 - -config HW_MEM_HOLE_SIZE_AUTO_INC - bool - default n - -config MMCONF_BASE_ADDRESS - hex - default 0xF8000000 - -config MMCONF_BUS_NUMBER - int - default 64 - -endif # NORTHBRIDGE_AMD_AGESA_FAMILY15 diff --git a/src/northbridge/amd/agesa/family15/Makefile.inc b/src/northbridge/amd/agesa/family15/Makefile.inc deleted file mode 100644 index 3021ef48da..0000000000 --- a/src/northbridge/amd/agesa/family15/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += dimmSpd.c - -ramstage-y += northbridge.c - -romstage-y += state_machine.c -ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family15/amdfam10.h b/src/northbridge/amd/agesa/family15/amdfam10.h deleted file mode 100644 index 27f78a3331..0000000000 --- a/src/northbridge/amd/agesa/family15/amdfam10.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMDFAM10_H -#define AMDFAM10_H - -#include <cpu/x86/msr.h> - -#define HWCR_MSR 0xC0010015 -#define NB_CFG_MSR 0xC001001f -#define LS_CFG_MSR 0xC0011020 -#define IC_CFG_MSR 0xC0011021 -#define DC_CFG_MSR 0xC0011022 -#define BU_CFG_MSR 0xC0011023 -#define BU_CFG2_MSR 0xC001102A - -#define CPU_ID_FEATURES_MSR 0xC0011004 -#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 - -/* Definitions of various FAM10 registers */ -/* Function 0 */ -#define HT_TRANSACTION_CONTROL 0x68 -#define HTTC_DIS_RD_B_P (1 << 0) -#define HTTC_DIS_RD_DW_P (1 << 1) -#define HTTC_DIS_WR_B_P (1 << 2) -#define HTTC_DIS_WR_DW_P (1 << 3) -#define HTTC_DIS_MTS (1 << 4) -#define HTTC_CPU1_EN (1 << 5) -#define HTTC_CPU_REQ_PASS_PW (1 << 6) -#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7) -#define HTTC_DIS_P_MEM_C (1 << 8) -#define HTTC_DIS_RMT_MEM_C (1 << 9) -#define HTTC_DIS_FILL_P (1 << 10) -#define HTTC_RSP_PASS_PW (1 << 11) -#define HTTC_BUF_REL_PRI_SHIFT 13 -#define HTTC_BUF_REL_PRI_MASK 3 -#define HTTC_BUF_REL_PRI_64 0 -#define HTTC_BUF_REL_PRI_16 1 -#define HTTC_BUF_REL_PRI_8 2 -#define HTTC_BUF_REL_PRI_2 3 -#define HTTC_LIMIT_CLDT_CFG (1 << 15) -#define HTTC_LINT_EN (1 << 16) -#define HTTC_APIC_EXT_BRD_CST (1 << 17) -#define HTTC_APIC_EXT_ID (1 << 18) -#define HTTC_APIC_EXT_SPUR (1 << 19) -#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20) -#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21 -#define HTTC_DS_NP_REQ_LIMIT_MASK 3 -#define HTTC_DS_NP_REQ_LIMIT_NONE 0 -#define HTTC_DS_NP_REQ_LIMIT_1 1 -#define HTTC_DS_NP_REQ_LIMIT_4 2 -#define HTTC_DS_NP_REQ_LIMIT_8 3 - -/* Function 1 */ - -/* Function 2 */ - -/* Function 3 */ - - -/* Function 5 for FBDIMM */ -#define LinkConnected (1 << 0) -#define InitComplete (1 << 1) -#define NonCoherent (1 << 2) -#define ConnectionPending (1 << 4) - -#if CONFIG_MAX_PHYSICAL_CPUS > 8 - #if CONFIG_MAX_PHYSICAL_CPUS > 32 - #define NODE_NUMS 64 - #else - #define NODE_NUMS 32 - #endif -#else - #define NODE_NUMS 8 -#endif - -#ifdef __PRE_RAM__ -#if NODE_NUMS == 64 - #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else - #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif -#endif - -#endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/agesa/family15/chip.h b/src/northbridge/amd/agesa/family15/chip.h deleted file mode 100644 index fdc0c2bdea..0000000000 --- a/src/northbridge/amd/agesa/family15/chip.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _NB_AGESA_CHIP_H_ -#define _NB_AGESA_CHIP_H_ - -struct northbridge_amd_agesa_family15_config -{ - /* - * Here are a couple of examples of how this would be put into the - * devicetree.cb file. Note the array is oversized to support different - * configurations of server boards. - * This should be placed after the device pci 18.x statements. - * - * Example: AMD Dinar - * register "spdAddrLookup" = " - * { // Use 8-bit SPD addresses here - * { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 0 - Channel 0-3 - * { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 1 - Channel 0-3 - * }" - * Example: Tyan S8226 - * register "spdAddrLookup" = " - * { // Use 8-bit SPD addresses here - * { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 0 - * { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 1 - * }" - * - */ - - u8 spdAddrLookup[8][4][4]; -}; - -#endif diff --git a/src/northbridge/amd/agesa/family15/dimmSpd.c b/src/northbridge/amd/agesa/family15/dimmSpd.c deleted file mode 100644 index 2e33c0de56..0000000000 --- a/src/northbridge/amd/agesa/family15/dimmSpd.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci_def.h> -#include <device/device.h> -#include <stdlib.h> -#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ - -/* warning: Porting.h includes an open #pragma pack(1) */ -#include "Porting.h" -#include "AGESA.h" -#include "chip.h" - -#include <northbridge/amd/agesa/dimmSpd.h> - -/** - * Gets the SMBus address for an SPD from the array in devicetree.cb - * then read the SPD into the supplied buffer. - */ -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info) -{ - UINT8 spdAddress; - - DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2)); - if (dev == NULL) - return AGESA_ERROR; - - DEVTREE_CONST struct northbridge_amd_agesa_family15_config *config = dev->chip_info; - if (config == NULL) - return AGESA_ERROR; - - if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) - return AGESA_ERROR; - if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) - return AGESA_ERROR; - if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) - return AGESA_ERROR; - - spdAddress = config->spdAddrLookup - [info->SocketId][info->MemChannelId][info->DimmId]; - - if (spdAddress == 0) - return AGESA_ERROR; - - int err = smbus_readSpd(spdAddress, (void *) info->Buffer, 256); - if (err) - return AGESA_ERROR; - return AGESA_SUCCESS; -} diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c deleted file mode 100644 index 2ef652d45d..0000000000 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ /dev/null @@ -1,1053 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/acpigen.h> -#include <arch/io.h> -#include <stdint.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/hypertransport.h> -#include <stdlib.h> -#include <string.h> -#include <lib.h> -#include <cpu/cpu.h> -#include <cbmem.h> - -#include <cpu/x86/lapic.h> -#include <cpu/amd/mtrr.h> - -#include <Porting.h> -#include <AGESA.h> -#include <Options.h> -#include <Topology.h> - -#include <northbridge/amd/agesa/state_machine.h> -#include <northbridge/amd/agesa/agesa_helper.h> -#include "sb_cimx.h" - -#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) - -typedef struct dram_base_mask { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -} dram_base_mask_t; - -static unsigned node_nums; -static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; -static unsigned fx_devs = 0; - -static dram_base_mask_t get_dram_base_mask(u32 nodeid) -{ - device_t dev; - dram_base_mask_t d; - dev = __f1_dev[0]; - u32 temp; - temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] - d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too - temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp << 21; - temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] - d.mask |= (temp & 1); // enable bit - d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too - temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp << 21; - return d; -} - -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, - u32 io_min, u32 io_max) -{ - u32 i; - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - -static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) -{ - u32 i; - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit - for (i = 0; i < nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - -static device_t get_node_pci(u32 nodeid, u32 fn) -{ -#if MAX_NODE_NUMS + CONFIG_CDB >= 32 - if ((CONFIG_CDB + nodeid) < 32) { - return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); - } else { - return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); - } -#else - return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); -#endif -} - -static void get_fx_devs(void) -{ - int i; - for (i = 0; i < MAX_NODE_NUMS; i++) { - __f0_dev[i] = get_node_pci(i, 0); - __f1_dev[i] = get_node_pci(i, 1); - __f2_dev[i] = get_node_pci(i, 2); - __f4_dev[i] = get_node_pci(i, 4); - if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) - fx_devs = i+1; - } - if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { - die("Cannot find 0:0x18.[0|1]\n"); - } - printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); -} - -static u32 f1_read_config32(unsigned reg) -{ - if (fx_devs == 0) - get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); -} - -static void f1_write_config32(unsigned reg, u32 value) -{ - int i; - if (fx_devs == 0) - get_fx_devs(); - for (i = 0; i < fx_devs; i++) { - device_t dev; - dev = __f1_dev[i]; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } - } -} - -static u32 amdfam15_nodeid(device_t dev) -{ -#if MAX_NODE_NUMS == 64 - unsigned busn; - busn = dev->bus->secondary; - if (busn != CONFIG_CBB) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; - } else { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; - } - -#else - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; -#endif -} - -static void set_vga_enable_reg(u32 nodeid, u32 linkn) -{ - u32 val; - - val = 1 | (nodeid << 4) | (linkn << 12); - /* it will routing - * (1)mmio 0xa0000:0xbffff - * (2)io 0x3b0:0x3bb, 0x3c0:0x3df - */ - f1_write_config32(0xf4, val); - -} - -/** - * @return - * @retval 2 resoure does not exist, usable - * @retval 0 resource exists, not usable - * @retval 1 resource exist, resource has been allocated before - */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, - unsigned goal_link) -{ - struct resource *res; - unsigned nodeid, link = 0; - int result; - res = 0; - for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; - dev = __f0_dev[nodeid]; - if (!dev) - continue; - for (link = 0; !res && (link < 8); link++) { - res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); - } - } - result = 2; - if (res) { - result = 0; - if ((goal_link == (link - 1)) && - (goal_nodeid == (nodeid - 1)) && - (res->flags <= 1)) { - result = 1; - } - } - return result; -} - -static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) -{ - struct resource *resource; - u32 free_reg, reg; - resource = 0; - free_reg = 0; - for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { - int result; - result = reg_useable(reg, dev, nodeid, link); - if (result == 1) { - /* I have been allocated this one */ - break; - } - else if (result > 1) { - /* I have a free register pair */ - free_reg = reg; - } - } - if (reg > 0xd8) { - reg = free_reg; // if no free, the free_reg still be 0 - } - - resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); - - return resource; -} - -static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) -{ - struct resource *resource; - u32 free_reg, reg; - resource = 0; - free_reg = 0; - for (reg = 0x80; reg <= 0xb8; reg += 0x8) { - int result; - result = reg_useable(reg, dev, nodeid, link); - if (result == 1) { - /* I have been allocated this one */ - break; - } - else if (result > 1) { - /* I have a free register pair */ - free_reg = reg; - } - } - if (reg > 0xb8) { - reg = free_reg; - } - - resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); - return resource; -} - -static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) -{ - struct resource *resource; - - /* Initialize the io space constraints on the current bus */ - resource = amdfam15_find_iopair(dev, nodeid, link); - if (resource) { - u32 align; - align = log2(HT_IO_HOST_ALIGN); - resource->base = 0; - resource->size = 0; - resource->align = align; - resource->gran = align; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; - } - - /* Initialize the prefetchable memory constraints on the current bus */ - resource = amdfam15_find_mempair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - resource->flags |= IORESOURCE_BRIDGE; - } - - /* Initialize the memory constraints on the current bus */ - resource = amdfam15_find_mempair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; - } - -} - -static void nb_read_resources(device_t dev) -{ - u32 nodeid; - struct bus *link; - - nodeid = amdfam15_nodeid(dev); - for (link = dev->link_list; link; link = link->next) { - if (link->children) { - amdfam15_link_read_bases(dev, nodeid, link->link_num); - } - } - - /* - * This MMCONF resource must be reserved in the PCI domain. - * It is not honored by the coreboot resource allocator if it is in - * the CPU_CLUSTER. - */ - mmconf_resource(dev, 0xc0010058); -} - -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) -{ - resource_t rbase, rend; - unsigned reg, link_num; - char buf[50]; - - /* Make certain the resource has actually been set */ - if (!(resource->flags & IORESOURCE_ASSIGNED)) { - return; - } - - /* If I have already stored this resource don't worry about it */ - if (resource->flags & IORESOURCE_STORED) { - return; - } - - /* Only handle PCI memory and IO resources */ - if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) - return; - - /* Ensure I am actually looking at a resource of function 1 */ - if ((resource->index & 0xffff) < 0x1000) { - return; - } - /* Get the base address */ - rbase = resource->base; - - /* Get the limit (rounded up) */ - rend = resource_end(resource); - - /* Get the register and link */ - reg = resource->index & 0xfff; // 4k - link_num = IOINDEX_LINK(resource->index); - - if (resource->flags & IORESOURCE_IO) { - set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); - } - else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums);// [39:8] - } - resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof(buf), " <node %x link %x>", - nodeid, link_num); - report_resource_stored(dev, resource, buf); -} - -/** - * I tried to reuse the resource allocation code in set_resource() - * but it is too difficult to deal with the resource allocation magic. - */ - -static void create_vga_resource(device_t dev, unsigned nodeid) -{ - struct bus *link; - - /* find out which link the VGA card is connected, - * we only deal with the 'first' vga card */ - for (link = dev->link_list; link; link = link->next) { - if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) - extern device_t vga_pri; // the primary vga device, defined in device.c - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, - link->secondary,link->subordinate); - /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary) && - (vga_pri->bus->secondary <= link->subordinate)) -#endif - break; - } - } - - /* no VGA card installed */ - if (link == NULL) - return; - - printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); - set_vga_enable_reg(nodeid, sblink); -} - -static void nb_set_resources(device_t dev) -{ - unsigned nodeid; - struct bus *bus; - struct resource *res; - - /* Find the nodeid */ - nodeid = amdfam15_nodeid(dev); - - create_vga_resource(dev, nodeid); //TODO: do we need this? - - /* Set each resource we have found */ - for (res = dev->resource_list; res; res = res->next) { - set_resource(dev, res, nodeid); - } - - for (bus = dev->link_list; bus; bus = bus->next) { - if (bus->children) { - assign_resources(bus); - } - } -} - -static void scan_chains(device_t dev) -{ - unsigned nodeid; - struct bus *link; - device_t io_hub = NULL; - u32 next_unitid = 0x18; - - nodeid = amdfam15_nodeid(dev); - if (nodeid == 0) { - ASSERT(dev->bus->secondary == 0); - for (link = dev->link_list; link; link = link->next) { - if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */ - io_hub = link->children; - if (!io_hub || !io_hub->enabled) { - die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n"); - } - /* Now that nothing is overlapping it is safe to scan the children. */ - pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7); - } - } - } -} - - -static unsigned long acpi_fill_hest(acpi_hest_t *hest) -{ - void *addr, *current; - - /* Skip the HEST header. */ - current = (void *)(hest + 1); - - addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); - if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, - addr + 2, *(UINT16 *)addr - 2); - - addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); - if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, - addr + 2, *(UINT16 *)addr - 2); - - return (unsigned long)current; -} - -static void northbridge_fill_ssdt_generator(device_t device) -{ - msr_t msr; - char pscope[] = "\\_SB.PCI0"; - - acpigen_write_scope(pscope); - msr = rdmsr(TOP_MEM); - acpigen_write_name_dword("TOM1", msr.lo); - msr = rdmsr(TOP_MEM2); - /* - * Since XP only implements parts of ACPI 2.0, we can't use a qword - * here. - * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt - * slide 22ff. - * Shift value right by 20 bit to make it fit into 32bit, - * giving us 1MB granularity and a limit of almost 4Exabyte of memory. - */ - acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); - acpigen_pop_len(); -} - -static unsigned long agesa_write_acpi_tables(device_t device, - unsigned long current, - acpi_rsdp_t *rsdp) -{ - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *alib; - acpi_hest_t *hest; - - /* HEST */ - current = ALIGN(current, 8); - hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current, acpi_fill_hest); - acpi_add_table(rsdp, (void *)current); - current += ((acpi_header_t *)current)->length; - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); - if (srat != NULL) { - memcpy((void *)current, srat, srat->header.length); - srat = (acpi_srat_t *) current; - current += srat->header.length; - acpi_add_table(rsdp, srat); - } - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); - if (slit != NULL) { - memcpy((void *)current, slit, slit->header.length); - slit = (acpi_slit_t *) current; - current += slit->header.length; - acpi_add_table(rsdp, slit); - } - - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); - alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); - if (alib != NULL) { - memcpy((void *)current, alib, alib->length); - alib = (acpi_header_t *) current; - current += alib->length; - acpi_add_table(rsdp, (void *)alib); - } else { - printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); - } - - /* The DSDT needs additional work for the AGESA SSDT Pstate table */ - /* Keep the comment for a while. */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); - ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); - if (ssdt != NULL) { - memcpy((void *)current, ssdt, ssdt->length); - ssdt = (acpi_header_t *) current; - current += ssdt->length; - acpi_add_table(rsdp,ssdt); - } else { - printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); - } - - return current; -} - - -static struct device_operations northbridge_operations = { - .read_resources = nb_read_resources, - .set_resources = nb_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = DEVICE_NOOP, - .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, - .write_acpi_tables = agesa_write_acpi_tables, - .scan_bus = scan_chains, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver family15_northbridge __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT, -}; - -static const struct pci_driver family10_northbridge __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_10H_NB_HT, -}; - -struct chip_operations northbridge_amd_agesa_family15_ops = { - CHIP_NAME("AMD FAM15 Northbridge") - .enable_dev = 0, -}; - -static void domain_read_resources(device_t dev) -{ - unsigned reg; - - /* Find the already assigned resource pairs */ - get_fx_devs(); - for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { - u32 base, limit; - base = f1_read_config32(reg); - limit = f1_read_config32(reg + 0x04); - /* Is this register allocated? */ - if ((base & 3) != 0) { - unsigned nodeid, reg_link; - device_t reg_dev; - if (reg < 0xc0) { // mmio - nodeid = (limit & 0xf) + (base&0x30); - } else { // io - nodeid = (limit & 0xf) + ((base>>4)&0x30); - } - reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; - if (reg_dev) { - /* Reserve the resource */ - struct resource *res; - res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); - if (res) { - res->flags = 1; - } - } - } - } - /* FIXME: do we need to check extend conf space? - I don't believe that much preset value */ - - pci_domain_read_resources(dev); -} - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 -struct hw_mem_hole_info { - unsigned hole_startk; - int node_id; -}; -static struct hw_mem_hole_info get_hw_mem_hole_info(void) -{ - struct hw_mem_hole_info mem_hole; - int i; - mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; - mem_hole.node_id = -1; - for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; - u32 hole; - d = get_dram_base_mask(i); - if (!(d.mask & 1)) continue; // no memory on this node - hole = pci_read_config32(__f1_dev[i], 0xf0); - if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; - mem_hole.node_id = i; // record the node No with hole - break; // only one hole - } - } - - /* We need to double check if there is special set on base reg and limit reg - * are not continuous instead of hole, it will find out its hole_startk. - */ - if (mem_hole.node_id == -1) { - resource_t limitk_pri = 0; - for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; - resource_t base_k, limit_k; - d = get_dram_base_mask(i); - if (!(d.base & 1)) continue; - base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; - if (base_k > 4 *1024 * 1024) break; // don't need to go to check - if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G - mem_hole.node_id = i; - break; //only one hole - } - limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; - limitk_pri = limit_k; - } - } - return mem_hole; -} -#endif - -static void domain_set_resources(device_t dev) -{ - unsigned long mmio_basek; - u32 pci_tolm; - int i, idx; - struct bus *link; -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 - struct hw_mem_hole_info mem_hole; - u32 reset_memhole = 1; -#endif - - pci_tolm = 0xffffffffUL; - for (link = dev->link_list; link; link = link->next) { - pci_tolm = find_pci_tolm(link); - } - - // FIXME handle interleaved nodes. If you fix this here, please fix - // amdk8, too. - mmio_basek = pci_tolm >> 10; - /* Round mmio_basek to something the processor can support */ - mmio_basek &= ~((1 << 6) -1); - - // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M - // MMIO hole. If you fix this here, please fix amdk8, too. - /* Round the mmio hole to 64M */ - mmio_basek &= ~((64*1024) - 1); - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 - /* if the hw mem hole is already set in raminit stage, here we will compare - * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will - * use hole_basek as mmio_basek and we don't need to reset hole. - * otherwise We reset the hole to the mmio_basek - */ - - mem_hole = get_hw_mem_hole_info(); - - // Use hole_basek as mmio_basek, and we don't need to reset hole anymore - if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { - mmio_basek = mem_hole.hole_startk; - reset_memhole = 0; - } -#endif - - idx = 0x10; - for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; - resource_t basek, limitk, sizek; // 4 1T - - d = get_dram_base_mask(i); - - if (!(d.mask & 1)) continue; - basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; - - sizek = limitk - basek; - - /* see if we need a hole from 0xa0000 to 0xbffff */ - if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { - ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); - idx += 0x10; - basek = (8*64)+(16*16); - sizek = limitk - ((8*64)+(16*16)); - - } - - /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { - if (basek <= mmio_basek) { - unsigned pre_sizek; - pre_sizek = mmio_basek - basek; - if (pre_sizek > 0) { - ram_resource(dev, (idx | i), basek, pre_sizek); - idx += 0x10; - sizek -= pre_sizek; - } - basek = mmio_basek; - } - if ((basek + sizek) <= 4*1024*1024) { - sizek = 0; - } - else { - basek = 4*1024*1024; - sizek -= (4*1024*1024 - mmio_basek); - } - } - - ram_resource(dev, (idx | i), basek, sizek); - idx += 0x10; - printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", - i, mmio_basek, basek, limitk); - } - - add_uma_resource_below_tolm(dev, 7); - - for (link = dev->link_list; link; link = link->next) { - if (link->children) { - assign_resources(link); - } - } -} - -/* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */ -static void f15_pci_domain_scan_bus(device_t dev) -{ - struct bus *link = dev->link_list; - pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff); -} - -static struct device_operations pci_domain_ops = { - .read_resources = domain_read_resources, - .set_resources = domain_set_resources, - .init = DEVICE_NOOP, - .scan_bus = f15_pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, -}; - -static void sysconf_init(device_t dev) // first node -{ - sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 - node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] -} - -static void add_more_links(device_t dev, unsigned total_links) -{ - struct bus *link, *last = NULL; - int link_num; - - for (link = dev->link_list; link; link = link->next) - last = link; - - if (last) { - int links = total_links - last->link_num; - link_num = last->link_num; - if (links > 0) { - link = malloc(links*sizeof(*link)); - if (!link) - die("Couldn't allocate more links!\n"); - memset(link, 0, links*sizeof(*link)); - last->next = link; - } - } - else { - link_num = -1; - link = malloc(total_links*sizeof(*link)); - memset(link, 0, total_links*sizeof(*link)); - dev->link_list = link; - } - - for (link_num = link_num + 1; link_num < total_links; link_num++) { - link->link_num = link_num; - link->dev = dev; - link->next = link + 1; - last = link; - link = link->next; - } - last->next = NULL; -} - -static void cpu_bus_scan(device_t dev) -{ - struct bus *cpu_bus; - device_t dev_mc; -#if CONFIG_CBB - device_t pci_domain; -#endif - int i,j; - int coreid_bits; - int core_max = 0; - unsigned ApicIdCoreIdSize; - unsigned core_nums; - int siblings = 0; - unsigned int family; - -#if CONFIG_CBB - dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00 - if (dev_mc && dev_mc->bus) { - printk(BIOS_DEBUG, "%s found", dev_path(dev_mc)); - pci_domain = dev_mc->bus->dev; - if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) { - printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc)); - dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff - printk(BIOS_DEBUG, "%s",dev_path(dev_mc)); - } else { - printk(BIOS_DEBUG, " but it is not under pci_domain directly "); - } - printk(BIOS_DEBUG, "\n"); - } - dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); - if (!dev_mc) { - dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); - if (dev_mc && dev_mc->bus) { - printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc)); - pci_domain = dev_mc->bus->dev; - if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) { - if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) { - printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); - dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff - printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); - while (dev_mc) { - printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); - dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0); - printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); - dev_mc = dev_mc->sibling; - } - } - } - } - } -#endif - dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); - if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); - die(""); - } - sysconf_init(dev_mc); -#if CONFIG_CBB && (MAX_NODE_NUMS > 32) - if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe - if (pci_domain->link_list && !pci_domain->link_list->next) { - struct bus *new_link = new_link(pci_domain); - pci_domain->link_list->next = new_link; - new_link->link_num = 1; - new_link->dev = pci_domain; - new_link->children = 0; - printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain)); - } - pci_domain->link_list->next->secondary = CONFIG_CBB - 1; - } -#endif - - /* Get Max Number of cores(MNC) */ - coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12; - core_max = 1 << (coreid_bits & 0x000F); //mnc - - ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); - if (ApicIdCoreIdSize) { - core_nums = (1 << ApicIdCoreIdSize) - 1; - } else { - core_nums = 3; //quad core - } - - /* Find which cpus are present */ - cpu_bus = dev->link_list; - for (i = 0; i < node_nums; i++) { - device_t cdb_dev; - unsigned busn, devn; - struct bus *pbus; - - busn = CONFIG_CBB; - devn = CONFIG_CDB + i; - pbus = dev_mc->bus; -#if CONFIG_CBB && (MAX_NODE_NUMS > 32) - if (i >= 32) { - busn--; - devn -= 32; - pbus = pci_domain->link_list->next; - } -#endif - - /* Find the cpu's pci device */ - cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); - if (!cdb_dev) { - /* If I am probing things in a weird order - * ensure all of the cpu's pci devices are found. - */ - int fn; - for (fn = 0; fn <= 5; fn++) { //FBDIMM? - cdb_dev = pci_probe_dev(NULL, pbus, - PCI_DEVFN(devn, fn)); - } - cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); - } else { - /* Ok, We need to set the links for that device. - * otherwise the device under it will not be scanned - */ - add_more_links(cdb_dev, 8); - } - - family = cpuid_eax(1); - family = (family >> 20) & 0xFF; - if (family == 1) { //f10 - u32 dword; - cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); - dword = pci_read_config32(cdb_dev, 0xe8); - siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); - } else if (family == 6) {//f15 - cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5)); - if (cdb_dev && cdb_dev->enabled) { - siblings = pci_read_config32(cdb_dev, 0x84); - siblings &= 0xFF; - } - } else { - siblings = 0; //default one core - } - int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", - dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - - for (j = 0; j <= siblings; j++) { - u32 lapicid_start = 0; - - /* - * APIC ID calucation is tightly coupled with AGESA v5 code. - * This calculation MUST match the assignment calculation done - * in LocalApicInitializationAtEarly() function. - * And reference GetLocalApicIdForCore() - * - * Apply apic enumeration rules - * For systems with >= 16 APICs, put the IO-APICs at 0..n and - * put the local-APICs at m..z - * - * This is needed because many IO-APIC devices only have 4 bits - * for their APIC id and therefore must reside at 0..15 - */ - - u8 plat_num_io_apics = 3; /* FIXME */ - - if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { - lapicid_start = (plat_num_io_apics - 1) / core_max; - lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); - } -#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_G34) - u32 apic_id = (i / 2 * core_max) + j + lapicid_start + (i % 2 ? siblings + 1 : 0); -#else - u32 apic_id = (i * core_max) + j + lapicid_start; -#endif - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", - i, j, apic_id); - - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); - if (cpu) - amd_cpu_topology(cpu, i, j); - } //j - } -} - -static void cpu_bus_init(device_t dev) -{ - initialize_cpus(dev->link_list); -} - -static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, - .scan_bus = cpu_bus_scan, -}; - -static void root_complex_enable_dev(struct device *dev) -{ - static int done = 0; - - if (!done) { - setup_bsp_ramtop(); - done = 1; - } - - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - -struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = { - CHIP_NAME("AMD FAM15 Root Complex") - .enable_dev = root_complex_enable_dev, -}; diff --git a/src/northbridge/amd/agesa/family15/reset_test.h b/src/northbridge/amd/agesa/family15/reset_test.h deleted file mode 100644 index 61de4d9895..0000000000 --- a/src/northbridge/amd/agesa/family15/reset_test.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * copy from src/northbridge/amd/amdfam10/reset_test.c - */ - -#ifndef _RESET_TEST_H_ -#define _RESET_TEST_H_ - -#include <arch/io.h> -#include "amdfam10.h" /* NODE_PCI */ - -#define NODE_ID 0x60 -#define HT_INIT_CONTROL 0x6c -#define HTIC_ColdR_Detect (1 << 4) -#define HTIC_BIOSR_Detect (1 << 5) -#define HTIC_INIT_Detect (1 << 6) - -static inline u32 warm_reset_detect(u8 nodeid) -{ - u32 htic; - pci_devfn_t device; - device = NODE_PCI(nodeid, 0); - htic = pci_io_read_config32(device, HT_INIT_CONTROL); - return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); -} - -static inline void distinguish_cpu_resets(u8 nodeid) -{ - u32 htic; - pci_devfn_t device; - device = NODE_PCI(nodeid, 0); - htic = pci_io_read_config32(device, HT_INIT_CONTROL); - htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; - pci_io_write_config32(device, HT_INIT_CONTROL, htic); -} - -#endif diff --git a/src/northbridge/amd/agesa/family15/state_machine.c b/src/northbridge/amd/agesa/family15/state_machine.c deleted file mode 100644 index 83eadb0de0..0000000000 --- a/src/northbridge/amd/agesa/family15/state_machine.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Kyösti Mälkki - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "Porting.h" -#include "AGESA.h" - -#include <cbmem.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <northbridge/amd/agesa/agesa_helper.h> - -void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) -{ -} - -void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) -{ -} - -void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) -{ -} - -void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) -{ - backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); -} - -void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) -{ - OemInitResume(&Resume->S3DataBlock); -} - -void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) -{ -} - -void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) -{ - EmptyHeap(); -} - -void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) -{ -} - -void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) -{ - OemS3LateRestore(&S3Late->S3DataBlock); -} - -void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) -{ -} - -void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) -{ -} - -void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) -{ -} - -void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) -{ - OemS3Save(&S3Save->S3DataBlock); -} diff --git a/src/southbridge/amd/cimx/Kconfig b/src/southbridge/amd/cimx/Kconfig index cca87b0660..06544938a7 100644 --- a/src/southbridge/amd/cimx/Kconfig +++ b/src/southbridge/amd/cimx/Kconfig @@ -17,6 +17,5 @@ config AMD_SB_CIMX bool default n -source src/southbridge/amd/cimx/sb700/Kconfig source src/southbridge/amd/cimx/sb800/Kconfig source src/southbridge/amd/cimx/sb900/Kconfig diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc index b308e90190..b70d2feb7f 100644 --- a/src/southbridge/amd/cimx/Makefile.inc +++ b/src/southbridge/amd/cimx/Makefile.inc @@ -13,14 +13,11 @@ # GNU General Public License for more details. # -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900 -romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx_util.c romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c diff --git a/src/southbridge/amd/cimx/sb700/Amd.h b/src/southbridge/amd/cimx/sb700/Amd.h deleted file mode 100644 index 2e5702a061..0000000000 --- a/src/southbridge/amd/cimx/sb700/Amd.h +++ /dev/null @@ -1,359 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _AMD_H_ -#define _AMD_H_ - -// AGESA Types and Definitions -#ifndef NULL -#define NULL 0 -#endif - -#define LAST_ENTRY 0xFFFFFFFF -#define IOCF8 0xCF8 -#define IOCFC 0xCFC -#define IN -#define OUT - -#ifndef Int16FromChar -#define Int16FromChar(a,b) ((a) << 0 | (b) << 8) -#endif -#ifndef Int32FromChar -#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) -#endif - -#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D') - -typedef unsigned int AGESA_STATUS; - -#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) -#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) -#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) -#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) -#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) -#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) -#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) - -typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr); -typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr); -typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr); - -///This allocation type is used by the AmdCreateStruct entry point -typedef enum { - PreMemHeap = 0, ///< Create heap in cache. - PostMemDram, ///< Create heap in memory. - ByHost ///< Create heap by Host. -} ALLOCATION_METHOD; - -/// These width descriptors are used by the library function, and others, to specify the data size -typedef enum ACCESS_WIDTH { - AccessWidth8 = 1, ///< Access width is 8 bits. - AccessWidth16, ///< Access width is 16 bits. - AccessWidth32, ///< Access width is 32 bits. - AccessWidth64, ///< Access width is 64 bits. - - AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. - AccessS3SaveWidth16, ///< Save 16 bits data. - AccessS3SaveWidth32, ///< Save 32 bits data. - AccessS3SaveWidth64, ///< Save 64 bits data. -} ACCESS_WIDTH; - -// AGESA Structures - -/// The standard header for all AGESA services. -typedef struct _AMD_CONFIG_PARAMS { - IN unsigned int ImageBasePtr; ///< The AGESA Image base address. - IN unsigned int Func; ///< The service desired, @sa dispatch.h. - IN unsigned int AltImageBasePtr; ///< Alternate Image location - IN unsigned int PcieBasePtr; ///< PCIe MMIO Base address, if configured. - union { ///< Callback pointer - IN unsigned long long PlaceHolder; ///< Place holder - IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA - } CALLBACK; - IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use. -} AMD_CONFIG_PARAMS; - - -/// AGESA Binary module header structure -typedef struct _AMD_IMAGE_HEADER { - IN unsigned int Signature; ///< Binary Signature - IN signed char CreatorID[8]; ///< 8 characters ID - IN signed char Version[12]; ///< 12 characters version - IN unsigned int ModuleInfoOffset; ///< Offset of module - IN unsigned int EntryPointAddress; ///< Entry address - IN unsigned int ImageBase; ///< Image base - IN unsigned int RelocTableOffset; ///< Relocate Table offset - IN unsigned int ImageSize; ///< Size - IN unsigned short Checksum; ///< Checksum - IN unsigned char ImageType; ///< Type - IN unsigned char V_Reserved; ///< Reserved -} AMD_IMAGE_HEADER; - -/// AGESA Binary module header structure -typedef struct _AMD_MODULE_HEADER { - IN unsigned int ModuleHeaderSignature; ///< Module signature - IN signed char ModuleIdentifier[8]; ///< 8 characters ID - IN signed char ModuleVersion[12]; ///< 12 characters version - IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher - IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link -} AMD_MODULE_HEADER; - -#define FUNC_0 0 // bit-placed for PCI address creation -#define FUNC_1 1 -#define FUNC_2 2 -#define FUNC_3 3 -#define FUNC_4 4 -#define FUNC_5 5 -#define FUNC_6 6 -#define FUNC_7 7 - -// SBDFO - Segment Bus Device Function Offset -// 31:28 Segment (4-bits) -// 27:20 Bus (8-bits) -// 19:15 Device (5-bits) -// 14:12 Function (3-bits) -// 11:00 Offset (12-bits) - -#if 0 -#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \ - (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off))) -#endif -#define ILLEGAL_SBDFO 0xFFFFFFFF - -/// CPUID data received registers format -typedef struct _SB_CPUID_DATA { - IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX - IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX - IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX - IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX -} SB_CPUID_DATA; - -#define WARM_RESET 1 -#define COLD_RESET 2 // Cold reset -#define RESET_CPU 4 // Triggers a CPU reset - -/// HT frequency for external callbacks -typedef enum { - HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks - HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks - HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks - HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks - HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks - HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks - HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks - HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks - HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks - HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks - HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks - HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks - HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks - HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks - HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks - HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks -} HT_FREQUENCIES; - -#ifndef BIT0 -#define BIT0 0x0000000000000001ull -#endif -#ifndef BIT1 -#define BIT1 0x0000000000000002ull -#endif -#ifndef BIT2 -#define BIT2 0x0000000000000004ull -#endif -#ifndef BIT3 -#define BIT3 0x0000000000000008ull -#endif -#ifndef BIT4 -#define BIT4 0x0000000000000010ull -#endif -#ifndef BIT5 -#define BIT5 0x0000000000000020ull -#endif -#ifndef BIT6 -#define BIT6 0x0000000000000040ull -#endif -#ifndef BIT7 -#define BIT7 0x0000000000000080ull -#endif -#ifndef BIT8 -#define BIT8 0x0000000000000100ull -#endif -#ifndef BIT9 -#define BIT9 0x0000000000000200ull -#endif -#ifndef BIT10 -#define BIT10 0x0000000000000400ull -#endif -#ifndef BIT11 -#define BIT11 0x0000000000000800ull -#endif -#ifndef BIT12 -#define BIT12 0x0000000000001000ull -#endif -#ifndef BIT13 -#define BIT13 0x0000000000002000ull -#endif -#ifndef BIT14 -#define BIT14 0x0000000000004000ull -#endif -#ifndef BIT15 -#define BIT15 0x0000000000008000ull -#endif -#ifndef BIT16 -#define BIT16 0x0000000000010000ull -#endif -#ifndef BIT17 -#define BIT17 0x0000000000020000ull -#endif -#ifndef BIT18 -#define BIT18 0x0000000000040000ull -#endif -#ifndef BIT19 -#define BIT19 0x0000000000080000ull -#endif -#ifndef BIT20 -#define BIT20 0x0000000000100000ull -#endif -#ifndef BIT21 -#define BIT21 0x0000000000200000ull -#endif -#ifndef BIT22 -#define BIT22 0x0000000000400000ull -#endif -#ifndef BIT23 -#define BIT23 0x0000000000800000ull -#endif -#ifndef BIT24 -#define BIT24 0x0000000001000000ull -#endif -#ifndef BIT25 -#define BIT25 0x0000000002000000ull -#endif -#ifndef BIT26 -#define BIT26 0x0000000004000000ull -#endif -#ifndef BIT27 -#define BIT27 0x0000000008000000ull -#endif -#ifndef BIT28 -#define BIT28 0x0000000010000000ull -#endif -#ifndef BIT29 -#define BIT29 0x0000000020000000ull -#endif -#ifndef BIT30 -#define BIT30 0x0000000040000000ull -#endif -#ifndef BIT31 -#define BIT31 0x0000000080000000ull -#endif -#ifndef BIT32 -#define BIT32 0x0000000100000000ull -#endif -#ifndef BIT33 -#define BIT33 0x0000000200000000ull -#endif -#ifndef BIT34 -#define BIT34 0x0000000400000000ull -#endif -#ifndef BIT35 -#define BIT35 0x0000000800000000ull -#endif -#ifndef BIT36 -#define BIT36 0x0000001000000000ull -#endif -#ifndef BIT37 -#define BIT37 0x0000002000000000ull -#endif -#ifndef BIT38 -#define BIT38 0x0000004000000000ull -#endif -#ifndef BIT39 -#define BIT39 0x0000008000000000ull -#endif -#ifndef BIT40 -#define BIT40 0x0000010000000000ull -#endif -#ifndef BIT41 -#define BIT41 0x0000020000000000ull -#endif -#ifndef BIT42 -#define BIT42 0x0000040000000000ull -#endif -#ifndef BIT43 -#define BIT43 0x0000080000000000ull -#endif -#ifndef BIT44 -#define BIT44 0x0000100000000000ull -#endif -#ifndef BIT45 -#define BIT45 0x0000200000000000ull -#endif -#ifndef BIT46 -#define BIT46 0x0000400000000000ull -#endif -#ifndef BIT47 -#define BIT47 0x0000800000000000ull -#endif -#ifndef BIT48 -#define BIT48 0x0001000000000000ull -#endif -#ifndef BIT49 -#define BIT49 0x0002000000000000ull -#endif -#ifndef BIT50 -#define BIT50 0x0004000000000000ull -#endif -#ifndef BIT51 -#define BIT51 0x0008000000000000ull -#endif -#ifndef BIT52 -#define BIT52 0x0010000000000000ull -#endif -#ifndef BIT53 -#define BIT53 0x0020000000000000ull -#endif -#ifndef BIT54 -#define BIT54 0x0040000000000000ull -#endif -#ifndef BIT55 -#define BIT55 0x0080000000000000ull -#endif -#ifndef BIT56 -#define BIT56 0x0100000000000000ull -#endif -#ifndef BIT57 -#define BIT57 0x0200000000000000ull -#endif -#ifndef BIT58 -#define BIT58 0x0400000000000000ull -#endif -#ifndef BIT59 -#define BIT59 0x0800000000000000ull -#endif -#ifndef BIT60 -#define BIT60 0x1000000000000000ull -#endif -#ifndef BIT61 -#define BIT61 0x2000000000000000ull -#endif -#ifndef BIT62 -#define BIT62 0x4000000000000000ull -#endif -#ifndef BIT63 -#define BIT63 0x8000000000000000ull -#endif -#endif diff --git a/src/southbridge/amd/cimx/sb700/AmdSbLib.h b/src/southbridge/amd/cimx/sb700/AmdSbLib.h deleted file mode 100644 index 8dd796821c..0000000000 --- a/src/southbridge/amd/cimx/sb700/AmdSbLib.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _AMD_SB_LIB_H_ -#define _AMD_SB_LIB_H_ - -typedef signed char *va_list; -#ifndef _INTSIZEOF - #define _INTSIZEOF (n) ( (sizeof(n) + sizeof(UINTN) - 1) & ~(sizeof(UINTN) - 1) ) -#endif - -// Also support coding convention rules for var arg macros -#ifndef va_start - #define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) ) -#endif -#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) ) -#define va_end(ap) ( ap = (va_list)0 ) - - -#pragma pack (push, 1) - -#define IMAGE_ALIGN 32*1024 -#define NUM_IMAGE_LOCATION 32 - -//Entry Point Call -typedef void (*CIM_IMAGE_ENTRY) (void* pConfig); - -//Hook Call - -typedef struct _CIMFILEHEADER -{ - unsigned int AMDLogo; - unsigned long long CreatorID; - unsigned int Version1; - unsigned int Version2; - unsigned int Version3; - unsigned int ModuleInfoOffset; - unsigned int EntryPoint; - unsigned int ImageBase; - unsigned int RelocTableOffset; - unsigned int ImageSize; - unsigned short CheckSum; - unsigned char ImageType; - unsigned char Reserved2; -} CIMFILEHEADER; - -#pragma pack (pop) - -typedef enum -{ - AccWidthUint8 = 0, - AccWidthUint16, - AccWidthUint32, -} ACC_WIDTH; - -#define S3_SAVE 0x80 - -/** - * AmdSbDispatcher - Dispatch Southbridge function - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -AGESA_STATUS AmdSbDispatcher (IN void *pConfig); - -#endif diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig deleted file mode 100644 index 045dd70679..0000000000 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ /dev/null @@ -1,66 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SOUTHBRIDGE_AMD_CIMX_SB700 - bool - select IOAPIC - select HAVE_USBDEBUG_OPTIONS - select AMD_SB_CIMX - select HAVE_HARD_RESET - -if SOUTHBRIDGE_AMD_CIMX_SB700 -config SATA_CONTROLLER_MODE - hex - default 0x0 - help - 0x0 = Native IDE mode. - 0x1 = RAID mode. - 0x2 = AHCI mode. - 0x3 = Legacy IDE mode. - 0x4 = IDE->AHCI mode. - 0x5 = AHCI mode as 7804 ID (AMD driver). - 0x6 = IDE->AHCI mode as 7804 ID (AMD driver). - -config PCIB_ENABLE - bool - default n - help - n = Disable PCI Bridge Device 14 Function 4. - y = Enable PCI Bridge Device 14 Function 4. - -config ACPI_SCI_IRQ - hex - default 0x9 - help - Set SCI IRQ to 9. - -config EHCI_BAR - hex - default 0xfef00000 - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx/sb700/bootblock.c" - -config REDIRECT_SBCIMX_TRACE_TO_SERIAL - bool "Redirect AMD Southbridge CIMX Trace to serial console" - default n - help - This Option allows you to redirect the AMD Southbridge CIMX Trace - debug information to the serial console. - - Warning: Only enable this option when debuging or tracing AMD CIMX code. - -endif #SOUTHBRIDGE_AMD_CIMX_SB700 diff --git a/src/southbridge/amd/cimx/sb700/Makefile.inc b/src/southbridge/amd/cimx/sb700/Makefile.inc deleted file mode 100644 index 0b7614befe..0000000000 --- a/src/southbridge/amd/cimx/sb700/Makefile.inc +++ /dev/null @@ -1,34 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - - -# SB700 Platform Files - -romstage-y += early.c -romstage-y += smbus.c smbus_spd.c -romstage-y += reset.c -romstage-y += ramtop.c - -postcar-y += ramtop.c - -ramstage-y += late.c -ramstage-y += reset.c -ramstage-y += ramtop.c - -ramstage-y += smbus.c -ramstage-y += lpc.c - -romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ../../sb700/enable_usbdebug.c -ramstage-$(CONFIG_USBDEBUG) += ../../sb700/enable_usbdebug.c diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h deleted file mode 100644 index f83ec2375d..0000000000 --- a/src/southbridge/amd/cimx/sb700/Platform.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _AMD_SB_CIMx_PLATFORM_H_ -#define _AMD_SB_CIMx_PLATFORM_H_ - -#pragma pack(push,1) - -#include "cbtypes.h" -#include <console/console.h> -#include <commonlib/loglevel.h> -#ifdef NULL -#undef NULL -#endif -#define NULL 0 - -typedef struct _EXT_PCI_ADDR{ - UINT32 Reg :16; - UINT32 Func:3; - UINT32 Dev :5; - UINT32 Bus :8; -}EXT_PCI_ADDR; - - -typedef union _PCI_ADDR{ - UINT32 ADDR; - EXT_PCI_ADDR Addr; -}PCI_ADDR; - - -#ifdef CIM_DEBUG - -#if CIM_DEBUG & 2 -void TraceDebug( UINT32 Level, CHAR8 *Format, ...); -#define TRACE(Arguments) TraceDebug Arguments -#else -#define TRACE(Arguments) -#endif - -#if CIM_DEBUG & 1 -void TraceCode ( UINT32 Level, UINT32 Code); -#define TRACECODE(Arguments) TraceCode Arguments -#else -#define TRACECODE(Arguments) -#endif -#else - #ifdef TRACE - #undef TRACE - #endif - #if IS_ENABLED(CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL) - #define TRACE(Arguments) printk Arguments - #else - #define TRACE(Arguments) do {} while (0) - #endif - #define TRACECODE(Arguments) -#endif - -#define FIXUP_PTR(ptr) ptr - -#pragma pack(pop) - -#include "OEM.h" -#include "Amd.h" -#include "ACPILIB.h" -#include "SBTYPE.h" -#include "sbAMDLIB.h" -#include "SBCMNLIB.h" -#include "SB700.h" -#include "SBDEF.h" - -#define DMSG_SB_TRACE 0x02 - -#endif /* _AMD_SB_CIMx_PLATFORM_H_ */ diff --git a/src/southbridge/amd/cimx/sb700/amd_pci_int_defs.h b/src/southbridge/amd/cimx/sb700/amd_pci_int_defs.h deleted file mode 100644 index 989e72905d..0000000000 --- a/src/southbridge/amd/cimx/sb700/amd_pci_int_defs.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMD_PCI_INT_DEFS_H -#define AMD_PCI_INT_DEFS_H - -/* - * PIRQ and device routing - these define the index - * into the FCH PCI_INTR 0xC00/0xC01 interrupt - * routing table - */ -#define FCH_INT_TABLE_SIZE 0xD -#define PIRQ_NC 0x1F /* Not Used */ -#define PIRQ_A 0x00 /* INT A */ -#define PIRQ_B 0x01 /* INT B */ -#define PIRQ_C 0x02 /* INT C */ -#define PIRQ_D 0x03 /* INT D */ -#define PIRQ_ACPI 0x04 /* ACPI */ -#define PIRQ_SMBUS 0x05 /* SMBUS */ -/* Index 6, 7, 8 are all reserved */ -#define PIRQ_E 0x09 /* INT E */ -#define PIRQ_F 0x0A /* INT F */ -#define PIRQ_G 0x0B /* INT G */ -#define PIRQ_H 0x0C /* INT H */ - -#endif /* AMD_PCI_INT_DEFS_H */ diff --git a/src/southbridge/amd/cimx/sb700/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb700/amd_pci_int_types.h deleted file mode 100644 index 3fdc339f49..0000000000 --- a/src/southbridge/amd/cimx/sb700/amd_pci_int_types.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMD_PCI_INT_TYPES_H -#define AMD_PCI_INT_TYPES_H - -const char * intr_types[] = { - [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", - [0x04] = "ACPI\t", "SMBUS\t", "RSVD\t", "RSVD\t", "RSVD\t", - [0x09] = "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", -}; - -#endif /* AMD_PCI_INT_TYPES_H */ diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c deleted file mode 100644 index e10bb05ca9..0000000000 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <arch/io.h> - -static void sb700_enable_rom(void) -{ - u32 word; - u32 dword; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x14, 0x03); - /* SB700 LPC Bridge 0:20:3:44h. - * BIT6: Port Enable for serial port 0x3f8-0x3ff - * BIT29: Port Enable for KBC port 0x60 and 0x64 - * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 - */ - dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30); - /*Turn on all of LPC IO Port decode enable */ - dword = 0xffffffff; - pci_io_write_config32(dev, 0x44, dword); - - /* SB700 LPC Bridge 0:20:3:48h. - * BIT0: Port Enable for SuperIO 0x2E-0x2F - * BIT1: Port Enable for SuperIO 0x4E-0x4F - * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C) - * BIT6: Port Enable for RTC IO 0x70-0x73 - * BIT21: Port Enable for Port 0x80 - */ - dword = pci_io_read_config32(dev, 0x48); - dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21); - pci_io_write_config32(dev, 0x48, dword); - - /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */ - /* Set the 4MB enable bits */ - word = pci_io_read_config16(dev, 0x6c); - word = 0xFFC0; - pci_io_write_config16(dev, 0x6c, word); -} - -static void bootblock_southbridge_init(void) -{ - /* Setup the ROM access for 2M */ - sb700_enable_rom(); -} diff --git a/src/southbridge/amd/cimx/sb700/chip.h b/src/southbridge/amd/cimx/sb700/chip.h deleted file mode 100644 index 488d2167fe..0000000000 --- a/src/southbridge/amd/cimx/sb700/chip.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _CIMX_SB700_CHIP_H_ -#define _CIMX_SB700_CHIP_H_ - -/* - * configuration set in mainboard/devicetree.cb - * boot_switch_sata_ide: - * 0 -set SATA as primary, PATA(IDE) as secondary. - * 1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE, - * gpp_configuration - The configuration of General Purpose Port A/B/C/D - * 0(GPP_CFGMODE_X4000) -PortA Lanes[3:0] - * 2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2] - * 3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3 - * 4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 - */ -struct southbridge_amd_cimx_sb700_config -{ - u32 boot_switch_sata_ide : 1; - u8 gpp_configuration; -}; - -#endif /* _CIMX_SB700_CHIP_H_ */ diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c deleted file mode 100644 index d706a56b30..0000000000 --- a/src/southbridge/amd/cimx/sb700/early.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include "Platform.h" -#include "sb_cimx.h" -#include "sb700_cfg.h" /*sb700_cimx_config*/ -#include <console/console.h> -#include <commonlib/loglevel.h> -#include "smbus.h" - -/** - * @brief Get SouthBridge device number - * @param[in] bus target bus number - * @return southbridge device number - */ -u32 get_sbdn(u32 bus) -{ - pci_devfn_t dev; - - printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__); - dev = pci_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM), - bus); - - printk(BIOS_SPEW, "SB700 - Early.c - %s - End.\n", __func__); - return (dev >> 15) & 0x1f; -} - -/** - * @brief Enable A-Link Express Configuration DMA Access. - */ - -/** - * @brief South Bridge CIMx romstage entry, - * wrapper of sbPowerOnInit entry point. - */ -void sb_Poweron_Init(void) -{ - AMDSBCFG sb_early_cfg; - - printk(BIOS_SPEW, "cimx/sb700 early.c, %s() Start:\n", __func__); - /* Enable A-Link Base Address */ - //sb_enable_alink (); - - sb700_cimx_config(&sb_early_cfg); - sbPowerOnInit(&sb_early_cfg); - printk(BIOS_SPEW, "cimx/sb700 early.c, %s() End\n", __func__); -} - -void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) -{ - /* TODO: Now assume wio_index=0 */ - pci_devfn_t dev; - u8 reg8; - - //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ - dev = PCI_DEV(0, 0x14, 3); /* LPC Controller */ - pci_write_config32(dev, 0x64, base); - reg8 = pci_read_config8(dev, 0x48); - reg8 |= 1 << 2; - pci_write_config8(dev, 0x48, reg8); -} - -void sb7xx_51xx_disable_wideio(u8 wio_index) -{ - /* TODO: Now assume wio_index=0 */ - pci_devfn_t dev; - u8 reg8; - - //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ - dev = PCI_DEV(0, 0x14, 3); /* LPC Controller */ - pci_write_config32(dev, 0x64, 0); - reg8 = pci_read_config8(dev, 0x48); - reg8 &= ~(1 << 2); - pci_write_config8(dev, 0x48, reg8); -} diff --git a/src/southbridge/amd/cimx/sb700/gpio_oem.h b/src/southbridge/amd/cimx/sb700/gpio_oem.h deleted file mode 100644 index f28df0e474..0000000000 --- a/src/southbridge/amd/cimx/sb700/gpio_oem.h +++ /dev/null @@ -1,54 +0,0 @@ -#ifndef _CIMX_SB_GPIO_OEM_H_ -#define _CIMX_SB_GPIO_OEM_H_ - -/* Hudson-2 ACPI PmIO Space Define */ -#define SB_ACPI_BASE_ADDRESS 0x0400 -#define ACPI_MMIO_BASE 0xFED80000 -#define SB_CFG_BASE 0x000 // DWORD -#define GPIO_BASE 0x100 // BYTE -#define SMI_BASE 0x200 // DWORD -#define PMIO_BASE 0x300 // DWORD -#define PMIO2_BASE 0x400 // BYTE -#define BIOS_RAM_BASE 0x500 // BYTE -#define CMOS_RAM_BASE 0x600 // BYTE -#define CMOS_BASE 0x700 // BYTE -#define ASF_BASE 0x900 // DWORD -#define SMBUS_BASE 0xA00 // DWORD -#define WATCHDOG_BASE 0xB00 // ?? -#define HPET_BASE 0xC00 // DWORD -#define IOMUX_BASE 0xD00 // BYTE -#define MISC_BASE 0xE00 -#define SERIAL_DEBUG_BASE 0x1000 -#define GFX_DAC_BASE 0x1400 -#define CEC_BASE 0x1800 -#define XHCI_BASE 0x1C00 -#define ACPI_SMI_DATA_PORT 0xB1 -#define R_SB_ACPI_PM1_STATUS 0x00 -#define R_SB_ACPI_PM1_ENABLE 0x02 -#define R_SB_ACPI_PM_CONTROL 0x04 -#define R_SB_ACPI_EVENT_STATUS 0x20 -#define R_SB_ACPI_EVENT_ENABLE 0x24 -#define B_PWR_BTN_STATUS BIT8 -#define B_WAKEUP_STATUS BIT15 -#define B_SCI_EN BIT0 -#define SB_PM_INDEX_PORT 0xCD6 -#define SB_PM_DATA_PORT 0xCD7 -#define SB_PMIOA_REG24 0x24 // AcpiMmioEn -#define MmioAddress( BaseAddr, Register ) \ - ( (UINTN)BaseAddr + \ - (UINTN)(Register) \ - ) -#define Mmio32Ptr( BaseAddr, Register ) \ - ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) ) -#define Mmio32( BaseAddr, Register ) \ - *Mmio32Ptr( BaseAddr, Register ) - - -#define SB_GPIO_REG01 1 -#define SB_GPIO_REG02 2 -#define SB_GPIO_REG15 15 -#define SB_GPIO_REG24 24 -#define SB_GPIO_REG25 25 -#define SB_GPIO_REG27 27 - -#endif diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c deleted file mode 100644 index 051b563a24..0000000000 --- a/src/southbridge/amd/cimx/sb700/late.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <device/device.h> /* device_t */ -#include <device/pci.h> /* device_operations */ -#include <device/pci_ids.h> -#include <arch/ioapic.h> -#include <device/smbus.h> /* smbus_bus_operations */ -#include <pc80/mc146818rtc.h> -#include <pc80/i8254.h> -#include <pc80/i8259.h> -#include <console/console.h> /* printk */ -#include <device/pci_ehci.h> -#include <arch/acpi.h> -#include "lpc.h" /* lpc_read_resources */ -#include "Platform.h" /* Platform Specific Definitions */ -#include "sb_cimx.h" -#include "sb700_cfg.h" /* sb700 Cimx configuration */ -#include "chip.h" /* struct southbridge_amd_cimx_sb700_config */ - -static AMDSBCFG sb_late_cfg; //global, init in sb700_cimx_config -static AMDSBCFG *sb_config = &sb_late_cfg; - -/** - * @brief Entry point of Southbridge CIMx callout - * - * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) - * - * @param[in] func Southbridge CIMx Function ID. - * @param[in] data Southbridge Input Data. - * @param[in] config Southbridge configuration structure pointer. - * - */ -u32 sb700_callout_entry(u32 func, u32 data, void* config) -{ - u32 ret = 0; - - printk(BIOS_DEBUG, "SB700 - Late.c - sb700_callout_entry - Start.\n"); - printk(BIOS_DEBUG, "SB700 - Late.c - sb700_callout_entry - End.\n"); - return ret; -} - - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static void lpc_enable_resources(device_t dev) -{ - - printk(BIOS_SPEW, "SB700 - Late.c - %s - Start.\n", __func__); - pci_dev_enable_resources(dev); - lpc_enable_childrens_resources(dev); - printk(BIOS_SPEW, "SB700 - Late.c - %s - End.\n", __func__); -} - -static void lpc_init(device_t dev) -{ - printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n"); - - cmos_check_update_date(); - - /* Initialize the real time clock. - * The 0 argument tells cmos_init not to - * update CMOS unless it is invalid. - * 1 tells cmos_init to always initialize the CMOS. - */ - cmos_init(0); - - setup_i8259(); /* Initialize i8259 pic */ - setup_i8254(); /* Initialize i8254 timers */ - - printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - End.\n"); -} - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - - -static struct device_operations lpc_ops = { - .read_resources = lpc_read_resources, - .set_resources = lpc_set_resources, - .enable_resources = lpc_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) - .write_acpi_tables = acpi_write_hpet, -#endif - .init = lpc_init, - .scan_bus = scan_lpc_bus, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_LPC, -}; - - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver sata_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_SATA, //SATA IDE Mode 4390 -}; - -static struct device_operations usb_ops = { - .read_resources = pci_ehci_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -/* - * The pci id of usb ctrl 0 and 1 are the same. - */ -static const struct pci_driver usb_ohci123_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ -}; - -static const struct pci_driver usb_ohci3_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_USB_18_1, -}; - -static const struct pci_driver usb_ehci123_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ -}; - -static const struct pci_driver usb_ohci4_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_USB_20_5, /* OHCI-USB4 */ -}; - -static struct device_operations azalia_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver azalia_driver __pci_driver = { - .ops = &azalia_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_HDA, -}; - - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = 0, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB700_PCI, -}; - - -static void sb700_enable(device_t dev) -{ - struct southbridge_amd_cimx_sb700_config *sb_chip = - (struct southbridge_amd_cimx_sb700_config *)(dev->chip_info); - - printk(BIOS_DEBUG, "sb700_enable() "); - switch (dev->path.pci.devfn) { - case (0x11 << 3) | 0: /* 0:11.0 SATA */ - sb700_cimx_config(sb_config); - if (dev->enabled) { - sb_config->SataController = CIMX_OPTION_ENABLED; - if (1 == sb_chip->boot_switch_sata_ide) - sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. - else if (0 == sb_chip->boot_switch_sata_ide) - sb_config->SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. - } else { - sb_config->SataController = CIMX_OPTION_DISABLED; - } - break; - - case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ - case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ - case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ - case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ - break; - - case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ - { - uintptr_t ioapic_base; - printk(BIOS_DEBUG, "sm_init().\n"); - ioapic_base = IO_APIC_ADDR; - clear_ioapic((void *)ioapic_base); - /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ - if (CONFIG_MAX_CPUS >= 16) - setup_ioapic((void *)ioapic_base, 0); - else - setup_ioapic((void *)ioapic_base, CONFIG_MAX_CPUS + 1); - } - break; - - case (0x14 << 3) | 1: /* 0:14:1 IDE */ - break; - - case (0x14 << 3) | 2: /* 0:14:2 HDA */ - if (dev->enabled) { - if (AZALIA_DISABLE == sb_config->AzaliaController) { - sb_config->AzaliaController = AZALIA_AUTO; - } - printk(BIOS_DEBUG, "hda enabled\n"); - } else { - sb_config->AzaliaController = AZALIA_DISABLE; - printk(BIOS_DEBUG, "hda disabled\n"); - } - break; - - - case (0x14 << 3) | 3: /* 0:14:3 LPC */ - break; - - case (0x14 << 3) | 4: /* 0:14:4 PCI */ - break; - - case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ - /* call CIMX entry after last device enable */ - sb_Before_Pci_Init(); - break; - - default: - break; - } -} - -struct chip_operations southbridge_amd_cimx_sb700_ops = { - CHIP_NAME("ATI SB700") - .enable_dev = sb700_enable, -}; - -/** - * @brief SB Cimx entry point sbBeforePciInit wrapper - */ -void sb_Before_Pci_Init(void) -{ - printk(BIOS_SPEW, "sb700 %s Start\n", __func__); - /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */ - //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; - //AmdSbDispatcher(sb_config); - sbBeforePciInit(sb_config); - printk(BIOS_SPEW, "sb700 %s End\n", __func__); -} - -void sb_After_Pci_Init(void) -{ - printk(BIOS_SPEW, "sb700 %s Start\n", __func__); - /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */ - //sb_config->StdHeader.Func = SB_AFTER_PCI_INIT; - //AmdSbDispatcher(sb_config); - sbAfterPciInit(sb_config); - printk(BIOS_SPEW, "sb700 %s End\n", __func__); -} - -void sb_Late_Post(void) -{ - printk(BIOS_SPEW, "sb700 %s Start\n", __func__); - /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */ - //sb_config->StdHeader.Func = SB_LATE_POST_INIT; - //AmdSbDispatcher(sb_config); - sbLatePost(sb_config); - printk(BIOS_SPEW, "sb700 %s End\n", __func__); -} diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c deleted file mode 100644 index 5a8faa85b6..0000000000 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci.h> -#include "lpc.h" -#include <arch/io.h> -#include <arch/ioapic.h> -#include <console/console.h> /* printk */ -#include <cbmem.h> - -void lpc_read_resources(device_t dev) -{ - struct resource *res; - - printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__); - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - /* Add a memory resource for the SPI BAR. */ - fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE); - - res = new_resource(dev, 3); - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - compact_resources(dev); - printk(BIOS_SPEW, "SB700 - Lpc.c - %s - End.\n", __func__); -} - -void lpc_set_resources(struct device *dev) -{ - struct resource *res; - - printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__); - - /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ - res = find_resource(dev, 2); - pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE); - - pci_dev_set_resources(dev); - - printk(BIOS_SPEW, "SB700 - Lpc.c - %s - End.\n", __func__); -} - -/** - * @brief Enable resources for children devices - * - * @param dev the device whose children's resources are to be enabled - * - */ -void lpc_enable_childrens_resources(device_t dev) -{ - struct bus *link; - u32 reg, reg_x; - int var_num = 0; - u16 reg_var[3]; - - printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__); - reg = pci_read_config32(dev, 0x44); - reg_x = pci_read_config32(dev, 0x48); - - for (link = dev->link_list; link; link = link->next) { - device_t child; - for (child = link->children; child; - child = child->sibling) { - if (child->enabled - && (child->path.type == DEVICE_PATH_PNP)) { - struct resource *res; - for (res = child->resource_list; res; res = res->next) { - u32 base, end; /* don't need long long */ - if (!(res->flags & IORESOURCE_IO)) - continue; - base = res->base; - end = resource_end(res); -/* - printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n", - dev_path(child), base, end); -*/ - switch (base) { - case 0x60: /* KB */ - case 0x64: /* MS */ - reg |= (1 << 29); - break; - case 0x3f8: /* COM1 */ - reg |= (1 << 6); - break; - case 0x2f8: /* COM2 */ - reg |= (1 << 7); - break; - case 0x378: /* Parallel 1 */ - reg |= (1 << 0); - break; - case 0x3f0: /* FD0 */ - reg |= (1 << 26); - break; - case 0x220: /* Audio 0 */ - reg |= (1 << 8); - break; - case 0x300: /* Midi 0 */ - reg |= (1 << 18); - break; - case 0x400: - reg_x |= (1 << 16); - break; - case 0x480: - reg_x |= (1 << 17); - break; - case 0x500: - reg_x |= (1 << 18); - break; - case 0x580: - reg_x |= (1 << 19); - break; - case 0x4700: - reg_x |= (1 << 22); - break; - case 0xfd60: - reg_x |= (1 << 23); - break; - default: - if (var_num >= 3) - continue; /* only 3 var ; compact them ? */ - switch (var_num) { - case 0: - reg_x |= (1 << 2); - break; - case 1: - reg_x |= (1 << 24); - break; - case 2: - reg_x |= (1 << 25); - break; - } - reg_var[var_num++] = - base & 0xffff; - } - } - } - } - } - pci_write_config32(dev, 0x44, reg); - pci_write_config32(dev, 0x48, reg_x); - /* Set WideIO for as many IOs found (fall through is on purpose) */ - switch (var_num) { - case 2: - pci_write_config16(dev, 0x90, reg_var[2]); - case 1: - pci_write_config16(dev, 0x66, reg_var[1]); - case 0: - //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata - break; - } - printk(BIOS_SPEW, "SB700 - Lpc.c - %s - End.\n", __func__); -} diff --git a/src/southbridge/amd/cimx/sb700/lpc.h b/src/southbridge/amd/cimx/sb700/lpc.h deleted file mode 100644 index 6aea85e4da..0000000000 --- a/src/southbridge/amd/cimx/sb700/lpc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SB700_LPC_H_ -#define _SB700_LPC_H_ - - -#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 -#define SPI_ROM_ENABLE 0x02 -#define SPI_BASE_ADDRESS 0xFEC10000 - -void lpc_read_resources(device_t dev); -void lpc_set_resources(device_t dev); -void lpc_enable_childrens_resources(device_t dev); - -#endif diff --git a/src/southbridge/amd/cimx/sb700/ramtop.c b/src/southbridge/amd/cimx/sb700/ramtop.c deleted file mode 100644 index cbc4596f57..0000000000 --- a/src/southbridge/amd/cimx/sb700/ramtop.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <arch/io.h> -#include <cbmem.h> -#include <southbridge/amd/cimx/cimx_util.h> - -void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - u32 dword = ramtop; - int nvram_pos = 0xfc, i; - for (i = 0; i < 4; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - u32 xdata = 0; - int xnvram_pos = 0xfc, xi; - for (xi = 0; xi < 4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return xdata; -} diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c deleted file mode 100644 index 40e861c215..0000000000 --- a/src/southbridge/amd/cimx/sb700/reset.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - pci_devfn_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void do_hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void do_soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} diff --git a/src/southbridge/amd/cimx/sb700/sb_cimx.h b/src/southbridge/amd/cimx/sb700/sb_cimx.h deleted file mode 100644 index d64e07a5b3..0000000000 --- a/src/southbridge/amd/cimx/sb700/sb_cimx.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifndef _CIMX_H_ -#define _CIMX_H_ - -#define PM_INDEX 0xcd6 -#define PM_DATA 0xcd7 - -#define REV_SB700_A11 0x11 -#define REV_SB700_A12 0x12 - - -/** - * AMD South Bridge CIMx entry point wrapper - */ -void sb_Poweron_Init(void); -void sb_Before_Pci_Init(void); -void sb_After_Pci_Init(void); -void sb_Late_Post(void); - -void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base); -void sb7xx_51xx_disable_wideio(u8 wio_index); - -/** - * @brief Get SouthBridge device number, called by finalize_node_setup() - * @param[in] bus target bus number - * @return southbridge device number - */ -u32 get_sbdn(u32 bus); -#endif diff --git a/src/southbridge/amd/cimx/sb700/smbus.c b/src/southbridge/amd/cimx/sb700/smbus.c deleted file mode 100644 index 9d78cd06ee..0000000000 --- a/src/southbridge/amd/cimx/sb700/smbus.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <arch/io.h> -#include "smbus.h" -#include <console/console.h> /* printk */ - -static int smbus_wait_until_ready(u32 smbus_io_base) -{ - u32 loops; - - loops = SMBUS_TIMEOUT; - do { - u8 val; - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; - if (val == 0) { /* ready now */ - return 0; - } - outb(val, smbus_io_base + SMBHSTSTAT); - } while (--loops); - - return -2; /* time out */ -} - -static int smbus_wait_until_done(u32 smbus_io_base) -{ - u32 loops; - - loops = SMBUS_TIMEOUT; - do { - u8 val; - - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; /* mask off reserved bits */ - if (val & 0x1c) { - return -5; /* error */ - } - if (val == 0x02) { - outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */ - return 0; - } - } while (--loops); - - return -3; /* timeout */ -} - -int do_smbus_recv_byte(u32 smbus_io_base, u32 device) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; /* not ready */ - } - - printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - Start.\n"); - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTCMD); - - printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - End.\n"); - return byte; -} - -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; /* not ready */ - } - - printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - Start.\n"); - /* set the command... */ - outb(val, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - End.\n"); - return 0; -} - -int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; /* not ready */ - } - - printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - Start.\n"); - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTDAT0); - - printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - End.\n"); - return byte; -} - -int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; /* not ready */ - } - - printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - Start.\n"); - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); - - /* output value */ - outb(val, smbus_io_base + SMBHSTDAT0); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - End.\n"); - return 0; -} - -void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) -{ - u32 tmp; - - printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - Start.\n"); - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); - tmp = inl(AB_DATA); - /* rpr 4.2 - * For certain revisions of the chip, the ABCFG registers, - * with an address of 0x100NN (where 'N' is any hexadecimal - * number), require an extra programming step.*/ - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ - outl(tmp, AB_DATA); - outl(0, AB_INDX); - printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - End.\n"); -} - -void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) -{ - u32 tmp; - - printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - Start.\n"); - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); - tmp = inl(AB_DATA); - /* rpr 4.2 - * For certain revisions of the chip, the ABCFG registers, - * with an address of 0x100NN (where 'N' is any hexadecimal - * number), require an extra programming step.*/ - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ - outl(tmp, AB_DATA); - outl(0, AB_INDX); - printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - End.\n"); -} - -/* space = 0: AX_INDXC, AX_DATAC - * space = 1: AX_INDXP, AX_DATAP - */ -void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val) -{ - u32 tmp; - - printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ax_indx - Start.\n"); - /* read axindc to tmp */ - outl(space << 29 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(0, AB_INDX); - outl(space << 29 | space << 3 | 0x34, AB_INDX); - tmp = inl(AB_DATA); - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - /* write tmp */ - outl(space << 29 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(0, AB_INDX); - outl(space << 29 | space << 3 | 0x34, AB_INDX); - outl(tmp, AB_DATA); - outl(0, AB_INDX); - printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ax_indx - End.\n"); -} diff --git a/src/southbridge/amd/cimx/sb700/smbus.h b/src/southbridge/amd/cimx/sb700/smbus.h deleted file mode 100644 index fa6ce9f609..0000000000 --- a/src/southbridge/amd/cimx/sb700/smbus.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SB700_SMBUS_H_ -#define _SB700_SMBUS_H_ - -//#include <stdint.h> -#include <Platform.h> /* SMBUS0_BASE_ADDRESS */ -#ifndef SMBUS0_BASE_ADDRESS -#error SMBUS0_BASE_ADDRESS not define -#endif -#define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS - -#define SMBHSTSTAT 0x0 -#define SMBSLVSTAT 0x1 -#define SMBHSTCTRL 0x2 -#define SMBHSTCMD 0x3 -#define SMBHSTADDR 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBHSTBLKDAT 0x7 - -#define SMBSLVCTRL 0x8 -#define SMBSLVCMD_SHADOW 0x9 -#define SMBSLVEVT 0xa -#define SMBSLVDAT 0xc - -/*//SB00.H -#define AX_INDXC 0 -#define AX_INDXP 2 -#define AXCFG 4 -#define ABCFG 6 -#define RC_INDXC 1 -#define RC_INDXP 3 -*/ - -#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) - -/* Between 1-10 seconds, We should never timeout normally - * Longer than this is just painful when a timeout condition occurs. - */ -#define SMBUS_TIMEOUT (100*1000*10) - -#define abcfg_reg(reg, mask, val) \ - alink_ab_indx((ABCFG), (reg), (mask), (val)) -#define axcfg_reg(reg, mask, val) \ - alink_ab_indx((AXCFG), (reg), (mask), (val)) -#define axindxc_reg(reg, mask, val) \ - alink_ax_indx((AX_INDXC), (reg), (mask), (val)) -#define axindxp_reg(reg, mask, val) \ - alink_ax_indx((AX_INDXP), (reg), (mask), (val)) -#define rcindxc_reg(reg, port, mask, val) \ - alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val)) -#define rcindxp_reg(reg, port, mask, val) \ - alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) - -int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); -int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -int do_smbus_recv_byte(u32 smbus_io_base, u32 device); -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); -void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); -void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); -void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); - -#endif //_SB700_SMBUS_H_ diff --git a/src/southbridge/amd/cimx/sb700/smbus_spd.c b/src/southbridge/amd/cimx/sb700/smbus_spd.c deleted file mode 100644 index 73261c4ab4..0000000000 --- a/src/southbridge/amd/cimx/sb700/smbus_spd.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <device/pci_def.h> -#include <device/device.h> -#include <stdlib.h> -#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ - -/* warning: Porting.h includes an open #pragma pack(1) */ -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include "chip.h" -#include "smbus_spd.h" - -#include <northbridge/amd/agesa/dimmSpd.h> - -/* uncomment for source level debug - GDB gets really confused otherwise. */ -//#pragma optimize ("", off) - -/** - * Read a single SPD byte. If the first byte is being read, set up the - * address and offset. Following bytes auto increment. - */ -static UINT8 readSmbusByte(UINT16 iobase, UINT8 address, char *buffer, - int offset, int initial_offset) -{ - unsigned int status = -1; - UINT64 time_limit; - - /* clear status register */ - __outbyte(iobase + SMBUS_STATUS_REG, 0xFF); - __outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x1F); - - if (offset == initial_offset) { - /* Set offset, set slave address and start reading */ - __outbyte(iobase + SMBUS_CONTROL_REG, offset); - __outbyte(iobase + SMBUS_HOST_CMD_REG, address | READ_BIT); - __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_BYTE_COMMAND); - } else { - /* Issue read command - auto increments to next byte */ - __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_COMMAND); - } - /* time limit to avoid hanging for unexpected error status */ - time_limit = __rdtsc() + MAX_READ_TSC_COUNT; - while (__rdtsc() <= time_limit) { - status = __inbyte(iobase + SMBUS_STATUS_REG); - if ((status & SMBUS_INTERRUPT_MASK) == 0) - continue; /* SMBusInterrupt not set, keep waiting */ - if ((status & HOSTBUSY_MASK) != 0) - continue; /* HostBusy set, keep waiting */ - break; - } - - if (status != STATUS__COMPLETED_SUCCESSFULLY) - return AGESA_ERROR; - - buffer[0] = __inbyte(iobase + SMBUS_DATA0_REG); - return AGESA_SUCCESS; -} - -/** - * Write a single smbus byte. - */ -UINT8 writeSmbusByte(UINT16 iobase, UINT8 address, UINT8 buffer, - int offset) -{ - unsigned int status = -1; - UINT64 time_limit; - - /* clear status register */ - __outbyte(iobase + SMBUS_STATUS_REG, 0xFF); - __outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x1F); - - /* set offset, set slave address, set data and start writing */ - __outbyte(iobase + SMBUS_CONTROL_REG, offset); - __outbyte(iobase + SMBUS_HOST_CMD_REG, address & (~READ_BIT)); - __outbyte(iobase + SMBUS_DATA0_REG, buffer); - __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_WRITE_BYTE_COMMAND); - - /* time limit to avoid hanging for unexpected error status */ - time_limit = __rdtsc() + MAX_READ_TSC_COUNT; - while (__rdtsc() <= time_limit) { - status = __inbyte(iobase + SMBUS_STATUS_REG); - if ((status & SMBUS_INTERRUPT_MASK) == 0) - continue; /* SMBusInterrupt not set, keep waiting */ - if ((status & HOSTBUSY_MASK) != 0) - continue; /* HostBusy set, keep waiting */ - break; - } - - if (status != STATUS__COMPLETED_SUCCESSFULLY) - return AGESA_ERROR; - - return AGESA_SUCCESS; -} - -static void setupFch(UINT16 ioBase) -{ - AMD_CONFIG_PARAMS StdHeader; - UINT32 PciData32; - UINT8 PciData8; - PCI_ADDR PciAddress; - - /* Set SMBus MMIO. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90); - PciData32 = (ioBase & 0xFFFFFFF0) | BIT0; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader); - - /* Enable SMBus MMIO. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2); - LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); - PciData8 |= BIT0; - LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader); - - /* Set SMBus clock to 400 KHz */ - __outbyte(ioBase + SMBUS_CLOCK_REG, SMBUS_FREQUENCY_CONST / 400000); -} - -/** - * Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Reads 128 bytes in 7-8 ms at 400 KHz. - */ -static UINT8 readspd(UINT16 iobase, UINT8 SmbusSlaveAddress, char *buffer, - UINT16 count) -{ - UINT16 index; - UINT8 status; - UINT8 initial_offset = 0; - - setupFch(iobase); - - for (index = initial_offset; index < count; index++) { - status = readSmbusByte(iobase, SmbusSlaveAddress, &buffer[index], index, - initial_offset); - if (status != AGESA_SUCCESS) - return status; - } - - return status; -} - -int smbus_readSpd(int spdAddress, char *buf, size_t len) -{ - int ioBase = SMBUS0_BASE_ADDRESS; - setupFch (ioBase); - return readspd (ioBase, spdAddress, buf, len); -} diff --git a/src/southbridge/amd/cimx/sb700/smbus_spd.h b/src/southbridge/amd/cimx/sb700/smbus_spd.h deleted file mode 100644 index e2f6c216b8..0000000000 --- a/src/southbridge/amd/cimx/sb700/smbus_spd.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SMBUS_SPD_H_ -#define _SMBUS_SPD_H_ - -#define READ_BIT 0x01 - -#define SMBUS_INTERRUPT_MASK 0x02 -#define HOSTBUSY_MASK 0x01 - -#define SMBUS_READ_BYTE_COMMAND 0x48 -#define SMBUS_READ_COMMAND 0x44 - -#define SMBUS_WRITE_BYTE_COMMAND 0x48 - -#define MAX_READ_TSC_COUNT (2000000000 / 10) - -#define PMIO_INDEX_REG 0xCD6 -#define PMIO_DATA_REG 0xCD7 - -#define SMBUS_BAR_LOW_BYTE 0x2C -#define SMBUS_BAR_HIGH_BYTE 0x2D - -#define SMBUS_STATUS_REG 0x00 -#define SMBUS_SLAVE_STATUS_REG 0x01 -#define SMBUS_COMMAND_REG 0x02 -#define SMBUS_CONTROL_REG 0x03 -#define SMBUS_HOST_CMD_REG 0x04 -#define SMBUS_DATA0_REG 0x05 -#define SMBUS_CLOCK_REG 0x0E - -#define STATUS__COMPLETED_SUCCESSFULLY 0x02 - -#define SMBUS_FREQUENCY_CONST 66000000 / 4 - -/* - * This function prototype is only used by the AMD Dinar mainboard. The SMBus - * write is used to select which socket's SPD will be read by the subsequent - * SPD read call. This function is being placed in the F15 wrapper code with - * the other SPD read functions because the next step of the SPD read clean-up - * will be to move the SMBus read/write functions into the southbridge to make - * them more generic. Having the writeSmbusByte() function in the same file as - * the readSmbusByte() function will ensure that the writeSmbusByte() function - * is not overlooked. - */ -UINT8 writeSmbusByte(UINT16 iobase, UINT8 address, UINT8 buffer, int offset); - -#endif diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc index 107b2f66b4..92bb1493aa 100644 --- a/src/southbridge/amd/common/Makefile.inc +++ b/src/southbridge/amd/common/Makefile.inc @@ -1,4 +1,3 @@ -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) += amd_pci_util.c diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index 018cd53eb3..24110a7909 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -1,6 +1,5 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += f12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += f14 -subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += f15 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += f15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += f16kb diff --git a/src/vendorcode/amd/cimx/Makefile.inc b/src/vendorcode/amd/cimx/Makefile.inc index 7051ea2330..36223127ec 100644 --- a/src/vendorcode/amd/cimx/Makefile.inc +++ b/src/vendorcode/amd/cimx/Makefile.inc @@ -1,4 +1,3 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900 subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890 |