diff options
| author | Martin Roth <martinroth@chromium.org> | 2021-08-09 10:37:45 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-27 02:51:05 +0000 |
| commit | c47155da3a8f971ad4e4f17886b848f8a8a2fa41 (patch) | |
| tree | de866caad313fdb477d38f58490ca4cd11bc14da | |
| parent | 3412d28b454202a945cbac140677a29753cfcc5b (diff) | |
soc/amd/common/block/spi: Add SPI config to Kconfig
Currently, The SPI speed/mode configuration is split between Kconfig
and devicetree. We'd like to have everything in one place. Since we
need the fast-read speed and the mode available in the Makefile to build
the AMD EFS table, we currently need it in Kconfig. Move all of the
settings to Kconfig and remove them from Devicetree in a later commit.
BUG=b:195943311
TEST=boot majolica & guybrush, verify spi settings
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8f29e49e886bd99b39172905e21bfd392c6c10e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56884
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/common/block/spi/Kconfig | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig index eb5412fd29..8853f6f275 100644 --- a/src/soc/amd/common/block/spi/Kconfig +++ b/src/soc/amd/common/block/spi/Kconfig @@ -17,6 +17,7 @@ config SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST config EFS_SPI_READ_MODE int range 0 7 + default 0 if EM100 default 2 help SPI read mode to be programmed by the PSP. @@ -35,6 +36,7 @@ config EFS_SPI_READ_MODE config EFS_SPI_SPEED int range 0 5 + default 3 if EM100 default 0 help SPI Fast Speed to be programmed by the PSP. @@ -56,3 +58,45 @@ config EFS_SPI_MICRON_FLAG 0: Board does not use Micron parts 1: Board always uses Micron parts 2: Micron parts are optional + +config NORMAL_READ_SPI_SPEED + int + range 0 5 + default 3 if EM100 + default 1 + help + SPI Normal Speed to be programmed by coreboot. + 0: 66.66Mhz + 1: 33.33MHz + 2: 22.22MHz + 3: 16.66MHz + 4: 100MHz + 5: 800KHz + +config ALT_SPI_SPEED + int + range 0 5 + default 3 if EM100 + default 0 + help + SPI ALT Speed to be programmed by coreboot. + 0: 66.66Mhz + 1: 33.33MHz + 2: 22.22MHz + 3: 16.66MHz + 4: 100MHz + 5: 800KHz + +config TPM_SPI_SPEED + int + range 0 5 + default 3 if EM100 + default 0 + help + SPI TPM Speed to be programmed by coreboot. + 0: 66.66Mhz + 1: 33.33MHz + 2: 22.22MHz + 3: 16.66MHz + 4: 100MHz + 5: 800KHz |