soc/intel/skylake: Update systemagent.asl to ASL2.0

This change updates systemagent.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for soraka.

Change-Id: If8d8dd50af9a79d30f54e98f7f2fe7ce49188763
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 21 insertions, 21 deletions

diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl
index 6ea782b23f..b2e691ddf8 100644
--- a/src/soc/intel/skylake/acpi/systemagent.asl
+++ b/src/soc/intel/skylake/acpi/systemagent.asl
@@ -188,30 +188,30 @@ Method (_CRS, 0, Serialized)
 	 * Fix up PCI memory region
 	 * Start with Top of Lower Usable DRAM
 	 */
-	Store (\_SB.PCI0.MCHC.TLUD, Local0)
-	Store (\_SB.PCI0.MCHC.MEBA, Local1)
+	Local0 = \_SB.PCI0.MCHC.TLUD
+	Local1 = \_SB.PCI0.MCHC.MEBA
 
 	/*  Check if ME base is equal */
-	If (LEqual (Local0, Local1)) {
+	If (Local0 == Local1) {
 		/*  Use Top Of Memory instead */
-		Store (\_SB.PCI0.MCHC.TOM, Local0)
+		Local0 = \_SB.PCI0.MCHC.TOM
 	}
 
 	Store (Local0, PMIN)
-	Add (Subtract (PMAX, PMIN), 1, PLEN)
+	PLEN = (PMAX - PMIN) + 1
 
 	/* Patch PM02 range based on Memory Size */
-	If (LEqual (A4GS, 0)) {
+	If (A4GS == 0) {
 		CreateQwordField (MCRS, PM02._LEN, MSEN)
-		Store (0, MSEN)
+		MSEN = 0
 	} Else {
 		CreateQwordField (MCRS, PM02._MIN, MMIN)
 		CreateQwordField (MCRS, PM02._MAX, MMAX)
 		CreateQwordField (MCRS, PM02._LEN, MLEN)
 		/* Set 64bit MMIO resource base and length */
-		Store (A4GS, MLEN)
-		Store (A4GB, MMIN)
-		Subtract (Add (MMIN, MLEN), 1, MMAX)
+		MLEN = A4GS
+		MMIN = A4GB
+		MMAX = (MMIN + MLEN) - 1
 	}
 
 	Return (MCRS)
@@ -220,35 +220,35 @@ Method (_CRS, 0, Serialized)
 /* Get MCH BAR */
 Method (GMHB, 0, Serialized)
 {
-	ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, Local0)
+	Local0 = \_SB.PCI0.MCHC.MHBR << 15
 	Return (Local0)
 }
 
 /* Get EP BAR */
 Method (GEPB, 0, Serialized)
 {
-	ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, Local0)
+	Local0 = \_SB.PCI0.MCHC.EPBR << 12
 	Return (Local0)
 }
 
 /* Get PCIe BAR */
 Method (GPCB, 0, Serialized)
 {
-	ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, Local0)
+	Local0 = \_SB.PCI0.MCHC.PXBR << 26
 	Return (Local0)
 }
 
 /* Get PCIe Length */
 Method (GPCL, 0, Serialized)
 {
-	ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0)
+	Local0 = 0x10000000 >> \_SB.PCI0.MCHC.PXSZ
 	Return (Local0)
 }
 
 /* Get DMI BAR */
 Method (GDMB, 0, Serialized)
 {
-	ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, Local0)
+	Local0 = \_SB.PCI0.MCHC.DIBR << 12
 	Return (Local0)
 }
 
@@ -296,22 +296,22 @@ Device (PDRC)
 		})
 
 		CreateDwordField (BUF0, MCHB._BAS, MBR0)
-		Store (\_SB.PCI0.GMHB (), MBR0)
+		MBR0 = \_SB.PCI0.GMHB ()
 
 		CreateDwordField (BUF0, DMIB._BAS, DBR0)
-		Store (\_SB.PCI0.GDMB (), DBR0)
+		DBR0 = \_SB.PCI0.GDMB ()
 
 		CreateDwordField (BUF0, EGPB._BAS, EBR0)
-		Store (\_SB.PCI0.GEPB (), EBR0)
+		EBR0 = \_SB.PCI0.GEPB ()
 
 		CreateDwordField (BUF0, PCIX._BAS, XBR0)
-		Store (\_SB.PCI0.GPCB (), XBR0)
+		XBR0 = \_SB.PCI0.GPCB ()
 
 		CreateDwordField (BUF0, PCIX._LEN, XSZ0)
-		Store (\_SB.PCI0.GPCL (), XSZ0)
+		XSZ0 = \_SB.PCI0.GPCL ()
 
 		CreateDwordField (BUF0, FIOH._BAS, FBR0)
-		Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0)
+		FBR0 = 0x100000000 - CONFIG_ROM_SIZE
 
 		Return (BUF0)
 	}