diff options
| author | Konstantin Aladyshev <aladyshev@nicevt.ru> | 2013-03-06 22:13:42 +0400 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2013-03-08 07:30:06 +0100 |
| commit | c2f2bd0a6d00a7f8df4005f148f67373db6d26d6 (patch) | |
| tree | 385ec9b00e6ab35bf6ad36d0b1f4bc3618581f6f | |
| parent | 4c1e906e36252db3361d7df4c3764b352f53e2f3 (diff) | |
AGESA: Fix CR0_PE bit define
AGESA code has wrong definition of CR0_PE bit (1 instead of 0).
PE [Protected Mode Enable] is 0 bit in CR0 register
(If PE=1, system is in protected mode, else system is in real mode)
Bit 1 is MP [Monitor co-processor]
(Controls interaction of WAIT/FWAIT instructions with TS flag in CR0)
System uses CR0_PE define, but I didn't expect any consequences because of this bug.
Change-Id: I54d9a8c0ee3af0a2e0267777036f227a9e05f3e1
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2591
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
| -rwxr-xr-x | src/vendorcode/amd/agesa/f10/gcccar.inc | 2 | ||||
| -rwxr-xr-x | src/vendorcode/amd/agesa/f12/gcccar.inc | 2 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f14/cpcar.inc | 2 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f14/gcccar.inc | 2 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/gcccar.inc | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc index 70988b89b8..61a8d3ee71 100755 --- a/src/vendorcode/amd/agesa/f10/gcccar.inc +++ b/src/vendorcode/amd/agesa/f10/gcccar.inc @@ -100,7 +100,7 @@ CU_CFG3 = 0x0C001102B /* Combined Unit Configuration COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ -CR0_PE = 1 # Protection Enable +CR0_PE = 0 # Protection Enable CR0_NW = 29 # Not Write-through CR0_CD = 30 # Cache Disable CR0_PG = 31 # Paging Enable diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc index e7f2ec7bd7..d7da81d1fc 100755 --- a/src/vendorcode/amd/agesa/f12/gcccar.inc +++ b/src/vendorcode/amd/agesa/f12/gcccar.inc @@ -100,7 +100,7 @@ CU_CFG3 = 0x0C001102B /* Combined Unit Configuration COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ -CR0_PE = 1 # Protection Enable +CR0_PE = 0 # Protection Enable CR0_NW = 29 # Not Write-through CR0_CD = 30 # Cache Disable CR0_PG = 31 # Paging Enable diff --git a/src/vendorcode/amd/agesa/f14/cpcar.inc b/src/vendorcode/amd/agesa/f14/cpcar.inc index b9aaa91a7b..ce33f62402 100644 --- a/src/vendorcode/amd/agesa/f14/cpcar.inc +++ b/src/vendorcode/amd/agesa/f14/cpcar.inc @@ -97,7 +97,7 @@ CU_CFG3 EQU 0C001102Bh ; Combined Unit Configuration 3 COMBINE_CR0_CD EQU 49 ; Combine CR0.CD for both cores of a compute unit -CR0_PE EQU 1 ; Protection Enable +CR0_PE EQU 0 ; Protection Enable CR0_NW EQU 29 ; Not Write-through CR0_CD EQU 30 ; Cache Disable CR0_PG EQU 31 ; Paging Enable diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index fc1b1adaa4..703734479b 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -114,7 +114,7 @@ CU_CFG3 = 0x0C001102B /* Combined Unit Configuration COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ -CR0_PE = 1 # Protection Enable +CR0_PE = 0 # Protection Enable CR0_NW = 29 # Not Write-through CR0_CD = 30 # Cache Disable CR0_PG = 31 # Paging Enable diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc index 3627da6df3..b20c77e575 100644 --- a/src/vendorcode/amd/agesa/f15/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15/gcccar.inc @@ -115,7 +115,7 @@ CU_CFG3 = 0x0C001102B /* Combined Unit Configuration COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ -CR0_PE = 1 # Protection Enable +CR0_PE = 0 # Protection Enable CR0_NW = 29 # Not Write-through CR0_CD = 30 # Cache Disable CR0_PG = 31 # Paging Enable |