mb/google/myst: Update DXIO descriptor definition

Update definition to be more intuitive and extensible.
Port descriptors will be defined as individual entities and added
to the descriptor list as such.

BUG=b:281059446
TEST=builds

Change-Id: I23ddd11b7e4da35a0d81299aa648f928e81ea24e
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79626
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 112 insertions, 85 deletions

diff --git a/src/mainboard/google/myst/port_descriptors.c b/src/mainboard/google/myst/port_descriptors.c
index 7c3ddb3825..664b440a32 100644
--- a/src/mainboard/google/myst/port_descriptors.c
+++ b/src/mainboard/google/myst/port_descriptors.c
@@ -2,73 +2,10 @@
 
 #include <baseboard/variants.h>
 #include <console/console.h>
-#include <fw_config.h>
 #include <gpio.h>
 #include <soc/platform_descriptors.h>
 #include <types.h>
 
-static fsp_dxio_descriptor myst_dxio_descriptors[] = {
-	[DXIO_WWAN] = {
-		.engine_type = UNUSED_ENGINE,
-		.port_present = true,
-		.start_lane = 13,
-		.end_lane = 13,
-		.device_number = PCI_SLOT(WWAN_DEVFN),
-		.function_number = PCI_FUNC(WWAN_DEVFN),
-		.link_speed_capability = GEN3,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ2,
-	},
-	[DXIO_WLAN] = {
-		.engine_type = PCIE_ENGINE,
-		.port_present = true,
-		.start_lane = 14,
-		.end_lane = 14,
-		.device_number = PCI_SLOT(WLAN_DEVFN),
-		.function_number = PCI_FUNC(WLAN_DEVFN),
-		.link_speed_capability = GEN3,
-		.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ0,
-	},
-	[DXIO_SD] = {
-		.engine_type = PCIE_ENGINE,
-		.port_present = true,
-		.start_lane = 15,
-		.end_lane = 15,
-		.device_number = PCI_SLOT(SD_DEVFN),
-		.function_number = PCI_FUNC(SD_DEVFN),
-		.link_speed_capability = GEN1,
-		.turn_off_unused_lanes = true,
-		.link_hotplug = HOTPLUG_ENHANCED,
-		.clk_req = CLK_REQ1,
-	},
-	[DXIO_STORAGE] = { 0 },
-};
-
-static const fsp_dxio_descriptor emmc_descriptor = {
-	.engine_type = PCIE_ENGINE,
-	.port_present = true,
-	.start_lane = 16,
-	.end_lane = 16,
-	.device_number = PCI_SLOT(NVME_DEVFN),
-	.function_number = PCI_FUNC(NVME_DEVFN),
-	.link_speed_capability = GEN_MAX,
-	.turn_off_unused_lanes = true,
-	.clk_req = CLK_REQ3,
-};
-
-static const fsp_dxio_descriptor nvme_descriptor = {
-	.engine_type = PCIE_ENGINE,
-	.port_present = true,
-	.start_lane = 16,
-	.end_lane = 19,
-	.device_number = PCI_SLOT(NVME_DEVFN),
-	.function_number = PCI_FUNC(NVME_DEVFN),
-	.link_speed_capability = GEN_MAX,
-	.turn_off_unused_lanes = true,
-	.clk_req = CLK_REQ3,
-};
-
 static const fsp_ddi_descriptor myst_ddi_descriptors[] = {
 	{ /* DDI0 - eDP */
 		.connector_type = DDI_EDP,
@@ -101,16 +38,7 @@ void mainboard_get_dxio_ddi_descriptors(
 		const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
 		const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
 {
-	if (fw_config_is_provisioned() && fw_config_probe(FW_CONFIG(STORAGE, NVME))) {
-		printk(BIOS_DEBUG, "Enabling NVMe.\n");
-		myst_dxio_descriptors[DXIO_STORAGE] = nvme_descriptor;
-	} else {
-		printk(BIOS_DEBUG, "Enabling eMMC.\n");
-		myst_dxio_descriptors[DXIO_STORAGE] = emmc_descriptor;
-	}
-
-	*dxio_descs = myst_dxio_descriptors;
-	*dxio_num = ARRAY_SIZE(myst_dxio_descriptors);
+	variant_get_dxio_descriptors(dxio_descs, dxio_num);
 	*ddi_descs = myst_ddi_descriptors;
 	*ddi_num = ARRAY_SIZE(myst_ddi_descriptors);
 }
diff --git a/src/mainboard/google/myst/variants/baseboard/Makefile.inc b/src/mainboard/google/myst/variants/baseboard/Makefile.inc
index d5e133a9ec..10b34e3379 100644
--- a/src/mainboard/google/myst/variants/baseboard/Makefile.inc
+++ b/src/mainboard/google/myst/variants/baseboard/Makefile.inc
@@ -4,8 +4,10 @@ bootblock-y += gpio.c
 
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += gpio.c
+ramstage-y += port_descriptors.c
 
 romstage-y += gpio.c
+romstage-y += port_descriptors.c
 
 verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += gpio.c
 
diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/port_descriptors.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/port_descriptors.h
new file mode 100644
index 0000000000..7742bed288
--- /dev/null
+++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/port_descriptors.h
@@ -0,0 +1,70 @@
+#ifndef __BASEBOARD_PORT_DESCRIPTORS_H__
+#define __BASEBOARD_PORT_DESCRIPTORS_H__
+
+#define WWAN_DEVFN PCIE_GPP_2_1_DEVFN
+#define WLAN_DEVFN PCIE_GPP_2_2_DEVFN
+#define SD_DEVFN PCIE_GPP_2_3_DEVFN
+#define NVME_DEVFN PCIE_GPP_2_4_DEVFN
+
+#define WWAN_DXIO_DESCRIPTOR {                   \
+	.engine_type = UNUSED_ENGINE,            \
+	.port_present = true,                    \
+	.start_lane = 13,                        \
+	.end_lane = 13,                          \
+	.device_number = PCI_SLOT(WWAN_DEVFN),   \
+	.function_number = PCI_FUNC(WWAN_DEVFN), \
+	.link_speed_capability = GEN3,           \
+	.turn_off_unused_lanes = true,           \
+	.clk_req = CLK_REQ2,                     \
+}
+
+#define WLAN_DXIO_DESCRIPTOR {                   \
+	.engine_type = PCIE_ENGINE,              \
+	.port_present = true,                    \
+	.start_lane = 14,                        \
+	.end_lane = 14,                          \
+	.device_number = PCI_SLOT(WLAN_DEVFN),   \
+	.function_number = PCI_FUNC(WLAN_DEVFN), \
+	.link_speed_capability = GEN3,           \
+	.turn_off_unused_lanes = true,           \
+	.clk_req = CLK_REQ0,                     \
+}
+
+#define SD_DXIO_DESCRIPTOR {                   \
+	.engine_type = PCIE_ENGINE,            \
+	.port_present = true,                  \
+	.start_lane = 15,                      \
+	.end_lane = 15,                        \
+	.device_number = PCI_SLOT(SD_DEVFN),   \
+	.function_number = PCI_FUNC(SD_DEVFN), \
+	.link_speed_capability = GEN1,         \
+	.turn_off_unused_lanes = true,         \
+	.link_hotplug = HOTPLUG_ENHANCED,      \
+	.clk_req = CLK_REQ1,                   \
+}
+
+#define NVME_DXIO_DESCRIPTOR {                   \
+	.engine_type = PCIE_ENGINE,              \
+	.port_present = true,                    \
+	.start_lane = 16,                        \
+	.end_lane = 19,                          \
+	.device_number = PCI_SLOT(NVME_DEVFN),   \
+	.function_number = PCI_FUNC(NVME_DEVFN), \
+	.link_speed_capability = GEN_MAX,        \
+	.turn_off_unused_lanes = true,           \
+	.clk_req = CLK_REQ3,                     \
+}
+
+#define EMMC_DXIO_DESCRIPTOR {                   \
+	.engine_type = PCIE_ENGINE,              \
+	.port_present = true,                    \
+	.start_lane = 16,                        \
+	.end_lane = 16,                          \
+	.device_number = PCI_SLOT(NVME_DEVFN),   \
+	.function_number = PCI_FUNC(NVME_DEVFN), \
+	.link_speed_capability = GEN_MAX,        \
+	.turn_off_unused_lanes = true,           \
+	.clk_req = CLK_REQ3,                     \
+}
+
+#endif //__BASEBOARD_PORT_DESCRIPTORS_H__
diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
index 6446763152..540a0c86aa 100644
--- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
@@ -7,18 +7,6 @@
 #include <platform_descriptors.h>
 #include <soc/pci_devs.h>
 
-#define WWAN_DEVFN	PCIE_GPP_2_1_DEVFN
-#define WLAN_DEVFN	PCIE_GPP_2_2_DEVFN
-#define SD_DEVFN	PCIE_GPP_2_3_DEVFN
-#define NVME_DEVFN	PCIE_GPP_2_4_DEVFN
-
-enum dxio_port_id {
-	DXIO_WWAN,
-	DXIO_WLAN,
-	DXIO_SD,
-	DXIO_STORAGE
-};
-
 /* This function provides base GPIO configuration table. */
 void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size);
 
@@ -43,4 +31,9 @@ void variant_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size)
 /* This function provides GPIO settings for TPM i2c bus. */
 void variant_tpm_gpio_table(const struct soc_amd_gpio **gpio, size_t *size);
 
+/*
+ * This function allows a variant to override dxio descriptors passed to the FSP.
+ */
+void variant_get_dxio_descriptors(const fsp_dxio_descriptor **dxio_descriptor, size_t *num);
+
 #endif /* __BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/myst/variants/baseboard/port_descriptors.c b/src/mainboard/google/myst/variants/baseboard/port_descriptors.c
new file mode 100644
index 0000000000..b26f300116
--- /dev/null
+++ b/src/mainboard/google/myst/variants/baseboard/port_descriptors.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <baseboard/port_descriptors.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <soc/platform_descriptors.h>
+
+enum baseboard_dxio_port_id {
+	BASEBOARD_DXIO_WWAN,
+	BASEBOARD_DXIO_WLAN,
+	BASEBOARD_DXIO_SD,
+	BASEBOARD_DXIO_STORAGE,
+};
+
+static fsp_dxio_descriptor myst_dxio_descriptors[] = {
+	[BASEBOARD_DXIO_WWAN] = WWAN_DXIO_DESCRIPTOR,
+	[BASEBOARD_DXIO_WLAN] = WLAN_DXIO_DESCRIPTOR,
+	[BASEBOARD_DXIO_SD] = SD_DXIO_DESCRIPTOR,
+	/* This value modified at runtime, default to emmc */
+	[BASEBOARD_DXIO_STORAGE] = EMMC_DXIO_DESCRIPTOR,
+};
+
+__weak void variant_get_dxio_descriptors(const fsp_dxio_descriptor **dxio_descriptor, size_t *num)
+{
+	if (fw_config_is_provisioned() && fw_config_probe(FW_CONFIG(STORAGE, NVME))) {
+		printk(BIOS_DEBUG, "Enabling NVMe.\n");
+		myst_dxio_descriptors[BASEBOARD_DXIO_STORAGE] = (fsp_dxio_descriptor)NVME_DXIO_DESCRIPTOR;
+	} else {
+		printk(BIOS_DEBUG, "Defaulting to eMMC.\n");
+	}
+	*dxio_descriptor = myst_dxio_descriptors;
+	*num = ARRAY_SIZE(myst_dxio_descriptors);
+}