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authorNick Vaccaro <nvaccaro@google.com>2020-09-30 15:43:41 -0700
committerNick Vaccaro <nvaccaro@google.com>2020-10-05 18:03:38 +0000
commitbe34b500a623068ec579e4f32881adf0e663089b (patch)
treefd5a1853e1f2777cb8b9dfc8522c02a7f695dee6
parent53b99a84a59b8eab1e17498e9dd217a0235b4174 (diff)
mb/google/hatch,dedede,volteer: enable CHROMEOS_DRAM_PART_NUMBER_IN_CBI
Enable CHROMEOS_DRAM_PART_NUMBER_IN_CBI on hatch, dedede, and volteer to use the common version of mainboard_get_dram_part_num(). Remove duplicate instances of mainboard_get_dram_part_num(). BUG=b:169789558, b:168724473 TEST="emerge-volteer coreboot && emerge-hatch coreboot && emerge-dedede coreboot" and verify it builds. Change-Id: I4e29d3e7ef0f3370eab9a6996a5c4a21a636b40e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45883 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/dedede/Kconfig1
-rw-r--r--src/mainboard/google/dedede/romstage.c13
-rw-r--r--src/mainboard/google/hatch/Kconfig1
-rw-r--r--src/mainboard/google/hatch/romstage_spd_cbfs.c25
-rw-r--r--src/mainboard/google/volteer/Kconfig1
-rw-r--r--src/mainboard/google/volteer/romstage.c12
6 files changed, 3 insertions, 50 deletions
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index bd7d36e0fc..e1b713677d 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -37,6 +37,7 @@ config CHROMEOS
bool
default y
select CHROMEOS_CSE_BOARD_RESET_OVERRIDE
+ select CHROMEOS_DRAM_PART_NUMBER_IN_CBI
select EC_GOOGLE_CHROMEEC_SWITCHES
select GBB_FLAG_FORCE_DEV_SWITCH_ON
select GBB_FLAG_FORCE_DEV_BOOT_USB
diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c
index e143f700cd..02ebfac426 100644
--- a/src/mainboard/google/dedede/romstage.c
+++ b/src/mainboard/google/dedede/romstage.c
@@ -21,16 +21,3 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated);
}
-
-const char *mainboard_get_dram_part_num(void)
-{
- static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE];
-
- if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0],
- sizeof(part_num_store)) < 0) {
- printk(BIOS_ERR, "No DRAM part number in CBI!\n");
- return NULL;
- }
-
- return part_num_store;
-}
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index ecf156f266..257ad77a42 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -47,6 +47,7 @@ if BOARD_GOOGLE_HATCH_COMMON
config CHROMEOS
bool
default y
+ select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if !ROMSTAGE_SPD_SMBUS
select EC_GOOGLE_CHROMEEC_SWITCHES
select GBB_FLAG_FORCE_DEV_SWITCH_ON
select GBB_FLAG_FORCE_DEV_BOOT_USB
diff --git a/src/mainboard/google/hatch/romstage_spd_cbfs.c b/src/mainboard/google/hatch/romstage_spd_cbfs.c
index b8937de91b..f3c38bbf4f 100644
--- a/src/mainboard/google/hatch/romstage_spd_cbfs.c
+++ b/src/mainboard/google/hatch/romstage_spd_cbfs.c
@@ -56,28 +56,3 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
}
-
-const char *mainboard_get_dram_part_num(void)
-{
- static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE];
- static enum {
- PART_NUM_NOT_READ,
- PART_NUM_AVAILABLE,
- PART_NUM_NOT_IN_CBI,
- } part_num_state = PART_NUM_NOT_READ;
-
- if (part_num_state == PART_NUM_NOT_READ) {
- if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0],
- sizeof(part_num_store)) < 0) {
- printk(BIOS_ERR, "No DRAM part number in CBI!\n");
- part_num_state = PART_NUM_NOT_IN_CBI;
- } else {
- part_num_state = PART_NUM_AVAILABLE;
- }
- }
-
- if (part_num_state == PART_NUM_NOT_IN_CBI)
- return NULL;
-
- return part_num_store;
-}
diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
index f32b54a609..58ff4eb270 100644
--- a/src/mainboard/google/volteer/Kconfig
+++ b/src/mainboard/google/volteer/Kconfig
@@ -35,6 +35,7 @@ config CHROMEOS
bool
default y
select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU
+ select CHROMEOS_DRAM_PART_NUMBER_IN_CBI
select EC_GOOGLE_CHROMEEC_SWITCHES
select GBB_FLAG_FORCE_DEV_SWITCH_ON
select GBB_FLAG_FORCE_DEV_BOOT_USB
diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c
index 51a4ebc75d..720ab7f3a1 100644
--- a/src/mainboard/google/volteer/romstage.c
+++ b/src/mainboard/google/volteer/romstage.c
@@ -28,15 +28,3 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
meminit_ddr(mem_cfg, board_cfg, &spd_info, half_populated);
}
-
-const char *mainboard_get_dram_part_num(void)
-{
- static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE];
-
- if (google_chromeec_cbi_get_dram_part_num(part_num_store,
- sizeof(part_num_store)) < 0) {
- printk(BIOS_ERR, "ERROR: Couldn't obtain DRAM part number from CBI\n");
- return NULL;
- }
- return part_num_store;
-}