diff options
| author | Werner Zeh <werner.zeh@siemens.com> | 2021-06-16 12:30:36 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-21 05:35:58 +0000 |
| commit | bab5d5008b6509bcd805f73e6f874fa8c094177f (patch) | |
| tree | dff1d67be215378c71dfc8891e4ca490770120fa | |
| parent | 6a103907f166fc6659162942cc6745ac555c12de (diff) | |
soc/intel/elkhartlake: Expose In-Band ECC config to mainboard
Elkhart Lake provides a feature called "In-Band ECC" which uses a piece
of system DRAM to store the ECC information in. There are a few
parameters in FSP-M to set this feature up as needed.
This patch adds code to expose these parameters to the devicetree so
that they can be configured on mainboard level as needed.
Change-Id: I7a4953d7b35277de01daff04211450e3d1bd8103
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55668
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/elkhartlake/chip.h | 21 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/romstage/fsp_params.c | 15 |
2 files changed, 36 insertions, 0 deletions
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index c2faddc2b9..e4c8e38fef 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -24,6 +24,24 @@ #define MAX_HD_AUDIO_SNDW_LINKS 4 #define MAX_HD_AUDIO_SSP_LINKS 6 +/* Define config parameters for In-Band ECC (IBECC). */ +#define MAX_IBECC_REGIONS 8 + +enum ibecc_mode { + IBECC_PER_REGION, + IBECC_NONE, + IBECC_ALL +}; + +struct ehl_ibecc_config { + bool enable; + bool parity_en; + enum ibecc_mode mode; + bool region_enable[MAX_IBECC_REGIONS]; + uint16_t region_base[MAX_IBECC_REGIONS]; + uint16_t region_mask[MAX_IBECC_REGIONS]; +}; + struct soc_intel_elkhartlake_config { /* Common struct containing soc config data required by common code */ @@ -68,6 +86,9 @@ struct soc_intel_elkhartlake_config { /* Memory Thermal Throttling: Enable - Default (0) / Disable (1) */ bool MemoryThermalThrottlingDisable; + /* In-Band ECC (IBECC) configuration */ + struct ehl_ibecc_config ibecc; + /* FuSa (Functional Safety): Disable - Default (0) / Enable (1) */ bool FuSaEnable; diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c index 4f8657abcc..449d14ef65 100644 --- a/src/soc/intel/elkhartlake/romstage/fsp_params.c +++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c @@ -107,6 +107,21 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Processor Early Power On Configuration FCLK setting */ m_cfg->FClkFrequency = 0x1; + + /* Ib-Band ECC configuration */ + if (config->ibecc.enable) { + m_cfg->Ibecc = !!config->ibecc.enable; + m_cfg->IbeccParity = !!config->ibecc.parity_en; + m_cfg->IbeccOperationMode = config->ibecc.mode; + if (m_cfg->IbeccOperationMode == IBECC_PER_REGION) { + FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionEnable, + config->ibecc.region_enable); + FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionBase, + config->ibecc.region_base); + FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionMask, + config->ibecc.region_mask); + } + } } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |