summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorPatrick Rudolph <patrick.rudolph@9elements.com>2023-03-20 08:43:21 +0100
committerLean Sheng Tan <sheng.tan@9elements.com>2023-03-21 11:26:16 +0000
commitb8fc81d8580e6fe8b0a274930d42c53f81d94011 (patch)
treeed7c5b0ad7634d8a1438707f4871d685b9135ff1
parentfb4fdac64cfe05c9642cd93129dbbf23dde4ac51 (diff)
mb/intel/adlrvp: Enable onboard GBE
The ADL RVP has an i219 PHY connected to the PCH internal MAC. Enable it to have working ethernet on the board. Test: Added GBE region and verified that the PCI device 00:1f.6 is working. Change-Id: I2ca1af00ae4564a04f5388cd3734bb735d87352e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--src/mainboard/intel/adlrvp/Kconfig1
-rw-r--r--src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb6
2 files changed, 6 insertions, 1 deletions
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig
index 7a5f1ecc0d..6a616e8719 100644
--- a/src/mainboard/intel/adlrvp/Kconfig
+++ b/src/mainboard/intel/adlrvp/Kconfig
@@ -23,6 +23,7 @@ config BOARD_INTEL_ADLRVP_P
select MAINBOARD_USES_IFD_EC_REGION
select SOC_INTEL_ALDERLAKE_PCH_P
select GEN3_EXTERNAL_CLOCK_BUFFER
+ select MAINBOARD_USES_IFD_GBE_REGION
config BOARD_INTEL_ADLRVP_P_EXT_EC
select BOARD_INTEL_ADLRVP_COMMON
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb
index e58e9fbdce..3254141533 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb
@@ -1,4 +1,8 @@
chip soc/intel/alderlake
- device domain 0 on end
+ register "pcie_clk_config_flag[6]" = "PCIE_CLK_LAN"
+
+ device domain 0 on
+ device ref gbe on end # i219
+ end
end