diff options
| author | Edward O'Callaghan <quasisec@google.com> | 2019-12-18 11:04:20 +1100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-20 07:23:34 +0000 |
| commit | b61f33cd484ece8c86acdce2740d0ab4018f3f30 (patch) | |
| tree | a4eb30208b4225af548c7493cdccde16c44793be | |
| parent | d4823664a895546ac699cc70e41a94f943b364f8 (diff) | |
mainboard/google/puff: Enable pcie7 ep in dt
Missing bus init for RTL8111H ethernet chip hanging on bus.
V.2: Include admendments from Kangheui.
BRANCH=none
BUG=b:146437819
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I22aba312f183ea05eeb81d326ca0c05ce340a2e8
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
| -rw-r--r-- | src/mainboard/google/hatch/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/variants/puff/overridetree.cb | 8 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 90c5ed3427..3427ced44d 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -22,6 +22,8 @@ config BOARD_GOOGLE_BASEBOARD_HATCH select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE select SOC_INTEL_COMETLAKE select SYSTEM_TYPE_LAPTOP + select RT8168_GET_MAC_FROM_VPD if BOARD_GOOGLE_PUFF + select RT8168_SET_LED_MODE if BOARD_GOOGLE_PUFF if BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index ca6c818128..d362b22770 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -103,6 +103,13 @@ chip soc/intel/cannonlake }, }" + # PCIe port 7 for LAN + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + # Uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "6" + register "PcieClkSrcClkReq[0]" = "0" + # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B" @@ -134,6 +141,7 @@ chip soc/intel/cannonlake end end #I2C #4 device pci 1a.0 on end # eMMC + device pci 1c.6 on end # PCI Express Port 7, RTL8111H Ethernet NIC. device pci 1e.3 off end # GSPI #1 end |