diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-12-11 10:08:34 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-13 14:26:23 +0000 |
| commit | b433470b02e773c182adffde654d3fcbb2b9f9b5 (patch) | |
| tree | 7643ab7e5c7894b8173503a1c6b90c42f3429807 | |
| parent | eb99f62456fc44f4db6c2f08316b4b56082dbfa6 (diff) | |
soc/cavium/cn81xx: Use write{32,64}p()
Change-Id: I9c94f45264f541ce0849a53245534a10aaa5d854
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
| -rw-r--r-- | src/soc/cavium/cn81xx/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/cavium/cn81xx/cpu.c b/src/soc/cavium/cn81xx/cpu.c index 14aff58a2a..43b64d5430 100644 --- a/src/soc/cavium/cn81xx/cpu.c +++ b/src/soc/cavium/cn81xx/cpu.c @@ -72,7 +72,7 @@ size_t start_cpu(size_t cpu, void (*entry_64)(size_t core_id)) return 1; /* Write the address of the main entry point */ - write64((void *)MIO_BOOT_AP_JUMP, (uintptr_t)secondary_init); + write64p(MIO_BOOT_AP_JUMP, (uintptr_t)secondary_init); /* Get coremask of cores in reset */ const uint64_t reset = read64p(RST_PP_RESET); @@ -86,7 +86,7 @@ size_t start_cpu(size_t cpu, void (*entry_64)(size_t core_id)) printk(BIOS_DEBUG, "CPU: Taking core %zu out of reset.\n", cpu); /* Release core from reset */ - write64((void *)RST_PP_RESET, reset & ~coremask); + write64p(RST_PP_RESET, reset & ~coremask); /* Wait for cores to finish coming out of reset */ udelay(1); |