mb/intel/adlrvp_m: Enable CR50 TPM support over SPI

Add Kconfig options and enable TPM device in devicetree

BUG=None
TEST=Booted the image and checked the successful TPM
communication in verstage,romstage & ramstage from
coreboot logs.

Signed-off-by: Thejaswani Puta thejaswani.putta@intel.com <thejaswani.putta@intel.com>
Change-Id: Icaedf9f17e35e82c35cbabd6d2938c167e42e9e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>

4 files changed, 51 insertions, 4 deletions

diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig
index f62292134d..eed3b303ea 100644
--- a/src/mainboard/intel/adlrvp/Kconfig
+++ b/src/mainboard/intel/adlrvp/Kconfig
@@ -22,6 +22,9 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_I2C_MAX98373
 	select FW_CONFIG if BOARD_INTEL_ADLRVP_M_EXT_EC
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI if BOARD_INTEL_ADLRVP_M_EXT_EC
+	select MAINBOARD_HAS_TPM2 if BOARD_INTEL_ADLRVP_M_EXT_EC
+	select MAINBOARD_HAS_SPI_TPM_CR50 if BOARD_INTEL_ADLRVP_M_EXT_EC
+	select SPI_TPM if BOARD_INTEL_ADLRVP_M_EXT_EC
 
 config CHROMEOS
 	select GBB_FLAG_FORCE_DEV_SWITCH_ON
@@ -91,11 +94,18 @@ endchoice
 
 config VBOOT
 	select VBOOT_LID_SWITCH
-	select VBOOT_MOCK_SECDATA
+	select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC
 	select EC_GOOGLE_CHROMEEC_SWITCHES if ADL_CHROME_EC
 	select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_M_EXT_EC
 
 config UART_FOR_CONSOLE
 	int
 	default 0
+
+config DRIVER_TPM_SPI_BUS
+	default 0x2 if BOARD_INTEL_ADLRVP_M_EXT_EC
+
+config TPM_TIS_ACPI_INTERRUPT
+	int
+	default 67 if BOARD_INTEL_ADLRVP_M_EXT_EC  # GPE0_DW2_3 (GPP_E3)
 endif
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index b28f387e2b..65a6cac1c4 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -6,6 +6,19 @@ fw_config
 end
 chip soc/intel/alderlake
 
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	# This disables autonomous GPIO power management, otherwise
+	# old cr50 FW only supports short pulses.
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
+
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this
 	# route. i.e. If this route changes then the affected GPE
@@ -107,14 +120,14 @@ chip soc/intel/alderlake
 
 	register "SerialIoGSpiMode" = "{
 		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
-		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
 		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
 		[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
 	}"
 
 	register "SerialIoGSpiCsMode" = "{
 		[PchSerialIoIndexGSPI0] = 0,
-		[PchSerialIoIndexGSPI1] = 0,
+		[PchSerialIoIndexGSPI1] = 1,
 		[PchSerialIoIndexGSPI2] = 0,
 		[PchSerialIoIndexGSPI3] = 0,
 	}"
@@ -141,6 +154,10 @@ chip soc/intel/alderlake
 	# Intel Common SoC Config
 	register "common_soc_config" = "{
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.gspi[1] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
 		.i2c[0] = {
 			.speed = I2C_SPEED_FAST,
 		},
@@ -353,6 +370,14 @@ chip soc/intel/alderlake
 		device ref uart0 on end
 		device ref gspi0 on end
 		device ref p2sb on end
+		device pci 1e.3 on
+			chip drivers/spi/acpi
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "compat_string" = ""google,cr50""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)"
+				device spi 0 on end
+			end
+		end # GSPI1
 		device ref hda on
 			chip drivers/intel/soundwire
 				device generic 0 on
diff --git a/src/mainboard/intel/adlrvp/early_gpio_m.c b/src/mainboard/intel/adlrvp/early_gpio_m.c
index 3b60e248d0..79349b1be6 100644
--- a/src/mainboard/intel/adlrvp/early_gpio_m.c
+++ b/src/mainboard/intel/adlrvp/early_gpio_m.c
@@ -99,6 +99,18 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1),
 	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1),
 	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1),
+
+	/* H1_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT),
+	/* TPM */
+	/* F16 : GSPI1_CS0N */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
+	/* F11 : GSPI1_CLK */
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
+	/* F13 : GSPI1_MISO */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
+	/* F12 : GSPI1_MOSI */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
 };
 
 static const struct pad_config early_uart_gpio_table[] = {
diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c
index d5eeffa1c4..11686be203 100644
--- a/src/mainboard/intel/adlrvp/gpio_m.c
+++ b/src/mainboard/intel/adlrvp/gpio_m.c
@@ -159,7 +159,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
 
 	/* S7 : SNDW4_DATA */
-	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2)
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
 };
 
 void variant_configure_gpio_pads(void)